Freescale Semiconductor MCF5441X User manual

Freescale Semiconductor Inc.
Microcontroller Solutions Group
MCF5441X Tower Module
User Manual
Rev. 1.1

MCF5441X Tower Module Hardware Specification Page 2 of 31
Contents
1PURPOSE.........................................................................................................................................................................3
2REFERENCE DOCUMENTS ........................................................................................................................................3
3OVERVIEW.....................................................................................................................................................................3
3.1 MCF5441X OVERVIEW......................................................................................................................................................3
3.2 TWR-MCF5441X OVERVIEW...........................................................................................................................................5
4HARDWARE SPECIFICATION...................................................................................................................................6
4.1 MICROCONTROLLER...........................................................................................................................................................6
4.2 CLOCKING..........................................................................................................................................................................7
4.3 SYSTEM POWER .................................................................................................................................................................8
4.4 DEBUG INTERFACE.............................................................................................................................................................8
4.4.1 Stardard BDM...........................................................................................................................................................8
4.4.2 OSBDM Bootloader Mode ......................................................................................................................................10
4.4.3 OSBDM Debug Interface ........................................................................................................................................10
4.5 RS232 HEADERS..............................................................................................................................................................10
4.6 SDRAM INTERFACE........................................................................................................................................................11
4.7 NAND FLASH MEMORY INTERFACES..............................................................................................................................11
4.8 ACCELEROMETER ............................................................................................................................................................11
4.9 POTENTIOMETER..............................................................................................................................................................12
4.10 TEMPERATURE SENSOR .................................................................................................................................................13
4.11 AUDIO HEADERS (DAC)................................................................................................................................................13
4.12 USER INTERFACES..........................................................................................................................................................13
4.13 RESET CONFIGURATION .................................................................................................................................................14
4.13.1 Default Configuration (J5: 3-4 and 1-2 = ON:ON)..............................................................................................15
4.13.2 Parallel Configuration (J5: 3-4 and 1-2 = ON:OFF)...........................................................................................16
4.13.3 Serial Configuration (J5 OFF:OFF) ....................................................................................................................17
4.14 JUMPERS,SWITCHES ......................................................................................................................................................20
4.15 CUT/TRACE PADS ..........................................................................................................................................................21

MCF5441X Tower Module Hardware Specification Page 3 of 31
1Purpose
This document provides design and usage information for the Freescale TWR_M54418 evaluation,
development and reference platform.
The TWR-MCF5441X platform provides and evaluation system for the Freescale MCF5441x ColdFire
V4m embedded microprocessor family. The MCF54418 is the superset device in the family and is the
processor featured on this platform. This allows evaluation and development for the entire MCF5441x
family on an existing Tower system.
2Reference Documents
MCF54418 Reference Manual
TWR-M54418 Quick Start Guide
TWR-M54418 Schematics
MCF54418 Data Sheet
MMA7361L Data Sheet –Three Axis Accelerometer
DDR2 SDRAM Specification (JESD79-2C)
Tower Overview Presentation
Tower Mechanical Specification
DS18B20 Data Sheet –Temperature Sensor
DS18B20 Application Note 120: Using an API to Control the DS1WM 1-Wire Bus Master
TS2007 Data Sheet –Class D audio power amplifier with 6-12dB gains.
MC9S08JM60 Reference Manual
Cut/Trace Pads
3Overview
3.1 MCF5441x Overview
The following is a brief summary of the functional blocks in the MCF5441x superset device.
Version 4 ColdFire Core with MMU and EMAC
oCPU @250 MHz
16 KBytes instruction cache and 16 KBytes data cache

MCF5441X Tower Module Hardware Specification Page 4 of 31
64 Kbytes internal SRAM
Support for booting from SPI-compatible flash
Support for booting from NAND flash
Crossbar switch technology (XBS) for concurrent access to peripherals or RAM from multiple
bus masters
64 channel DMA controller
DDR1/DDR2 Controller
USB 2.0 On-the-Go controller with ULPI support
Two smart card ports
Two 10/100 Ethernet Controllers
IEEE 1588-2002
SDHC host controller
Two CAN modules
Cryptographic acceleration unit (CAU)
Random number generator
Synchronous serial interface (SSI)
Four 32-bit timers with DMA support
Four DMA-supported serial peripheral interface (DSPI)
Ten UARTs
Six I2C bus interface
12-bit ADC
A multi-channel PWM
Two DACs

MCF5441X Tower Module Hardware Specification Page 5 of 31
3.2 TWR-MCF5441X Overview
The TWR-MCF5441X provides hardware to evaluate as many of the configurations of the MCF5441x
family as possible. The TWR-MCF5441X features:
Tower compatible processor board
MCF54418 in a 256 MAPBGA package
DDR2 SDRAM (128 MByte)
A NAND Flash memory device (256MByte)
Two RS232 headers (2x5 pins)
Standard 26-pin BDM Header

MCF5441X Tower Module Hardware Specification Page 6 of 31
MC9S08JM60 based Open Source BDM (OSBDM) circuit
Standard 6-pin BKGD/MS Header
MMA7361L three-axis accelerometer
Wire Digital Temperature Sensor
Four LEDs
DIP Switches and push buttons for user input
Potentiometer
Audio Speaker (Header Only) uses LM4889 audio power amplifier.
4Hardware Specification
This section provides specification details for the TWR-MCF5441X board.
4.1 Microcontroller
The microcontroller on the TWR-MCF5441X will be a member of the highly-integrated 32-bit
microprocessor family based on the Coldfire V4m with MMU, EMAC, and CAU units.

MCF5441X Tower Module Hardware Specification Page 7 of 31
MCF54418
ColdFire® V4m
Microprocessor
256 MAPBGA
1.2V 1.8V 3.3V
DDR2
(128 MB)
Open-Source
BDM Interface
26-Pin Header
PCIe Expansion Connectors
Timers, IRQs, FlexBus, UARTs, I2C,
SPI, USB, Ethernet, SSI, SDHC,
CAN, ADC, DAC, mcPWM, etc.
USB
Mini-AB
SDRAM Interface
Freescale Silicon External Connectors Memory Devices Interface ICs Power Rails
Reset, GPIO
Power Switch and
Regulation
NAND Flash
(2Gbit)
ADC
UART
5.0V 3.3V
5.0V
UART
BDM
32.768 kHz
(RTC)
25 MHz
(RefClk)
UART DAC
Speaker
Header
ADC
MMA7361L 3-axis
Accelerometer
Temp Sensor
(DS18B20)
1-Wire
LED
LED
LED
LED
Dual
RS-232
2x5 Pin
2x5 Pin
NFC
High Speed
Analog
Switches
FEC RMII
USB ULPI
UARTs, Flexbus, I2C, CAN, etc...
4.2 Clocking
The MCF54418 requires 2 clocks sources in order to enable proper internal timing. A 25 MHz crystal is
connected to EXTAL to generate several clocks including the CPU clock and peripherals’ clock. The
EXTAL can also use a 50MHz clock from the Tower Elevator (selected via jumper J2). A 32.768 kHz
crystal is connected to RTC_XTAL and RTC_EXTAL for Real-Time Clock usage.
Clock Selection
Pin
External clock source
1-2
Onboard 25Mhz clock
2-3
Table 1 - J2 Headers
The MCF54418’s core clock speed is default to 250 MHz on the TWR-MCF54418 platform. The DDR2
SDRAM bus speed is set at 250 MHz to generate a 500 MHz data rate. The system bus clock is set at
125MHz. All clock speeds such as CPU, SYSTEM, SDHC, USB and NAND can be programmable to desire
frequency with software modification and jumpers.

MCF5441X Tower Module Hardware Specification Page 8 of 31
To fully support the DDR2 interface a VCO of 500 MHz is required. In order to supply a VCO of
500MHz, the clock multiplier should be adjusted based on the input reference clock.
Clock Source
PLL Multiplier
SW1 Dip [7:8]
settings
50MHz
10x
0:0 (On:On)
25MHz
20x
1:1 (Off:Off)
Note: VCO must be in the range from 240-500 MHz. USB frequency must be 60MHz, SDHC frequency
must not be greater than 250MHz, and NAND frequency must not be greater than 80MHz.
4.3 System Power
The TWR-MCF5411X board is powered by +5V either from the OSBDM circuit (via the miniAB USB
connector) or the Tower Elevator power connections. Power regulation circuitry is capable of
providing 1.2V, 1.8V, and if needed 3.3V from either of the power source.
4.4 Debug Interface
TWR-MCF5441X provides two debug interfaces –a standard BDM and an Open Source BDM (OSBDM).
4.4.1 Stardard BDM
The primary debug port on the TWR-MCF5441X is referred to as the background debug module or
BDM. The standard 26-pin BDM header (J11) is provided on the TWR-M5441X for attachment of an
external BDM control interface.

MCF5441X Tower Module Hardware Specification Page 9 of 31
J11
Function
J11
Function
1
RSTOUT_b
2
TMS/BKPT_b
3
GND
4
DSCLK
5
GND
6
TCK
7
RSTIN_b
8
TDI/DSI
9
3V3
10
TDO/DSO
11
GND
12
PST3
13
PST2
14
PST1
15
PST0
16
DDATA3
17
DDATA2
18
DDATA1
19
DDATA0
20
GND
21
NC
22
NC
23
GND
24
PSTCLK/OSBDM
25
3V3
26
NC
Table 2 - BDM Headers
The MCF5441x also features IEEE 1149.1 Test Access Port (JTAG) test logic that can be used for
boundary-scan testability. The access pins for JTAG are multiplexed over the BDM control signals and
are available on J11.
The JTAG_EN input signal to the MCF5441x determines the debug mode: BDM or JTAG. This signal is
controllable by J6 as shown below:
Debug Mode
Pin
JTAG
No shunt
BDM
Shunt on 1-2
Table 3 - J6 Headers
The TCLK and PSTCLK signals are the only two multiplexed signals that switch input/output state,
depending on which debug mode is selected. In BDM mode, the PSTCLK is an output from the
MCF5441x to the external BDM control interface. In JTAG mode, TCLK is the test clock input. The
standard 26-pin BDM header defines pin 24 as PSTCLK. A common practice is to place TCLK on pin 6 of
this header. J8 is available to control the routing of the multiplexed TCLK_PSTCLK signal to the 26-pin
debug header (J11) as shown below.
TCLK_PSTCLK Routing
Pin
TCK/PSTCLK on J11[pin 24]
1-2
TCK/PSTCLK on J11[pin 6]
2-3
Table 4 - J8 Headers

MCF5441X Tower Module Hardware Specification Page 10 of 31
4.4.2 OSBDM Bootloader Mode
The MC9S08JM60 device used in the OSBMD circuit is preprogrammed with OSBDM debugger
firmware and a USB Bootloader. Jumper J10 determines which application will run following a power-
on reset. If Bootloader Mode is chosen (Jumper ON J10), the bootloader will executed, allowing in-
circuit reprogramming of the JM60 flash memory via USB. This enables the OSBDM firmware to be
upgraded by the user when upgrades become available. For details on the USB Bootloader, refer to
Application Note AN3561 on the Freescale website (http://www.freescale.com).
The USB Bootloader communicates with a GUI application running on a host PC. The GUI application
can be found on the Freescale website; search keyword “JM60 GUI”. Refer to section 2.5 and 3.3 of
AN3561 for details on installing and running the application.
Note:
The JM60 GUI Installer should be run before connecting the OSBDM in Bootloader Mode to a host USB
port. Otherwise, the JM60 USB device will not be recognized and the proper drivers will not be loaded.
4.4.3 OSBDM Debug Interface
The OSBDM circuit is designed so that it can program the on-board MCF54418 device. The steps
necessary to operate the OSBDM in this mode are listed here:
1. Ensure that J10 is not shunted (J10 holds JM60 in reset)
2. Connect J7 (2x3 header) from TWR-MCF54418 to target debug connector
Pi
n
Function
Pi
n
Function
1
BKDG/MS
2
5V
3
NC
4
RESET_b
5
NC
6
5V
Table 5 - J7 JM60 BKGD Headers
4.5 RS232 Headers
The MCF54418 includes ten UART modules. The TWR-M5441X provides two RS232 transceivers on
UART0 and UART4. Two 2x5 pin headers are provided allowing access to the RS232 interfaces - J1
(UART0) and J3 (UART4). A 2x5 adaptor to Female DB9 serial cable must be used in order to establish
serial communication.

MCF5441X Tower Module Hardware Specification Page 11 of 31
Pi
n
Function
Pi
n
Function
1
No Connect
2
No Connect
3
TXD
4
CTS
5
RXD
6
RTS
7
No Connect
8
No Connect
9
GND
10
3.3V
Table 6 - J1 & J3
4.6 SDRAM Interface
The MCF5441x is capable of supporting 256MB DDR2-500 1.8V SDRAM at 250MHz SDRAM Clock. To
reduce cost, the TWR-M54418 uses an 8-bit memory bus to interface to 128MB Micron MT47H128M8
DDR2 SDRAM.
4.7 NAND Flash Memory Interfaces
The TWR-M54418 uses a 16-bit 2Gbit 48 pin TSOP NAND Flash device (MT29F2G16A). The NAND Flash
device may uses up to 256MB (2048 blocks at 64 pages per block). The first four pages of block 0 may
use for boot code with an 8-bit bus interface. The NAND signals are shared with FlexBus signals. Pin
Assignments must be set correctly for access to work properly for each Mode: NAND or FlexBus. The
MCF5441x is capable of booting from NAND Flash Memory device.
4.8 Accelerometer
An MMA7361L accelerometer is connected to three ADC inputs. There are 4 GPIO signals used to
configure the MMA7361L that are optional on the TWR-MCF5441X. The MMA7361L is wired as shown
here (as recommended in the MMA7361L Data Sheet):

MCF5441X Tower Module Hardware Specification Page 12 of 31
Figure 1 - MMA7361L Connection Diagram
By default the control signals are not connected, but can be enabled using Cut-Trace pads. By default
the MMZ7361L is configured to operate in normal mode with 1.5g sensitivity and no self test
functionality.
The MMA7361L Accelerometer is connected as follows to the MCF54418 MPU:
Accelerometer
MCF54418
Configuration
Cut-Trace Pad
XOUT
ADC_IN0
CT3
YOUT
ADC_IN1
CT6
ZOUT
ADC_IN2
CT9
g-Select
PST[0]/GPIO2
CT7
nSleep
PST[1]/GPIO3
CT12
Self Test
PST[2]/GPIO4
CT4
0g-Detect
PST[3]/GPIO5
CT10
Table 7 - Accelerometer Connection to MCF54418
By default the analog signals from the accelerometer are connected to the ADC channels 0-2 of the
MCF54418. If desired the connection to the accelerometer can be disconnected and the ADC channels
of the MCF54418 can be connected to the edge connectors for use on a module connected to the
TWR-ELEV.
To change the connection of ADC 0, 1, and 2 use the Cut-Trace pads CT3, CT6, and CT9 respectively.
Using a tool with a razor blade tip sever the connection between the pads 1 and 2 of each required
Cut-Trace implementation. Using a solder iron make a connection between pad 1 and pad 3.
By default the control signals for the MMA7361L accelerometer are not connected to the MCF54418.
To change the connection of the control signals (G-Select, nSleep, Self Test, and 0g-Detect) use the
respective Cut-Trace pads: CT7, CT12, CT4, and CT10. Using a solder iron create a connection between
pads 1 and 3.
Note that it is not possible to disconnect the default signals routing (PST[3:0]) for the these signals,
they are used for OSBDM functionality.
For more details regarding the Cut-Trace pad options and the pad numbering refer to the Cut-Trace
Pad section of this document.
4.9 Potentiometer
The TWR-MCF5441X includes an on-board potentiometer to allow the user to simulate an analog
input.

MCF5441X Tower Module Hardware Specification Page 13 of 31
By default voltage level from the potentiometer is connected to the ADC channel 4 of the MCF54418.
If desired the connection to the potentiometer can be disconnected and the ADC channel of the
MCF54418 can be connected to the edge connectors for use on a module connected to the TWR-ELEV.
To change the connection of ADC 4 use the Cut-Trace pad CT14.
Using a tool with a razor blade tip sever the connection between the pads 1 and 2 of the CT14. Using
a solder iron make a connection between pad 1 and pad 3.
For more details regarding the Cut-Trace pad options and the pad numbering refer to the Cut-Trace
Pad section of this document.
4.10 Temperature Sensor
TWR-M54418 uses 1-wire interface (OWIO) to interact with temperature sensor Maxim DS18B20
digital thermometer. The sensor device is powered from TWR-MCF5441X’s 3.3V power circuit. The
Parasite-Powered method (where the power source is from data bus) is not used in this platform.
By default the One-Wire digital temperature sensor is connected to the OWIO port on the MCF54418.
Using Cut-Trace pad (CT15) the signal can be connected to the TWR-ELEV connector for connection to
additional One-Wire devices. This signal can also be used to control the operating mode of a CAN
transceiver on an external Tower System module. For the CAN use case, the will be configured as a
GPIO and should be disconnected from any One-Wire devices. To disconnect the signal from the on-
board temperature sensor cut the trace between pads 1 and 2 of CT15.
For more details regarding the Cut-Trace pad options and the pad numbering refer to the Cut-Trace
Pad section of this document.
4.11 Audio Headers (DAC)
The TWR-MCF5441X uses National Semiconductor LM4889 Audio Power Amplifier to drive signal from
DAC1_OUT up to 1W into an 8 speaker.
Pin
Function
1
Output +
2
Output -
Table 8 - J4 Headers
4.12 User Interfaces
Three push buttons:

MCF5441X Tower Module Hardware Specification Page 14 of 31
oIRQ1 (SW3)
oIRQ2 (SW5)
oMCU reset (SW2)
One 8-way DIP switch for controlling Parallel Reset Configuration
One 2-way DIP Switch for additional GPIOs (Assuming BDM DDATA[3:2] are disabled).
Four LEDs driven directly by MPU output pins.
The LEDs are concurrently connected to the LED’s and the edge connector for GPIO access to external
Tower System modules. If required the signals from the MCF54418 can be disconnected from either
the LED’s or the TWR-ELEV GPIO’s. The connection to the LEDs is made between pads 1 and 2. The
connection to the TWR-ELEV GPIO’s is made between pads 1 and 3. Refer to the table below for
details regarding which signal corresponds to which LED and TWR-ELEV GPIO.
MCF54418
Signal Name
LED
TWR-ELEV GPIO
Configuration
Cut-Trace Pad
GPIO_G0
LED1 (Amber)
GPIO9 (A9)
CT3
GPIO_G1
LED2 (Yellow)
GPIO7 (A11)
CT6
GPIO_G2
LED3 (Green)
GPIO1 (B21)
CT9
GPIO_G3
LED4 (Orange/Red)
GPIO5 (B52)
CT7
For more details regarding the Cut-Trace pad options and the pad numbering refer to the Cut-Trace
Pad section of this document.
4.13 Reset Configuration
The TWR-MCF5441X has three boot mode options:
Boot with default configuration constants specified in the RCON register
Boot with NAND/NOR with configuration data specified by the Flexbus FB_AD[7:0] pins
Boot with configuration data obtained from an external SPI memory through the serial boot
facility.
The boot modes are determined by the jumper configuration of J5 at reset. Placing a jumper on pins
1-2 of J5 causes BOOTMOD[0] to be low (0). Placing a jumper on pins 3-4 of J5 causes BOOTMOD[1] to
be low (0). In the table below “ON” implies that the respective jumper is shunted.

MCF5441X Tower Module Hardware Specification Page 15 of 31
BOOTMOD[1:0]
J5
3-4 : 1-2
Description
00
ON:ON
Boot from Flexbus with default (RCON)
01
ON:OFF
override default via data bus (FB_AD[7:0]) –NAND/FlexBus
The is the typical boot mode for the TWR-MCF5441X
10
OFF:ON
Override default and boot from serial boot facility with load
configuration and optional booting from internal SRAM. If
not booting from internal SRAM, serial RCON configuration
will decide the boot source at address 0 either from FlexBus
or NAND Flash.
11
OFF:OFF
Table 9 - J5 Headers
4.13.1 Default Configuration (J5: 3-4 and 1-2 = ON:ON)
If the BOOTMOD pins are 00 during reset, the MCF5441x’s RCON register determines the chip
configuration after reset, regardless of the states of the external data pins. The RCON register specifies
the following default configuration for the MCF5441x:
VCO clock is 50 MHz, CPU clock at 25 MHz
System bus clock is 12.5 MHz, FlexBus clock is 6.25 MHz

MCF5441X Tower Module Hardware Specification Page 16 of 31
4.13.2 Parallel Configuration (J5: 3-4 and 1-2 = ON:OFF)
If the BOOTMOD pins are 01 during reset, the MCF5441x configuration after reset is determined
according to the levels driven onto the FB_AD[7:0] pins. On the TWR-MCF5441X, the FB_AD[7:0] pins
are actively driven by two 4-bit buffers enabled when the MCF5441x RSTOUT signal is asserted. The
values driven by the buffer are set by the SW1 DIP switch settings. For SW1, a value of 0 implies that
the dip is switched “On”.
Override Pins in Reset
Function
SW1- DIP 1
Boot Memory
0 (Default)
NAND Flash
1
FlexBus
SW1-2
PLL mode
0
Disabled
1 (Default)
Enabled
SW1-3
Oscillator mode
0 (Default)
Crystal oscillator mode
1
Oscillator bypass mode
SW1-4
FB_ALE select
0
FB_TS_B
1 (Default)
FB_ALE
SW1-[6:5]
BOOT Port size
00
32-bit (32-bit muxed address)
01
8-bit (24-bit non-muxed address)
10 (Default)
16-bit (16-bit non-muxed address)
11
16-bit (16-bit non-muxed address)
SW1-[8:7]
PLL Multiplier
00 (Default)
Fvco = 10 x Fref
01
Fvco = 15 x Fref
10
Fvco = 16 x Fref
11
Fvco = 20 x Fref
Table 10 - SW1 8-way DIP switch

MCF5441X Tower Module Hardware Specification Page 17 of 31
4.13.3 Serial Configuration (J5 OFF:OFF)
If the BOOTMOD pins are 11 during reset, then the chip configuration after reset is determined by
data obtained from an external SPI memory through serial boot using the SBF_DI, SBF_DO, SBF_CS,
and SBF_CLK signals. The internal configuration signals are driven to reflect the data being received
from the external SPI memory to allow for module configuration. See Table below.
BYTE Address
Data Contents
0x0
{0000, BLDIV[3:0]}
0x1
BLL[7:0]
0x2
BLL[15:8]
0x3
RCON[7:0]
0x4
RCON[15:8]
0x5
RCON[23:16]
0x6
RCON[31:24]
Table 11 - Serial Boot Facility 7-BYTE Header

MCF5441X Tower Module Hardware Specification Page 18 of 31
Override Serial RCON
Function
SBF_RCON[31:30]
BOOT Port size
00
32-bit (32-bit muxed address)
01
8-bit (24-bit non-muxed address)
10
16-bit (16-bit non-muxed address)
11
16-bit (16-bit non-muxed address)
SBF_RCON[29]
Boot Memory
0
NAND Flash
1
FlexBus
SBF_RCON[28:27]
Reserved
SBF_RCON[26]
FB_ALE select
0
FB_TS
1
FB_ALE
SBF_RCON[25]
Oscillator mode
0
Crystal oscillator mode
1
Oscillator bypass mode
SBF_RCON[24]
PLL mode
0
Disabled
1
Enabled
SBF_RCON[23:22]
PLL Reference Divider (PLL_CR[REFDIV])
00
1
01
2
Override Serial RCON
Function
10
Reserved
11
Reserved
SBF_RCON[21:16]
PLL reference Clock Multiplier (PLL_CR[FBKDIV])
SBF_RCON[15]
FlexBus Half Clock Enable
0
FlexBus Runs at Fsys/2
1
FlexBus Runs at Fsys/4
SBF_RCON[14:10]
NFC Clock Frequency (PLL_DR[OUTDIV5])
SBF_RCON[9:5]
Internal Bus Clock Frequency (PLL_DR[OUTDIV5])
SBF_RCON[4:0]
Core Bus Clock Frequency (PLL_DR[OUTDIV5])
Table 12 - Serial Boot Facility RCON Bit Definitions

MCF5441X Tower Module Hardware Specification Page 19 of 31
The value of BLL[15:0] of serial boot header (7-byte) will determine whether the code will continue to
load from SPI memory at offset 7 to internal SRAM and boot from internal SRAM. If the value of
BLL[15:0] is cleared, the serial boot facility will not continue to access SPI memory after offset 6.
Instead, it will depend on the SBF_RCON bit 29 to determine whether the code will continue to load at
address 0 either from FlexBus or NAND flash.
Serial RCON
BOOT Port size
Boot Memory
Reserved
FB_ALE select
Oscillator mode
PLL mode
PLL Reference Divider
PLL Clock Multiplier
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Serial RCON
FlexBus Half Clock
NAND Flash Controller Clock Divider
Internal Bus Clock Divider
Core Bus Clock Divider
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 13 - Easy Configurable Serial RCON

MCF5441X Tower Module Hardware Specification Page 20 of 31
4.14 Jumpers, Switches
The TWR-MCF5441X implements a number of configuration jumpers, switches and headers. Refer to
this section for a quick overview of each. For more details refer to the specific section related to the
functionality of the specific jumper, switch, or header.
Jumpers /
Header
Description
J1
UART0 Header
J2
Clock Source (25Mhz/ External) Jumper
J3
UART4 Header
J4
Audio Speaker Header
J5
Boot Mode Jumpers
J6
BDM/JTAG mode Jumper
J7
JM60 BKGD/MS Header
J8
TCK/PSTCLK_OSBDM Jumper
J9
USB Mini B (OSBDM / PWR)
J10
JM60 IRQ (Boot Mode) Jumper
J11
26-pin BDM Header
J12
MCU Reset Jumper
J13
Primary Elevator Connection
J14
Secondary Elevator Connection
Table 14 - Jumpers / Headers Summary
Switches /
Pushbuttons
Description
SW1
RCON Boot Settings Switch for BOOTMOD 01
SW2
MCU Reset Push Button
SW3
IRQ1 Push Button
SW4
User Input Switch (GPIOH0 / GPIOH1)
SW5
IRQ2 Puch Button
Table 15- Switches / Push Buttons Summary