Freescale Semiconductor M68HC08RG User manual

© Motorola, Inc., 2002
M68HC08RG/AD
Rev. 2, 3/2002
M68HC08
Family Reference Guide
Reference Guide
Programming Model
70
A ACCUMULATOR (A)
15 8 7 0
H X INDEX REGISTER (H:X)
15 0
STACK POINTER (SP)
15 0
PROGRAM COUNTER (PC)
70
CONDITION CODE
REGISTER (CCR)
V11HINZC
CARRY/BORROW FLAG (C)
TWO’S COMPLEMENT OVERFLOW
FLAG(V) ZEROFLAG(Z)
HALF-CARRYFLAG(H) NEGATIVE FLAG (N)
INTERRUPT MASK (I)
Figure 1. Programming Model
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...

M68HC08RG/AD
2M68HC08 Family Reference Guide MOTOROLA
Stacking
Figure 2. Interrupt Stack Frame
NOTE: To maintain compatibility with the M6805 Family, H (the high byte of the index
register) is not stacked during interrupt processing. If the interrupt service
routine modifies H or uses the indexed addressing mode, it is
the user’s responsibility to save and restore it prior to returning.
IRQINT PSHH
|
|Interrupt service routine
|
|
PULH
RTI
Figure 3. H Register Storage
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER (LOW BYTE X)(1)
PROGRAM COUNTER HIGH
1. High byte (H) of index register is not stacked.
PROGRAM COUNTER LOW
•
•
•
•
•
•
70
$00FF (DEFAULT ADDRESS
UNSTACKING
ORDER
STACKING
ORDER
5
4
3
2
1
1
2
3
4
5
ON RESET)
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...

M68HC08RG/AD
MOTOROLA M68HC08 Family Reference Guide 3
Interrupt Vector Locations
Notation Used in Instruction Set Summary
See Table 2 for the instruction set summary.
Table 1. M68HC08 Vectors
Address Reset Priority
FFFE Reset 1
FFFC SWI 2
FFFA IREQ[0] 3
:::
FF02 IREQ[124] 127
FF00 IREQ[125] 128
Operators
( ) = Contents of register or memory location shown inside parentheses
←= Is loaded with (read: “gets”)
&= Boolean AND
|= Boolean OR
⊕= Boolean exclusive OR
×= Multiply
÷= Divide
:= Concatenate
+=Add
–= Negate (two’s complement)
«= Sign extend
CPU Registers
A = Accumulator
CCR = Condition code register
H = Index register, higher order (most significant) eight bits
X = Index register, lower order (least significant) eight bits
PC = Program counter
PCH = Program counter, higher order (most significant) eight bits
PCL = Program counter, lower order (least significant) eight bits
SP = Stack pointer
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...

M68HC08RG/AD
4M68HC08 Family Reference Guide MOTOROLA
Memory and Addressing
M= A memory location or absolute data, depending on addressing
mode
M:M + $0001 = A 16-bit value in two consecutive memory locations. The higher-
order (most significant) eight bits are located at the address of M,
and the lower-order (least significant) eight bits are located at the
next higher sequential address.
rel =The relative offset, which is the two’s complement number stored
in the last byte of machine code corresponding to a branch
instruction
Condition Code Register (CCR) Bits
V=Two’s complement overflow indicator, bit 7
H= Half carry, bit 4
I= Interrupt mask, bit 3
N= Negative indicator, bit 2
Z= Zero indicator, bit 1
C= Carry/borrow, bit 0 (carry out of bit 7)
Bit Status BEFORE Execution of an Instruction (n = 7, 6, 5, ... 0)(1)
1. For 2-byte operations such as LDHX, STHX, and CPHX, n= 15 refers to bit 15 of the
2-byte word or bit 7 of the most significant (first) byte.
Mn=Bitnof memory location used in operation
An=Bitnof accumulator
Hn=Bitnof index register H
Xn=Bitnof index register X
bn=Bitnof the source operand (M, A, or X)
Bit Status AFTER Execution of an Instruction(1)
1. For 2-byte operations such as LDHX, STHX, and CPHX, n= 15 refers to bit 15 of the
2-byte word or bit 7 of the most significant (first) byte.
Rn=Bitnof the result of an operation (n= 7, 6, 5, …0)
CCR Activity Figure Notation
– = Bit not affected
0 = Bit forced to 0
1 = Bit forced to 1
 =Bit set or cleared according to results of operation
U = Undefined after the operation
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...

M68HC08RG/AD
MOTOROLA M68HC08 Family Reference Guide 5
Machine Coding Notation
dd =Low-order eight bits of a direct address $0000–$00FF (high byte assumed
to be $00)
ee =Upper eight bits of 16-bit offset
ff =Lower eight bits of 16-bit offset or 8-bit offset
ii =One byte of immediate data
jj =High-order byte of a 16-bit immediate data value
kk =Low-order byte of a 16-bit immediate data value
hh =High-order byte of 16-bit extended address
ll =Low-order byte of 16-bit extended address
rr =Relative offset
Explanation of Italic Expressions in Source Form Column
n=Any label or expression that evaluates to a single integer in the range 0–7
opr8i =Any label or expression that evaluates to an 8-bit immediate value
opr16i =Any label or expression that evaluates to a 16-bit immediate value
opr8a =Any label or expression that evaluates to an 8-bit value. The instruction
treats this 8-bit value as the loworder eight bits of an address inthe direct
page of the 64-Kbyte address space ($00xx).
opr16a =Any label or expression that evaluates to a 16-bit value. The instruction
treats this value as an address in the 64-Kbyte address space.
oprx8 =Any label or expression that evaluates to an unsigned 8-bit value; used
for indexed addressing
oprx16 =Any label or expression that evaluates to a 16-bit value. Since the
MC68HC08S has a 16-bit address bus, this can be either a signed or an
unsigned value.
rel =Any label or expression that refers to an address that is within –128 to
+127 locations from the next address after the last byte of object code for
the current instruction. The assembler will calculate the 8-bit signed
offset and include it in the object code for this instruction.
Address Modes
INH =Inherent (no operands)
IMM =8-bit or 16-bit immediate
DIR =8-bit direct
EXT =16-bit extended
IX =16-bit indexed no offset
IX+ =16-bit indexed no offset, post increment (CBEQ and MOV only)
IX1 =16-bit indexed with 8-bit offset from H:X
IX1+ =16-bit indexed with 8-bit offset, post increment (CBEQ only)
IX2 =16-bit indexed with 16-bit offset from H:X
REL =8-bit relative offset
SP1 =Stack pointer relative with 8-bit offset
SP2 =Stack pointer relative with 16-bit offset
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...

M68HC08RG/AD
6M68HC08 Family Reference Guide MOTOROLA
Table 2. Instruction Set Summary (Sheet 1 of 8)
Source
Form Operation Description Effect
on CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
ADC #opr8i
ADC opr8a
ADC opr16a
ADC oprx16,X
ADC oprx8,X
ADC ,X
ADC oprx16,SP
ADC oprx8,SP
Add with Carry A ←(A) + (M) + (C)
 – 
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A9
B9
C9
D9
E9
F9
9ED9
9EE9
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
2
5
4
ADD #opr8i
ADD opr8a
ADD opr16a
ADD oprx16,X
ADD oprx8,X
ADD ,X
ADD oprx16,SP
ADD oprx8,SP
Add without Carry A ←(A) + (M)
 – 
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
AB
BB
CB
DB
EB
FB
9EDB
9EEB
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
2
5
4
AIS #opr8i Add Immediate Value
(Signed) to Stack Pointer SP ←(SP) + (M) M is sign extended to a 16-bit value ––––––IMM A7 ii 2
AIX #opr8i Add Immediate Value (Signed) to Index
Register (H:X)
H:X ←(H:X) + (M)
M is sign extended to a 16-bit value ––––––IMM AF ii 2
AND #opr8i
AND opr8a
AND opr16a
AND oprx16,X
AND oprx8,X
AND ,X
AND oprx16,SP
AND oprx8,SP
Logical AND A ←(A) & (M) 0 ––
 –
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A4
B4
C4
D4
E4
F4
9ED4
9EE4
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
2
5
4
ASL opr8a
ASLA
ASLX
ASL oprx8,X
ASL ,X
ASL oprx8,SP
Arithmetic Shift Left
(Same as LSL)
 –– 
DIR
INH
INH
IX1
IX
SP1
38
48
58
68
78
9E68
dd
ff
ff
4
1
1
4
3
5
ASR opr8a
ASRA
ASRX
ASR oprx8,X
ASR ,X
ASR oprx8,SP
Arithmetic Shift Right
 –– 
DIR
INH
INH
IX1
IX
SP1
37
47
57
67
77
9E67
dd
ff
ff
4
1
1
4
3
5
BCC rel Branch if Carry Bit Clear Branch if (C) = 0 ––––––REL 24 rr 3
Cb0
b7 0
b0
b7 C
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...

M68HC08RG/AD
MOTOROLA M68HC08 Family Reference Guide 7
BCLR n,opr8a Clear Bit n in Memory Mn ←0 ––––––
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
BCS rel Branch if Carry Bit Set
(Same as BLO) Branch if (C) = 1 ––––––REL 25 rr 3
BEQ rel Branch if Equal Branch if (Z) = 1 ––––––REL 27 rr 3
BGE rel Branch if Greater Than or Equal To
(Signed Operands) Branch if (N ⊕ V) = 0 ––––––REL 90 rr 3
BGT rel Branch if Greater Than
(Signed Operands) Branch if (Z) | (N ⊕ V) = 0 ––––––REL 92 rr 3
BHCC rel Branch if Half Carry Bit
Clear Branch if (H) = 0 ––––––REL 28 rr 3
BHCS rel Branch if Half Carry Bit
Set Branch if (H) = 1 ––––––REL 29 rr 3
BHI rel Branch if Higher Branch if (C) | (Z) = 0 ––––––REL 22 rr 3
BHS rel Branch if Higher or Same
(Same as BCC) Branch if (C) = 0 ––––––REL 24 rr 3
BIH rel Branch if IRQ Pin High Branch if IRQ pin = 1 ––––––REL 2F rr 3
BIL rel Branch if IRQ Pin Low Branch if IRQ pin = 0 ––––––REL 2E rr 3
BIT #opr8i
BIT opr8a
BIT opr16a
BIT oprx16,X
BIT oprx8,X
BIT ,X
BIT oprx16,SP
BIT oprx8,SP
Bit Test (A) & (M) (CCR Updated but Operands
Not Changed) 0––
 –
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A5
B5
C5
D5
E5
F5
9ED5
9EE5
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
2
5
4
BLE rel Branch if Less Than or Equal To
(Signed Operands) Branch if (Z) | (N ⊕ V) = 1 ––––––REL 93 rr 3
BLO rel Branch if Lower
(Same as BCS) Branch if (C) = 1 ––––––REL 25 rr 3
BLS rel Branch if Lower or Same Branch if (C) | (Z) = 1 ––––––REL 23 rr 3
BLT rel Branch if Less Than
(Signed Operands) Branch if (N ⊕ V ) = 1––––––REL 91 rr 3
BMC rel Branch if Interrupt Mask
Clear Branch if (I) = 0 ––––––REL 2C rr 3
BMI rel Branch if Minus Branch if (N) = 1 ––––––REL 2B rr 3
Table 2. Instruction Set Summary (Sheet 2 of 8)
Source
Form Operation Description Effect
on CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...

M68HC08RG/AD
8M68HC08 Family Reference Guide MOTOROLA
BMS rel Branch if Interrupt Mask
Set Branch if (I) = 1 ––––––REL 2D rr 3
BNE rel Branch if Not Equal Branch if (Z) = 0 ––––––REL 26 rr 3
BPL rel Branch if Plus Branch if (N) = 0 ––––––REL 2A rr 3
BRA rel Branch Always No Test ––––––REL 20 rr 3
BRCLR n,opr8a,rel Branch if Bit nin Memory
Clear Branch if (Mn) = 0 –––––

DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BRN rel Branch Never Uses 3 Bus Cycles ––––––REL 21 rr 3
BRSET n,opr8a,rel Branch if Bit nin Memory
Set Branch if (Mn) = 1 –––––

DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BSET n,opr8a Set Bit n in Memory Mn ←1 ––––––
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
BSR rel Branch to Subroutine
PC ← (PC) + $0002
push (PCL); SP ←(SP) –$0001
push (PCH); SP ←(SP) –$0001
PC ←(PC) + rel
––––––REL AD rr 4
CBEQ opr8a,rel
CBEQA #opr8i,rel
CBEQX #opr8i,rel
CBEQ oprx8,X+,rel
CBEQ ,X+,rel
CBEQ oprx8,SP,rel
Compare and Branch if
Equal
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (X) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
––––––
DIR
IMM
IMM
IX1+
IX+
SP1
31
41
51
61
71
9E61
dd rr
ii rr
ii rr
ff rr
rr
ff rr
5
4
4
5
4
6
CLC Clear Carry Bit C ←0 –––––0INH 98 1
CLI Clear Interrupt Mask Bit I ←0 ––0–––INH 9A 2
Table 2. Instruction Set Summary (Sheet 3 of 8)
Source
Form Operation Description Effect
on CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...

M68HC08RG/AD
MOTOROLA M68HC08 Family Reference Guide 9
CLR opr8a
CLRA
CLRX
CLRH
CLR oprx8,X
CLR ,X
CLR oprx8,SP
Clear
M ←$00
A ←$00
X ←$00
H ←$00
M ←$00
M ←$00
M ←$00
0––01–
DIR
INH
INH
INH
IX1
IX
SP1
3F
4F
5F
8C
6F
7F
9E6F
dd
ff
ff
3
1
1
1
3
2
4
CMP #opr8i
CMP opr8a
CMP opr16a
CMP oprx16,X
CMP oprx8,X
CMP ,X
CMP oprx16,SP
CMP oprx8,SP
Compare Accumulator
with Memory
(A) –(M)
(CCR Updated But Operands Not
Changed)
 –– 
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A1
B1
C1
D1
E1
F1
9ED1
9EE1
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
2
5
4
COM opr8a
COMA
COMX
COM oprx8,X
COM ,X
COM oprx8,SP
Complement
(One’s Complement)
M ←(M)= $FF –(M)
A ←(A) = $FF –(A)
X ←(X) = $FF –(X)
M ←(M) = $FF –(M)
M ←(M) = $FF –(M)
M ←(M) = $FF –(M)
0––
 1
DIR
INH
INH
IX1
IX
SP1
33
43
53
63
73
9E63
dd
ff
ff
4
1
1
4
3
5
CPHX #opr
CPHX opr Compare Index Register (H:X) with Memory
(H:X) –(M:M + $0001)
(CCR Updated But Operands Not
Changed)
 –– 
IMM
DIR 65 75 jj ii+1 dd 3 4
CPX #opr8i
CPX opr8a
CPX opr16a
CPX oprx16,X
CPX oprx8,X
CPX ,X
CPX oprx16,SP
CPX oprx8,SP
Compare X (Index
Register Low) with
Memory
(X) –(M)
(CCR Updated But Operands Not
Changed)
 –– 
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A3
B3
C3
D3
E3
F3
9ED3
9EE3
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
2
5
4
DAA Decimal Adjust AccumulatorAfterADDor
ADC of BCD Values (A)10 U––
 INH 72 2
DBNZ opr8a,rel
DBNZA rel
DBNZX rel
DBNZ oprx8,X,rel
DBNZ ,X,rel
DBNZ oprx8,SP,rel
Decrement and Branch if
Not Zero
Decrement A, X, or M
Branch if (result) ≠ 0
DBNZX Affects X Not H ––––––
DIR
INH
INH
IX1
IX
SP1
3B
4B
5B
6B
7B
9E6B
dd rr
rr
rr
ff rr
rr
ff rr
5
3
3
5
4
6
DEC opr8a
DECA
DECX
DEC oprx8,X
DEC ,X
DEC oprx8,SP
Decrement
M ←(M) –$01
A ←(A) –$01
X ←(X) –$01
M ←(M) –$01
M ←(M) –$01
M ←(M) –$01
 ––  –
DIR
INH
INH
IX1
IX
SP1
3A
4A
5A
6A
7A
9E6A
dd
ff
ff
4
1
1
4
3
5
DIV Divide A ←(H:A)÷(X)
H ←Remainder ––––
 INH 52 7
Table 2. Instruction Set Summary (Sheet 4 of 8)
Source
Form Operation Description Effect
on CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...

M68HC08RG/AD
10 M68HC08 Family Reference Guide MOTOROLA
EOR #opr8i
EOR opr8a
EOR opr16a
EOR oprx16,X
EOR oprx8,X
EOR ,X
EOR oprx16,SP
EOR oprx8,SP
Exclusive OR
Memory with
Accumulator A ←(A ⊕M) 0 ––
 –
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A8
B8
C8
D8
E8
F8
9ED8
9EE8
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
2
5
4
INC opr8a
INCA
INCX
INC oprx8,X
INC ,X
INC oprx8,SP
Increment
M ←(M) + $01
A ←(A) + $01
X ←(X) + $01
M ←(M) + $01
M ←(M) + $01
M ←(M) + $01
 ––  –
DIR
INH
INH
IX1
IX
SP1
3C
4C
5C
6C
7C
9E6C
dd
ff
ff
4
1
1
4
3
5
JMP opr8a
JMP opr16a
JMP oprx16,X
JMP oprx8,X
JMP ,X
Jump PC ←Jump Address ––––––
DIR
EXT
IX2
IX1
IX
BC
CC
DC
EC
FC
dd
hh ll
ee ff
ff
2
3
4
3
3
JSR opr8a
JSR opr16a
JSR oprx16,X
JSR oprx8,X
JSR ,X
Jump to Subroutine
PC ←(PC) + n(n= 1, 2, or 3)
Push (PCL); SP ←(SP) –$0001
Push (PCH); SP ←(SP) –$0001
PC ←Unconditional Address
––––––
DIR
EXT
IX2
IX1
IX
BD
CD
DD
ED
FD
dd
hh ll
ee ff
ff
4
5
6
5
4
LDA #opr8i
LDA opr8a
LDA opr16a
LDA oprx16,X
LDA oprx8,X
LDA ,X
LDA oprx16,SP
LDA oprx8,SP
Load Accumulator from
Memory A ←(M) 0 ––
 –
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A6
B6
C6
D6
E6
F6
9ED6
9EE6
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
2
5
4
LDHX #opr
LDHX opr LoadIndexRegister(H:X) from Memory H:X ← (M:M + $0001)0––
 –IMM
DIR 45 55 ii jj dd 3 4
LDX #opr8i
LDX opr8a
LDX opr16a
LDX oprx16,X
LDX oprx8,X
LDX ,X
LDX oprx16,SP
LDX oprx8,SP
Load X (Index Register
Low) from Memory X ←(M) 0 ––
 –
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
AE
BE
CE
DE
EE
FE
9EDE
9EEE
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
2
5
4
LSL opr8a
LSLA
LSLX
LSL oprx8,X
LSL ,X
LSL oprx8,SP
Logical Shift Left
(Same as ASL)
 –– 
DIR
INH
INH
IX1
IX
SP1
38
48
58
68
78
9E68
dd
ff
ff
4
1
1
4
3
5
Table 2. Instruction Set Summary (Sheet 5 of 8)
Source
Form Operation Description Effect
on CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
Cb0
b7 0
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...

M68HC08RG/AD
MOTOROLA M68HC08 Family Reference Guide 11
LSR opr8a
LSRA
LSRX
LSR oprx8,X
LSR ,X
LSR oprx8,SP
Logical Shift Right
 ––0 
DIR
INH
INH
IX1
IX
SP1
34
44
54
64
74
9E64
dd
ff
ff
4
1
1
4
3
5
MOV opr8a,opr8a
MOV opr8a,X+
MOV #opr8i,opr8a
MOV ,X+,opr8a
Move
(M)destination ← (M)source
H:X ←(H:X) + $0001 in
IX+/DIR and DIR/IX+ Modes
0––
 –
DIR/DIR
DIR/IX+
IMM/DIR
IX+/DIR
4E
5E
6E
7E
dd dd
dd
ii dd
dd
5
4
4
4
MUL Unsigned multiply X:A ←(X) ×(A) –0–––0INH 42 5
NEG opr8a
NEGA
NEGX
NEG oprx8,X
NEG ,X
NEG oprx8,SP
Negate
(Two’s Complement)
M ←– (M) = $00 –(M)
A ←– (A) = $00 –(A)
X ←– (X) = $00 –(X)
M ←– (M) = $00 –(M)
M ←– (M) = $00 –(M)
M ←– (M) = $00 –(M)
 –– 
DIR
INH
INH
IX1
IX
SP1
30
40
50
60
70
9E60
dd
ff
ff
4
1
1
4
3
5
NOP No Operation Uses 1 Bus Cycle ––––––INH 9D 1
NSA Nibble Swap
Accumulator A ←(A[3:0]:A[7:4]) ––––––INH 62 3
ORA #opr8i
ORA opr8a
ORA opr16a
ORA oprx16,X
ORA oprx8,X
ORA ,X
ORA oprx16,SP
ORA oprx8,SP
InclusiveORAccumulator
and Memory A ←(A) | (M) 0 ––
 –
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
AA
BA
CA
DA
EA
FA
9EDA
9EEA
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
2
5
4
PSHA Push Accumulator onto
Stack Push (A); SP ← (SP) –$0001 ––––––INH 87 2
PSHH Push H (Index Register
High) onto Stack Push (H);SP ← (SP) – $0001 ––––––INH 8B 2
PSHX Push X (Index Register
Low) onto Stack Push (X); SP ← (SP) – $0001 ––––––INH 89 2
PULA Pull Accumulator from
Stack SP ← (SP + $0001); Pull (A)––––––INH 86 2
PULH Pull H (Index Register
High) from Stack SP ← (SP + $0001); Pull (H)––––––INH 8A 2
PULX Pull X (Index Register
Low) from Stack SP ← (SP + $0001); Pull (X)––––––INH 88 2
ROL opr8a
ROLA
ROLX
ROL oprx8,X
ROL ,X
ROL oprx8,SP
Rotate Left through Carry
 –– 
DIR
INH
INH
IX1
IX
SP1
39
49
59
69
79
9E69
dd
ff
ff
4
1
1
4
3
5
Table 2. Instruction Set Summary (Sheet 6 of 8)
Source
Form Operation Description Effect
on CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
b0
b7 C0
Cb0
b7
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...

M68HC08RG/AD
12 M68HC08 Family Reference Guide MOTOROLA
ROR opr8a
RORA
RORX
ROR oprx8,X
ROR ,X
ROR oprx8,SP
Rotate Right through
Carry
 –– 
DIR
INH
INH
IX1
IX
SP1
36
46
56
66
76
9E66
dd
ff
ff
4
1
1
4
3
5
RSP Reset Stack Pointer SP ←$FF
(High Byte Not Affected) ––––––INH 9C 1
RTI Return from Interrupt
SP ←(SP) + $0001; Pull (CCR)
SP ←(SP) + $0001; Pull (A)
SP ←(SP) + $0001; Pull (X)
SP ←(SP) + $0001; Pull (PCH)
SP ←(SP) + $0001; Pull (PCL)
 INH 80 7
RTS Return from Subroutine SP ←SP + $0001; Pull (PCH)
SP ←SP + $0001; Pull (PCL) ––––––INH 81 4
SBC #opr8i
SBC opr8a
SBC opr16a
SBC oprx16,X
SBC oprx8,X
SBC ,X
SBC oprx16,SP
SBC oprx8,SP
Subtract with Carry A ←(A) –(M) –(C)
 –– 
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A2
B2
C2
D2
E2
F2
9ED2
9EE2
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
2
5
4
SEC Set Carry Bit C ←1 –––––1INH 99 1
SEI Set Interrupt Mask Bit I ←1 ––1–––INH 9B 2
STA opr8a
STA opr16a
STA oprx16,X
STA oprx8,X
STA ,X
STA oprx16,SP
STA oprx8,SP
Store Accumulator in
Memory M ← (A) 0 ––
 –
DIR
EXT
IX2
IX1
IX
SP2
SP1
B7
C7
D7
E7
F7
9ED7
9EE7
dd
hh ll
ee ff
ff
ee ff
ff
3
4
4
3
2
5
4
STHX opr Store H:X (Index Reg.) (M:M + $0001) ←(H:X) 0 ––
 –DIR 35 dd 4
STOP
Enable Interrupts:
Stop Processing
Refer to MCU
Documentation
I bit ←0; Stop Processing ––0–––INH 8E 1
STX opr8a
STX opr16a
STX oprx16,X
STX oprx8,X
STX ,X
STX oprx16,SP
STX oprx8,SP
Store X (Low 8 Bits of
Index Register)
in Memory M ← (X) 0 ––
 –
DIR
EXT
IX2
IX1
IX
SP2
SP1
BF
CF
DF
EF
FF
9EDF
9EEF
dd
hh ll
ee ff
ff
ee ff
ff
3
4
4
3
2
5
4
Table 2. Instruction Set Summary (Sheet 7 of 8)
Source
Form Operation Description Effect
on CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
b0
b7 C
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...

M68HC08RG/AD
MOTOROLA M68HC08 Family Reference Guide 13
SUB #opr8i
SUB opr8a
SUB opr16a
SUB oprx16,X
SUB oprx8,X
SUB ,X
SUB oprx16,SP
SUB oprx8,SP
Subtract A ←(A) –(M)
 –– 
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A0
B0
C0
D0
E0
F0
9ED0
9EE0
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
2
5
4
SWI Software Interrupt
PC ←(PC) + $0001
Push (PCL); SP ←(SP) –$0001
Push (PCH); SP ←(SP) –$0001
Push (X); SP ←(SP) –$0001
Push (A); SP ←(SP) –$0001
Push (CCR); SP ←(SP) –$0001
I ←1;
PCH ←Interrupt Vector High Byte
PCL ←Interrupt Vector Low Byte
––1–––INH 83 9
TAP Transfer Accumulator to
CCR CCR ←(A)
 INH 84 2
TAX Transfer Accumulator to
X (Index Register Low) X ←(A) ––––––INH 97 1
TPA Transfer CCR to
Accumulator A ←(CCR) ––––––INH 85 1
TST opr8a
TSTA
TSTX
TST oprx8,X
TST ,X
TST oprx8,SP
Test for Negative or Zero
(M) –$00
(A) –$00
(X) –$00
(M) –$00
(M) –$00
(M) –$00
0––
 –
DIR
INH
INH
IX1
IX
SP1
3D
4D
5D
6D
7D
9E6D
dd
ff
ff
3
1
1
3
2
4
TSX Transfer SP to Index Reg. H:X ←(SP) + $0001 ––––––INH 95 2
TXA Transfer X (Index Reg.
Low) to Accumulator A ←(X) ––––––INH 9F 1
TXS Transfer Index Reg. to SP SP ←(H:X) –$0001 ––––––INH 94 2
WAIT Enable Interrupts; Wait
for Interrupt I bit ←0; Halt CPU ––0–––INH 8F 1
Table 2. Instruction Set Summary (Sheet 8 of 8)
Source
Form Operation Description Effect
on CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...

M68HC08RG/AD
14 M68HC08 Family Reference Guide MOTOROLA
Addressing Modes
Inherent (INH) The inherent addressing mode has no operand because the opcode contains
all information necessaryto carry outthe instruction. Mostinherentinstructions
are one byte long.
Immediate (IMM) The operand in immediate mode instructions is contained in the byte(s)
immediately following the opcode. The immediate value is one or two bytes,
depending on the size of the register involved in the instruction.
Direct (DIR) Most direct mode instructions can access any of the first 256 memory
addresses with two bytes. The first byte is the opcode, and the second byte is
the low byte of the operand address. The high byte of the address is assumed
to be $00.
Extended (EXT) Extended mode instructions are three bytes in length and can access any
address in a 64-Kbyte memory map. The first byte is the opcode. The following
two bytes are the operand addresses.
Indexed (IX, IX1,
and IX2) Indexed mode instructions access data with variable addresses. The effective address (EA) of the operand is determined by the contents of the register (H:X)
added to a zero, 8-bit, or 16-bit offset. For one-byte, zero-offset mode
instructions (IX), X (index register low) contains the low byte of the EA of the
operand. The value of H (index register high) is $00 if none of the HC08
instructions that modify H are used, assuring source code compatibility with
HC05 Family instructions. The sum of H:X is the EA of the operand. For two-
byte, 8-bit offset mode instructions (IX1) the unsigned bytes in H:X added to the
unsigned byte following the opcode constitutes the EA of the operand. For
three byte, 16-bit offset mode instructions (IX2), the unsigned bytes in H:X
added to the 16-bit unsigned word following the opcode constitute the EA of the
operand.
Stack Pointer
(SP1 and SP2) Stack pointer (SP) mode instructions operate like indexed instructions, except that the offset is added to the 16-bit SP. Stack pointer, 8-bit offset instructions
(SP1) are three-byte instructions. The EA of the operand is formed by adding
the unsigned byte in the SP register to the unsigned byte following the opcode.
Stack pointer, 16-bit offset instructions (SP2) are four-byte instructions. The EA
of the operand is formed by adding the unsigned bytes in the 16-bit SP register
to the 16-bit unsigned word following the opcode.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...

M68HC08RG/AD
MOTOROLA M68HC08 Family Reference Guide 15
Relative (REL) Conditional branch instructions use the relative addressing mode. The EA of
the operand depends on whether or not the branch is taken. If a branch is
taken, the EA of the operand is formed by adding the signed byte following the
opcode to the value of the PC, and the PC is loaded with the EA. If no branch
is taken, the EA is the contents of the PC.
Memory to Memory
(IMD, DD, IX+D, and
DIX+)
Memory to memory immediate to direct (IMD) is a three-byte addressing mode.
The operand inthe byte immediatelyfollowing theopcodeis stored in thedirect
page location addressed by the second byte following the opcode.
Memory to memory direct to direct (DD) is a three-byte addressing mode. The
operand in the byte immediately following the opcode is stored in the direct
page location addressed by the second byte following the opcode.
Memory tomemoryindexed todirectwith postincrementofH:X(IX+D)isatwo-
byte addressing mode. The operand addressed by H:X is stored in the direct
page location addressed by the byte following the opcode.
Memory to memorydirect to indexedwith postincrementofH:X (DIX+) isa two-
byte addressing mode. The operand in the direct page location addressed by
the byte immediately following the opcode is stored in the location addressed
by H:X.
IndexedandIndexed
8-Bit Offset with
Post Increment
(IX+ and IX1+)
Indexed, no offset with post increment mode instructions (IX+) are two-byte
instructions that address operands, then increment H:X. The EA of the operand
isderived by adding X (low byte) to H(high byte). Indexed,8-bitoffsetwith post
increment mode instructions (IX1+) are three-byte instructions that address
operands with variable addresses, then increment H:X. The EA of the operand
is derived by adding X (low byte) with H (high byte).
Opcode Map
See Table 3.
Hexadecimal to ASCII Conversion
See Table 4.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...

M68HC08RG/AD
16 M68HC08 Family Reference Guide MOTOROLA
Table 3. M68HC08 Opcode Map
Bit-Manipulation Branch Read-Modify-Write Control Register/Memory
DIR DIR REL DIR INH INH IX1 SP1 IX INH INH IMM DIR EXT IX2 SP2 IX1 SP1 IX
01234569E6789ABCD9EDE9EEF
0
5
BRSET0
3DIR
4
BSET0
2DIR
3
BRA
2REL
4
NEG
2DIR
1
NEGA
1INH
1
NEGX
1INH
4
NEG
2IX1
5
NEG
3 SP1
3
NEG
1IX
7
RTI
1INH
3
BGE
2REL
2
SUB
2IMM
3
SUB
2DIR
4
SUB
3EXT
4
SUB
3IX2
5
SUB
4SP2
3
SUB
2IX1
4
SUB
3 SP1
2
SUB
1IX
1
5
BRCLR0
3DIR
4
BCLR0
2DIR
3
BRN
2REL
5
CBEQ
3DIR
4
CBEQA
3IMM
4
CBEQX
3IMM
5
CBEQ
3IX1+
6
CBEQ
4 SP1
4
CBEQ
2IX+
4
RTS
1INH
3
BLT
2REL
2
CMP
2IMM
3
CMP
2DIR
4
CMP
3EXT
4
CMP
3IX2
5
CMP
4SP2
3
CMP
2IX1
4
CMP
3 SP1
2
CMP
1IX
2
5
BRSET1
3DIR
4
BSET1
2DIR
3
BHI
2REL
5
MUL
1INH
7
DIV
1INH
3
NSA
1INH
2
DAA
1INH
3
BGT
2REL
2
SBC
2IMM
3
SBC
2DIR
4
SBC
3EXT
4
SBC
3IX2
5
SBC
4SP2
3
SBC
2IX1
4
SBC
3 SP1
2
SBC
1IX
3
5
BRCLR1
3DIR
4
BCLR1
2DIR
3
BLS
2REL
4
COM
2DIR
1
COMA
1INH
1
COMX
1INH
4
COM
2IX1
5
COM
3 SP1
3
COM
1IX
9
SWI
1INH
3
BLE
2REL
2
CPX
2IMM
3
CPX
2DIR
4
CPX
3EXT
4
CPX
3IX2
5
CPX
4SP2
3
CPX
2IX1
4
CPX
3 SP1
2
CPX
1IX
4
5
BRSET2
3DIR
4
BSET2
2DIR
3
BCC
2REL
4
LSR
2DIR
1
LSRA
1INH
1
LSRX
1INH
4
LSR
2IX1
5
LSR
3 SP1
3
LSR
1IX
2
TAP
1INH
2
TXS
1INH
2
AND
2IMM
3
AND
2DIR
4
AND
3EXT
4
AND
3IX2
5
AND
4SP2
3
AND
2IX1
4
AND
3 SP1
2
AND
1IX
5
5
BRCLR2
3DIR
4
BCLR2
2DIR
3
BCS
2REL
4
STHX
2DIR
3
LDHX
3IMM
4
LDHX
2DIR
3
CPHX
3IMM
4
CPHX
2DIR
1
TPA
1INH
2
TSX
1INH
2
BIT
2IMM
3
BIT
2DIR
4
BIT
3EXT
4
BIT
3IX2
5
BIT
4SP2
3
BIT
2IX1
4
BIT
3 SP1
2
BIT
1IX
6
5
BRSET3
3DIR
4
BSET3
2DIR
3
BNE
2REL
4
ROR
2DIR
1
RORA
1INH
1
RORX
1INH
4
ROR
2IX1
5
ROR
3 SP1
3
ROR
1IX
2
PULA
1INH
2
LDA
2IMM
3
LDA
2DIR
4
LDA
3EXT
4
LDA
3IX2
5
LDA
4SP2
3
LDA
2IX1
4
LDA
3 SP1
2
LDA
1IX
7
5
BRCLR3
3DIR
4
BCLR3
2DIR
3
BEQ
2REL
4
ASR
2DIR
1
ASRA
1INH
1
ASRX
1INH
4
ASR
2IX1
5
ASR
3 SP1
3
ASR
1IX
2
PSHA
1INH
1
TA X
1INH
2
AIS
2IMM
3
STA
2DIR
4
STA
3EXT
4
STA
3IX2
5
STA
4SP2
3
STA
2IX1
4
STA
3 SP1
2
STA
1IX
8
5
BRSET4
3DIR
4
BSET4
2DIR
3
BHCC
2REL
4
LSL
2DIR
1
LSLA
1INH
1
LSLX
1INH
4
LSL
2IX1
5
LSL
3 SP1
3
LSL
1IX
2
PULX
1INH
1
CLC
1INH
2
EOR
2IMM
3
EOR
2DIR
4
EOR
3EXT
4
EOR
3IX2
5
EOR
4SP2
3
EOR
2IX1
4
EOR
3 SP1
2
EOR
1IX
9
5
BRCLR4
3DIR
4
BCLR4
2DIR
3
BHCS
2REL
4
ROL
2DIR
1
ROLA
1INH
1
ROLX
1INH
4
ROL
2IX1
5
ROL
3 SP1
3
ROL
1IX
2
PSHX
1INH
1
SEC
1INH
2
ADC
2IMM
3
ADC
2DIR
4
ADC
3EXT
4
ADC
3IX2
5
ADC
4SP2
3
ADC
2IX1
4
ADC
3 SP1
2
ADC
1IX
A
5
BRSET5
3DIR
4
BSET5
2DIR
3
BPL
2REL
4
DEC
2DIR
1
DECA
1INH
1
DECX
1INH
4
DEC
2IX1
5
DEC
3 SP1
3
DEC
1IX
2
PULH
1INH
2
CLI
1INH
2
ORA
2IMM
3
ORA
2DIR
4
ORA
3EXT
4
ORA
3IX2
5
ORA
4SP2
3
ORA
2IX1
4
ORA
3 SP1
2
ORA
1IX
B
5
BRCLR5
3DIR
4
BCLR5
2DIR
3
BMI
2REL
5
DBNZ
3DIR
3
DBNZA
2INH
3
DBNZX
2INH
5
DBNZ
3IX1
6
DBNZ
4 SP1
4
DBNZ
2IX
2
PSHH
1INH
2
SEI
1INH
2
ADD
2IMM
3
ADD
2DIR
4
ADD
3EXT
4
ADD
3IX2
5
ADD
4SP2
3
ADD
2IX1
4
ADD
3 SP1
2
ADD
1IX
C
5
BRSET6
3DIR
4
BSET6
2DIR
3
BMC
2REL
4
INC
2DIR
1
INCA
1INH
1
INCX
1INH
4
INC
2IX1
5
INC
3 SP1
3
INC
1IX
1
CLRH
1INH
1
RSP
1INH
2
JMP
2DIR
3
JMP
3EXT
4
JMP
3IX2
3
JMP
2IX1
2
JMP
1IX
D
5
BRCLR6
3DIR
4
BCLR6
2DIR
3
BMS
2REL
3
TST
2DIR
1
TSTA
1INH
1
TSTX
1INH
3
TST
2IX1
4
TST
3 SP1
2
TST
1IX
1
NOP
1INH
4
BSR
2REL
4
JSR
2DIR
5
JSR
3EXT
6
JSR
3IX2
5
JSR
2IX1
4
JSR
1IX
E
5
BRSET7
3DIR
4
BSET7
2DIR
3
BIL
2REL
5
MOV
3DD
4
MOV
2DIX+
4
MOV
3IMD
4
MOV
2IX+D
1
STOP
1INH
*
2
LDX
2IMM
3
LDX
2DIR
4
LDX
3EXT
4
LDX
3IX2
5
LDX
4SP2
3
LDX
2IX1
4
LDX
3 SP1
2
LDX
1IX
F
5
BRCLR7
3DIR
4
BCLR7
2DIR
3
BIH
2REL
3
CLR
2DIR
1
CLRA
1INH
1
CLRX
1INH
3
CLR
2IX1
4
CLR
3 SP1
2
CLR
1IX
1
WAIT
1INH
1
TXA
1INH
2
AIX
2IMM
3
STX
2DIR
4
STX
3EXT
4
STX
3IX2
5
STX
4SP2
3
STX
2IX1
4
STX
3 SP1
2
STX
1IX
INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with EXT Extended IX2 Indexed, 16-Bit Offset Post Increment DD Direct-Direct IMD Immediate-Direct IX1+ Indexed, 1-Byte Offset with IX+D Indexed-Direct DIX+ Direct-Indexed Post Increment
*Pre-byte for stack pointer indexed instructions
High Byte of Opcode in Hexadecimal F
Low Byte of Opcode in Hexadecimal 0
2
SUB
1IX
HC08 Cycles Opcode Mnemonic Number of Bytes / Addressing Mode
HIGH
LOW
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...

M68HC08RG/AD
MOTOROLA M68HC08 Family Reference Guide 17
Table 4. Hexadecimal to ASCII Conversion
Hex ASCII Hex ASCII Hex ASCII Hex ASCII
$00 NUL $20 SP space $40 @$60 ‘grave
$01 SOH $21 !$41 A$61 a
$02 STX $22 “quote $42 B$62 b
$03 ETX $23 #$43 C$63 c
$04 EOT $24 $$44 D$64 d
$05 ENQ $25 %$45 E$65 e
$06 ACK $26 &$46 F$66 f
$07 BEL beep $27 ‘apost.$47 G$67 g
$08 BS back
sp $28 ($48 H$68 h
$09 HT tab $29 )$49 I$69 i
$0A LF
linefeed $2A *$4A J$6A j
$0B VT $2B +$4B K$6B k
$0C FF $2C , comma $4C L$6C l
$0D CR return $2D -dash $4D M$6D m
$0E SO $2E .period $4E N$6E n
$0F SI $2F /$4F O$6F o
$10 DLE $30 0$50 P$70 p
$11 DC1 $31 1$51 Q$71 q
$12 DC2 $32 2$52 R$72 r
$13 DC3 $33 3$53 S$73 s
$14 DC4 $34 4$54 T$74 t
$15 NAK $35 5$55 U$75 u
$16 SYN $36 6$56 V$76 v
$17 ETB $37 7$57 W$77 w
$18 CAN $38 8$58 X$78 x
$19 EM $39 9$59 Y$79 y
$1A SUB $3A :$5A Z$7A z
$1B ESCAPE $3B ;$5B [$7B {
$1C FS $3C <$5C \$7C |
$1D GS $3D =$5D ]$7D }
$1E RS $3E >$5E ^$7E ~
$1F US $3F ?$5F _ under $7F DEL
delete
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...

M68HC08RG/AD
18 M68HC08 Family Reference Guide MOTOROLA
Hexadecimal to Decimal Conversion
To convert a hexadecimal number (up to four hexadecimal digits) to decimal,
look up the decimal equivalent of each hexadecimal digit in Table 5. The
decimal equivalent of the original hexadecimal number is the sum of the
weights found in the table for all hexadecimal digits.
Table 5. Hexadecimal to/from Decimal Conversion
15 Bit 8 7Bit0
15 12 11 8 7430
4th Hex Digit 3rd Hex Digit 2nd Hex Digit 1st Hex Digit
Hex Decimal Hex Decimal Hex Decimal Hex Decimal
0 0 0 0 0 0 0 0
14,096 1256 116 1 1
28,192 2512 232 2 2
312,288 3768 348 3 3
416,384 41,024 464 4 4
520,480 51,280 580 5 5
624,576 61,536 696 6 6
728,672 71,792 7112 7 7
832,768 82,048 8128 8 8
936,864 92,304 9144 9 9
A40,960 A2,560 A160 A10
B45,056 B2,816 B176 B11
C49,152 C3,072 C192 C12
D53,248 D3,328 D208 D13
E57,344 E3,484 E224 E14
F61,440 F3,840 F240 F15
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...

M68HC08RG/AD
MOTOROLA M68HC08 Family Reference Guide 19
Decimal to Hexadecimal Conversion
To convert a decimal number (up to 65,53510) to hexadecimal, find the largest
decimal number in Table 5 that is less than or equal to the number you are
converting. The corresponding hexadecimal digit is the most significant
hexadecimal digit of the result. Subtract the decimal number found from the
original decimal number to get the remaining decimal value. Repeat the
procedure using the remaining decimal value for each subsequent
hexadecimal digit.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...

HOW TO REACH US:
USA/EUROPE/LOCATIONS NOT LISTED:
Motorola Literature Distribution;
P.O. Box 5405, Denver, Colorado 80217
1-303-675-2140 or 1-800-441-2447
JAPAN:
Motorola Japan Ltd.; SPS, Technical Information Center,
3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan
81-3-3440-3569
ASIA/PACIFIC:
Motorola Semiconductors H.K. Ltd.;
Silicon Harbour Centre, 2 Dai King Street,
Tai PoIndustrial Estate, Tai Po, N.T., Hong Kong
852-26668334
TECHNICAL INFORMATION CENTER:
1-800-521-6274
HOME PAGE:
http://www.motorola.com/semiconductors
Information in this document is provided solely to enable system and software
implementers to use Motorola products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits or
integrated circuits based on the information in this document.
Motorola reserves the right to make changes without further notice to any products
herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims anyandall liability, including without limitationconsequentialorincidental
damages. “Typical”parameters which may be provided in Motorola data sheets
and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts.
Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as
components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which
the failure of the Motorola productcould create a situation where personal injury or
death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated
with suchunintended or unauthorized use,even ifsuch claim alleges that Motorola
was negligent regarding the design or manufacture of the part.
Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark
Office. digital dna is a trademark of Motorola, Inc. All other product or service
names are the property of their respective owners. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
© Motorola, Inc. 2002
M68HC08RG/AD
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...