Freescale Semiconductor M68HC08RG User manual

© Motorola, Inc., 2002
M68HC08RG/AD
Rev. 2, 3/2002
M68HC08
Family Reference Guide
Reference Guide
Programming Model
70
A ACCUMULATOR (A)
15 8 7 0
H X INDEX REGISTER (H:X)
15 0
STACK POINTER (SP)
15 0
PROGRAM COUNTER (PC)
70
CONDITION CODE
REGISTER (CCR)
V11HINZC
CARRY/BORROW FLAG (C)
TWO’S COMPLEMENT OVERFLOW
FLAG(V) ZEROFLAG(Z)
HALF-CARRYFLAG(H) NEGATIVE FLAG (N)
INTERRUPT MASK (I)
Figure 1. Programming Model
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2M68HC08 Family Reference Guide MOTOROLA
Stacking
Figure 2. Interrupt Stack Frame
NOTE: To maintain compatibility with the M6805 Family, H (the high byte of the index
register) is not stacked during interrupt processing. If the interrupt service
routine modifies H or uses the indexed addressing mode, it is
the user’s responsibility to save and restore it prior to returning.
IRQINT PSHH
|
|Interrupt service routine
|
|
PULH
RTI
Figure 3. H Register Storage
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER (LOW BYTE X)(1)
PROGRAM COUNTER HIGH
1. High byte (H) of index register is not stacked.
PROGRAM COUNTER LOW
•
•
•
•
•
•
70
$00FF (DEFAULT ADDRESS
UNSTACKING
ORDER
STACKING
ORDER
5
4
3
2
1
1
2
3
4
5
ON RESET)
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MOTOROLA M68HC08 Family Reference Guide 3
Interrupt Vector Locations
Notation Used in Instruction Set Summary
See Table 2 for the instruction set summary.
Table 1. M68HC08 Vectors
Address Reset Priority
FFFE Reset 1
FFFC SWI 2
FFFA IREQ[0] 3
:::
FF02 IREQ[124] 127
FF00 IREQ[125] 128
Operators
( ) = Contents of register or memory location shown inside parentheses
←= Is loaded with (read: “gets”)
&= Boolean AND
|= Boolean OR
⊕= Boolean exclusive OR
×= Multiply
÷= Divide
:= Concatenate
+=Add
–= Negate (two’s complement)
«= Sign extend
CPU Registers
A = Accumulator
CCR = Condition code register
H = Index register, higher order (most significant) eight bits
X = Index register, lower order (least significant) eight bits
PC = Program counter
PCH = Program counter, higher order (most significant) eight bits
PCL = Program counter, lower order (least significant) eight bits
SP = Stack pointer
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4M68HC08 Family Reference Guide MOTOROLA
Memory and Addressing
M= A memory location or absolute data, depending on addressing
mode
M:M + $0001 = A 16-bit value in two consecutive memory locations. The higher-
order (most significant) eight bits are located at the address of M,
and the lower-order (least significant) eight bits are located at the
next higher sequential address.
rel =The relative offset, which is the two’s complement number stored
in the last byte of machine code corresponding to a branch
instruction
Condition Code Register (CCR) Bits
V=Two’s complement overflow indicator, bit 7
H= Half carry, bit 4
I= Interrupt mask, bit 3
N= Negative indicator, bit 2
Z= Zero indicator, bit 1
C= Carry/borrow, bit 0 (carry out of bit 7)
Bit Status BEFORE Execution of an Instruction (n = 7, 6, 5, ... 0)(1)
1. For 2-byte operations such as LDHX, STHX, and CPHX, n= 15 refers to bit 15 of the
2-byte word or bit 7 of the most significant (first) byte.
Mn=Bitnof memory location used in operation
An=Bitnof accumulator
Hn=Bitnof index register H
Xn=Bitnof index register X
bn=Bitnof the source operand (M, A, or X)
Bit Status AFTER Execution of an Instruction(1)
1. For 2-byte operations such as LDHX, STHX, and CPHX, n= 15 refers to bit 15 of the
2-byte word or bit 7 of the most significant (first) byte.
Rn=Bitnof the result of an operation (n= 7, 6, 5, …0)
CCR Activity Figure Notation
– = Bit not affected
0 = Bit forced to 0
1 = Bit forced to 1
 =Bit set or cleared according to results of operation
U = Undefined after the operation
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MOTOROLA M68HC08 Family Reference Guide 5
Machine Coding Notation
dd =Low-order eight bits of a direct address $0000–$00FF (high byte assumed
to be $00)
ee =Upper eight bits of 16-bit offset
ff =Lower eight bits of 16-bit offset or 8-bit offset
ii =One byte of immediate data
jj =High-order byte of a 16-bit immediate data value
kk =Low-order byte of a 16-bit immediate data value
hh =High-order byte of 16-bit extended address
ll =Low-order byte of 16-bit extended address
rr =Relative offset
Explanation of Italic Expressions in Source Form Column
n=Any label or expression that evaluates to a single integer in the range 0–7
opr8i =Any label or expression that evaluates to an 8-bit immediate value
opr16i =Any label or expression that evaluates to a 16-bit immediate value
opr8a =Any label or expression that evaluates to an 8-bit value. The instruction
treats this 8-bit value as the loworder eight bits of an address inthe direct
page of the 64-Kbyte address space ($00xx).
opr16a =Any label or expression that evaluates to a 16-bit value. The instruction
treats this value as an address in the 64-Kbyte address space.
oprx8 =Any label or expression that evaluates to an unsigned 8-bit value; used
for indexed addressing
oprx16 =Any label or expression that evaluates to a 16-bit value. Since the
MC68HC08S has a 16-bit address bus, this can be either a signed or an
unsigned value.
rel =Any label or expression that refers to an address that is within –128 to
+127 locations from the next address after the last byte of object code for
the current instruction. The assembler will calculate the 8-bit signed
offset and include it in the object code for this instruction.
Address Modes
INH =Inherent (no operands)
IMM =8-bit or 16-bit immediate
DIR =8-bit direct
EXT =16-bit extended
IX =16-bit indexed no offset
IX+ =16-bit indexed no offset, post increment (CBEQ and MOV only)
IX1 =16-bit indexed with 8-bit offset from H:X
IX1+ =16-bit indexed with 8-bit offset, post increment (CBEQ only)
IX2 =16-bit indexed with 16-bit offset from H:X
REL =8-bit relative offset
SP1 =Stack pointer relative with 8-bit offset
SP2 =Stack pointer relative with 16-bit offset
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Table 2. Instruction Set Summary (Sheet 1 of 8)
Source
Form Operation Description Effect
on CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
ADC #opr8i
ADC opr8a
ADC opr16a
ADC oprx16,X
ADC oprx8,X
ADC ,X
ADC oprx16,SP
ADC oprx8,SP
Add with Carry A ←(A) + (M) + (C)
 – 
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A9
B9
C9
D9
E9
F9
9ED9
9EE9
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
2
5
4
ADD #opr8i
ADD opr8a
ADD opr16a
ADD oprx16,X
ADD oprx8,X
ADD ,X
ADD oprx16,SP
ADD oprx8,SP
Add without Carry A ←(A) + (M)
 – 
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
AB
BB
CB
DB
EB
FB
9EDB
9EEB
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
2
5
4
AIS #opr8i Add Immediate Value
(Signed) to Stack Pointer SP ←(SP) + (M) M is sign extended to a 16-bit value ––––––IMM A7 ii 2
AIX #opr8i Add Immediate Value (Signed) to Index
Register (H:X)
H:X ←(H:X) + (M)
M is sign extended to a 16-bit value ––––––IMM AF ii 2
AND #opr8i
AND opr8a
AND opr16a
AND oprx16,X
AND oprx8,X
AND ,X
AND oprx16,SP
AND oprx8,SP
Logical AND A ←(A) & (M) 0 ––
 –
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A4
B4
C4
D4
E4
F4
9ED4
9EE4
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
2
5
4
ASL opr8a
ASLA
ASLX
ASL oprx8,X
ASL ,X
ASL oprx8,SP
Arithmetic Shift Left
(Same as LSL)
 –– 
DIR
INH
INH
IX1
IX
SP1
38
48
58
68
78
9E68
dd
ff
ff
4
1
1
4
3
5
ASR opr8a
ASRA
ASRX
ASR oprx8,X
ASR ,X
ASR oprx8,SP
Arithmetic Shift Right
 –– 
DIR
INH
INH
IX1
IX
SP1
37
47
57
67
77
9E67
dd
ff
ff
4
1
1
4
3
5
BCC rel Branch if Carry Bit Clear Branch if (C) = 0 ––––––REL 24 rr 3
Cb0
b7 0
b0
b7 C
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MOTOROLA M68HC08 Family Reference Guide 7
BCLR n,opr8a Clear Bit n in Memory Mn ←0 ––––––
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
BCS rel Branch if Carry Bit Set
(Same as BLO) Branch if (C) = 1 ––––––REL 25 rr 3
BEQ rel Branch if Equal Branch if (Z) = 1 ––––––REL 27 rr 3
BGE rel Branch if Greater Than or Equal To
(Signed Operands) Branch if (N ⊕ V) = 0 ––––––REL 90 rr 3
BGT rel Branch if Greater Than
(Signed Operands) Branch if (Z) | (N ⊕ V) = 0 ––––––REL 92 rr 3
BHCC rel Branch if Half Carry Bit
Clear Branch if (H) = 0 ––––––REL 28 rr 3
BHCS rel Branch if Half Carry Bit
Set Branch if (H) = 1 ––––––REL 29 rr 3
BHI rel Branch if Higher Branch if (C) | (Z) = 0 ––––––REL 22 rr 3
BHS rel Branch if Higher or Same
(Same as BCC) Branch if (C) = 0 ––––––REL 24 rr 3
BIH rel Branch if IRQ Pin High Branch if IRQ pin = 1 ––––––REL 2F rr 3
BIL rel Branch if IRQ Pin Low Branch if IRQ pin = 0 ––––––REL 2E rr 3
BIT #opr8i
BIT opr8a
BIT opr16a
BIT oprx16,X
BIT oprx8,X
BIT ,X
BIT oprx16,SP
BIT oprx8,SP
Bit Test (A) & (M) (CCR Updated but Operands
Not Changed) 0––
 –
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A5
B5
C5
D5
E5
F5
9ED5
9EE5
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
2
5
4
BLE rel Branch if Less Than or Equal To
(Signed Operands) Branch if (Z) | (N ⊕ V) = 1 ––––––REL 93 rr 3
BLO rel Branch if Lower
(Same as BCS) Branch if (C) = 1 ––––––REL 25 rr 3
BLS rel Branch if Lower or Same Branch if (C) | (Z) = 1 ––––––REL 23 rr 3
BLT rel Branch if Less Than
(Signed Operands) Branch if (N ⊕ V ) = 1––––––REL 91 rr 3
BMC rel Branch if Interrupt Mask
Clear Branch if (I) = 0 ––––––REL 2C rr 3
BMI rel Branch if Minus Branch if (N) = 1 ––––––REL 2B rr 3
Table 2. Instruction Set Summary (Sheet 2 of 8)
Source
Form Operation Description Effect
on CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
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BMS rel Branch if Interrupt Mask
Set Branch if (I) = 1 ––––––REL 2D rr 3
BNE rel Branch if Not Equal Branch if (Z) = 0 ––––––REL 26 rr 3
BPL rel Branch if Plus Branch if (N) = 0 ––––––REL 2A rr 3
BRA rel Branch Always No Test ––––––REL 20 rr 3
BRCLR n,opr8a,rel Branch if Bit nin Memory
Clear Branch if (Mn) = 0 –––––

DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BRN rel Branch Never Uses 3 Bus Cycles ––––––REL 21 rr 3
BRSET n,opr8a,rel Branch if Bit nin Memory
Set Branch if (Mn) = 1 –––––

DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BSET n,opr8a Set Bit n in Memory Mn ←1 ––––––
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
BSR rel Branch to Subroutine
PC ← (PC) + $0002
push (PCL); SP ←(SP) –$0001
push (PCH); SP ←(SP) –$0001
PC ←(PC) + rel
––––––REL AD rr 4
CBEQ opr8a,rel
CBEQA #opr8i,rel
CBEQX #opr8i,rel
CBEQ oprx8,X+,rel
CBEQ ,X+,rel
CBEQ oprx8,SP,rel
Compare and Branch if
Equal
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (X) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
––––––
DIR
IMM
IMM
IX1+
IX+
SP1
31
41
51
61
71
9E61
dd rr
ii rr
ii rr
ff rr
rr
ff rr
5
4
4
5
4
6
CLC Clear Carry Bit C ←0 –––––0INH 98 1
CLI Clear Interrupt Mask Bit I ←0 ––0–––INH 9A 2
Table 2. Instruction Set Summary (Sheet 3 of 8)
Source
Form Operation Description Effect
on CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
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MOTOROLA M68HC08 Family Reference Guide 9
CLR opr8a
CLRA
CLRX
CLRH
CLR oprx8,X
CLR ,X
CLR oprx8,SP
Clear
M ←$00
A ←$00
X ←$00
H ←$00
M ←$00
M ←$00
M ←$00
0––01–
DIR
INH
INH
INH
IX1
IX
SP1
3F
4F
5F
8C
6F
7F
9E6F
dd
ff
ff
3
1
1
1
3
2
4
CMP #opr8i
CMP opr8a
CMP opr16a
CMP oprx16,X
CMP oprx8,X
CMP ,X
CMP oprx16,SP
CMP oprx8,SP
Compare Accumulator
with Memory
(A) –(M)
(CCR Updated But Operands Not
Changed)
 –– 
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A1
B1
C1
D1
E1
F1
9ED1
9EE1
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
2
5
4
COM opr8a
COMA
COMX
COM oprx8,X
COM ,X
COM oprx8,SP
Complement
(One’s Complement)
M ←(M)= $FF –(M)
A ←(A) = $FF –(A)
X ←(X) = $FF –(X)
M ←(M) = $FF –(M)
M ←(M) = $FF –(M)
M ←(M) = $FF –(M)
0––
 1
DIR
INH
INH
IX1
IX
SP1
33
43
53
63
73
9E63
dd
ff
ff
4
1
1
4
3
5
CPHX #opr
CPHX opr Compare Index Register (H:X) with Memory
(H:X) –(M:M + $0001)
(CCR Updated But Operands Not
Changed)
 –– 
IMM
DIR 65 75 jj ii+1 dd 3 4
CPX #opr8i
CPX opr8a
CPX opr16a
CPX oprx16,X
CPX oprx8,X
CPX ,X
CPX oprx16,SP
CPX oprx8,SP
Compare X (Index
Register Low) with
Memory
(X) –(M)
(CCR Updated But Operands Not
Changed)
 –– 
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A3
B3
C3
D3
E3
F3
9ED3
9EE3
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
2
5
4
DAA Decimal Adjust AccumulatorAfterADDor
ADC of BCD Values (A)10 U––
 INH 72 2
DBNZ opr8a,rel
DBNZA rel
DBNZX rel
DBNZ oprx8,X,rel
DBNZ ,X,rel
DBNZ oprx8,SP,rel
Decrement and Branch if
Not Zero
Decrement A, X, or M
Branch if (result) ≠ 0
DBNZX Affects X Not H ––––––
DIR
INH
INH
IX1
IX
SP1
3B
4B
5B
6B
7B
9E6B
dd rr
rr
rr
ff rr
rr
ff rr
5
3
3
5
4
6
DEC opr8a
DECA
DECX
DEC oprx8,X
DEC ,X
DEC oprx8,SP
Decrement
M ←(M) –$01
A ←(A) –$01
X ←(X) –$01
M ←(M) –$01
M ←(M) –$01
M ←(M) –$01
 ––  –
DIR
INH
INH
IX1
IX
SP1
3A
4A
5A
6A
7A
9E6A
dd
ff
ff
4
1
1
4
3
5
DIV Divide A ←(H:A)÷(X)
H ←Remainder ––––
 INH 52 7
Table 2. Instruction Set Summary (Sheet 4 of 8)
Source
Form Operation Description Effect
on CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
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EOR #opr8i
EOR opr8a
EOR opr16a
EOR oprx16,X
EOR oprx8,X
EOR ,X
EOR oprx16,SP
EOR oprx8,SP
Exclusive OR
Memory with
Accumulator A ←(A ⊕M) 0 ––
 –
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A8
B8
C8
D8
E8
F8
9ED8
9EE8
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
2
5
4
INC opr8a
INCA
INCX
INC oprx8,X
INC ,X
INC oprx8,SP
Increment
M ←(M) + $01
A ←(A) + $01
X ←(X) + $01
M ←(M) + $01
M ←(M) + $01
M ←(M) + $01
 ––  –
DIR
INH
INH
IX1
IX
SP1
3C
4C
5C
6C
7C
9E6C
dd
ff
ff
4
1
1
4
3
5
JMP opr8a
JMP opr16a
JMP oprx16,X
JMP oprx8,X
JMP ,X
Jump PC ←Jump Address ––––––
DIR
EXT
IX2
IX1
IX
BC
CC
DC
EC
FC
dd
hh ll
ee ff
ff
2
3
4
3
3
JSR opr8a
JSR opr16a
JSR oprx16,X
JSR oprx8,X
JSR ,X
Jump to Subroutine
PC ←(PC) + n(n= 1, 2, or 3)
Push (PCL); SP ←(SP) –$0001
Push (PCH); SP ←(SP) –$0001
PC ←Unconditional Address
––––––
DIR
EXT
IX2
IX1
IX
BD
CD
DD
ED
FD
dd
hh ll
ee ff
ff
4
5
6
5
4
LDA #opr8i
LDA opr8a
LDA opr16a
LDA oprx16,X
LDA oprx8,X
LDA ,X
LDA oprx16,SP
LDA oprx8,SP
Load Accumulator from
Memory A ←(M) 0 ––
 –
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A6
B6
C6
D6
E6
F6
9ED6
9EE6
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
2
5
4
LDHX #opr
LDHX opr LoadIndexRegister(H:X) from Memory H:X ← (M:M + $0001)0––
 –IMM
DIR 45 55 ii jj dd 3 4
LDX #opr8i
LDX opr8a
LDX opr16a
LDX oprx16,X
LDX oprx8,X
LDX ,X
LDX oprx16,SP
LDX oprx8,SP
Load X (Index Register
Low) from Memory X ←(M) 0 ––
 –
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
AE
BE
CE
DE
EE
FE
9EDE
9EEE
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
2
5
4
LSL opr8a
LSLA
LSLX
LSL oprx8,X
LSL ,X
LSL oprx8,SP
Logical Shift Left
(Same as ASL)
 –– 
DIR
INH
INH
IX1
IX
SP1
38
48
58
68
78
9E68
dd
ff
ff
4
1
1
4
3
5
Table 2. Instruction Set Summary (Sheet 5 of 8)
Source
Form Operation Description Effect
on CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
Cb0
b7 0
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