Freescale Semiconductor MPC5510 User manual

© Freescale Semiconductor, Inc., 2012. All rights reserved.
Freescale Semiconductor MPC5510RM
Rev. 1.1, 04/2012
This is the MPC5510 Reference Manual set consisting of the following files:
• MPC5510 Reference Manual Addendum, Rev 1
• MPC5510 Reference Manual, Rev 1
MPC5510 Reference Manual

© Freescale Semiconductor, Inc., 2012. All rights reserved.
Freescale Semiconductor
Reference Manual Addendum MPC5510RMAD
Rev. 1, 04/2012
Table of Contents
This addendum document describes corrections to the
MPC5510 Microcontroller Reference Manual, order
number MPC5510RM. For convenience, the addenda
items are grouped by revision. Please check our website
at http://www.freescale.com/powerarchitecture for the
latest updates.
The current version available of the MPC5510
Microcontroller Reference Manual is Revision 1.0.
MPC5510 Reference Manual
Addendum
1 Addendum for Revision 1.0. . . . . . . . . . . . . . . . . . 2
2 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . 5

MPC5510 Reference Manual Addendum, Rev. 1
Addendum for Revision 1.0
Freescale Semiconductor2
1 Addendum for Revision 1.0
Table 1. MPC5510RM Rev 1.0 Addendum
Location Description
Section 2.2
“Signal Properties
Summary”
Added a note just above “MPC5510 Signal Properties” table:
“Please note that analog input pins (ANx) are directly connected to the eQADC and that they are not routed
through the PCRx register; thus, changes in the PCR register does not affect these inputs.”
Section 3.3
“System Clock
Architecture Block
Diagram”
Updated the paragraph:
To optimize system power consumption, the MPC5510 supports system-level clock dividers, static clock
gating using peripheral-level module disable (MDIS) bits and a system-level halt mechanism. Figure 3-2
shows the device-level clock gating mechanism for the MPC5510. Figure 3-3 shows a more detailed
implementation of the MDIS and halt mechanism connections for a given peripheral. These features are
detailed in subsequent sections.
Added a new NOTE:
While combining DMA with peripheral modules (for example eSCI), the user has to use LPCLKDIVx = 0
(no divide) to ensure that the DMA.DONE (same as DMA ACK) is correctly acknowledged by the
peripheral. Otherwise, DMA.DONE may not be sampled correctly, leading to data loss. In the case of eSCI
peripheral, BERR flag will be set and the peripheral behavior will be unexpected if LPCLKDIV4 > 0.

Addendum for Revision 1.0
MPC5510 Reference Manual Addendum, Rev. 1
Freescale Semiconductor 3
Section 3.3
“System Clock
Architecture Block
Diagram”
Updated Figure 3-2 ”System Clock Architecture”.
Table 1. MPC5510RM Rev 1.0 Addendum
Location Description
Protocol clock
Oscillator clock
Module clock
MCKO
MCKO
divider
CLK_SRC
MDIS
FlexRAY
Protocol clock
CLK_SRC
MDIS
FlexCAN_A
LPCLKDIV0
MDIS
DSPI_A
MDIS
ESCI_A,IIC_A,PIT
(RTI)
Protocol clock
CLK_SRC
MDIS
FlexCAN_B-F
LPCLKDIV2
CLKOUT
CLKOUT
divider
MDIS
DSPI_B-D
MDIS
ESCI_B-H
MDIS
eMIOS
MDIS
MLB
Cores INTC, DMA, SIU, RAM
Flash, BAM, AIPS, AXBS,
LPCLKDIV3
LPCLKDIV4
LPCLKDIV5
LPCLKDIV6
LPCLKDIV1
Switcher
and
divider Nexus
EBI
NPC
Module clock
DIV/2
PLL
IRC
XOSC
Bypass clock
System clock
Module clock
MCM, eQADC

MPC5510 Reference Manual Addendum, Rev. 1
Addendum for Revision 1.0
Freescale Semiconductor4
Section 3.5.2
“Halt Clock Gating” Added a note: SIU_HLT is not delayed by any pending interrupt for specific modules to be serviced. If any interrupt is
raised after the SIU_HLT request, it may cause the interrupt to hang. To avoid this, it is advised that all
interrupts are disabled before entering the SIU_HLT state and then, re-enabled once SIU_HLT is exited.
The result is that any interrupt will be flagged, but not triggered within its specific interrupt service routine.
Once the SIU_HLT has been enabled, any pending interrupt will be taken as normal. In the case of STOP
mode exit, an external interrupt may be required. In this case, the specific exit interrupt may be enabled,
but software must ensure the interrupt does not occur simultaneously with SIU_HLT being enabled.
Section 5.3.2
”Low-power Mode
Entry”
Updated “The system clock source should be set to the 16 MHz IRC prior to ...” to “The system clock source
needs be set to the 16 MHz IRC (with the default divide by 1 system clock configuration) prior to ...”.
Section 6.3.2.2
“Reset Status
Register
(SIU_RSR)”
Updated point 1. The updated text is as follows:
“If any reset request has negated and the device is still in the resulting reset, and then an external reset is
requested, both the original reset type and external reset status bits will be set. In this case, the device
started the reset sequence due to a non-external reset request but ended the reset sequence after an
external reset request.”
Updated figure note 3 of Figure 6-3, “Reset Status Register (SIU_RSR”. The updated text is as follows:
“The ERS bit is also set if the RESET pin is held low to extend the reset sequence.”
Section 6.3.2.25
“System Clock
Register
(SIU_SYSCLK)”
Aligned table 6-27 “LPCLKDIV Module Groups”, as mentioned below.
Section 24.1.1
“Block Diagram” Added a figure note for peripheral clock in the “eSCI Block Diagram” figure:
Refer to Section 3.3, “ System Clock Architecture Block Diagram”.
Section 24.3.2.3
“eSCI Data
Register
(ESCIx_DR)”
Added a note:
eSCI transmission delay will depend on the actual Tx load into the Data Register referenced with the
internal clock, if the load occurs before 45% of a bit time has passed, the Tx load will be transmitted in less
than a bit time. Otherwise, the Tx will take up to 1.5 of a bit time.
Table 1. MPC5510RM Rev 1.0 Addendum
Location Description
Table 6-27: LPCLKDIV Module Groups
LPCLKDIVnModules
LPCLKDIV0 FlexCAN_A, DSPI_A
LPCLKDIV1 ESCI_A, I2C_A, PIT
LPCLKDIV2 FlexCAN_B-F
LPCLKDIV3 DSPI_B-D
LPCLKDIV4 ESCI_B-H
LPCLKDIV5 eMIOS
LPCLKDIV6 MLB
LPCLKDIV7 Reserved

Revision History
MPC5510 Reference Manual Addendum, Rev. 1
Freescale Semiconductor 5
2 Revision History
Table 2 provides a revision history for this document.
Section 31.4.3.3
”External Trigger
Input Multiplexing”
• Updated the title from “External Trigger from eTPU to eMIOS Channels“ to “External Trigger Input
Multiplexing”.
• Updated the text of this section to:
The four eQADC external trigger inputs can be connected to two different external pins or one of two PIT
channels. The input source for each eQADC external trigger is individually specified in the IMUX Select
Register 0 (SIU_ISEL0). Figure 6-50 gives an example of the multiplexing of an eQADC external trigger
input. As shown in the figure, the ETRIG[0] input of the eQADC can be connected to the PC4 pin, the PG4
pin, the PIT7 channel, or the PIT8 channel. Remaining ETRIG inputs are multiplexed in the same manner.
The eQADC trigger numbers specified by SIU_ETISR[TSEL(0-3)] correspond to CFIFO numbers 0-3. To
calculate the CFIFO number that each trigger is connected to, divide the eDMA channel number by 2.
Table 2. Revision History Table
Rev. Number Substantive Changes Date of Release
1.0 First release. 04/2012
Table 1. MPC5510RM Rev 1.0 Addendum
Location Description

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reserved.
MPC5510RMAD
Rev. 1
04/2012

MPC5510 Microcontroller Family
Reference Manual
Devices Supported:
MPC5517G/E/S
MPC5516G/E/S
MPC5515S
MPC5514G/E
Document Number: MPC5510RM
Rev. 1
06/2008
PRELIMINARY

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Home Page:
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Web Support:
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2100 East Elliot Road
Tempe, Arizona 85284
1-800-521-6274 or [phone]
www.freescale.com/support
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
[phone] (English)
[phone] (English)
[phone] (German)
[phone] (French)
www.freescale.com/support
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
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Tokyo 153-0064
Japan
0120 191014 or [phone]
[email protected]
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Exchange Building 23F
No. 118 Jianguo Road
Chaoyang District
Beijing 100022
China
[phone]
[email protected]
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or [phone]
Fax: [phone]
[e-mail]
Information in this document is provided solely to enable system and
software implementers to use Freescale Semiconductor products. There are
no express or implied copyright licenses granted hereunder to design or
fabricate any integrated circuits or integrated circuits based on the
information in this document.
Freescale Semiconductor reserves the right to make changes without further
notice to anyproducts herein. Freescale Semiconductor makes no warranty,
representation or guarantee regarding the suitability of its products for any
particular purpose, nor does Freescale Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or
incidental damages. “Typical” parameters that may be provided in Freescale
Semiconductordata sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer
application by customer’s technical experts. Freescale Semiconductor does
not convey any license under its patent rights nor the rights of others.
FreescaleSemiconductorproductsarenotdesigned,intended,or authorized
for use as components in systems intendedfor surgical implant intothe body,
or other applications intended to support or sustain life, or for any other
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create a situation where personal injury or death may occur. Should Buyer
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Semiconductor and its officers, employees, subsidiaries, affiliates, and
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use, even if such claim alleges that Freescale Semiconductor was negligent
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© Freescale Semiconductor, Inc. 2007, 2008. All rights reserved.
MPC5510RM
Rev. 1
06/2008

MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor i
Preliminary
Chapter 1
Overview
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.3 MPC5510 Family Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3.1 Family Feature Set Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.4 Chip-Level Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.5 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.6 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Chapter 2
Signal Descriptions
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.3 Power and Ground Supply Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.4 Pinout – 144 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.5 Pinout – 176 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.6 Pinout – 208 BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.7 Detailed External Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.7.1 Port A Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.7.2 Port B Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.7.3 Port C Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.7.4 Port D Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.7.5 Port E Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2.7.6 Port F Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.7.7 Port G Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
2.7.8 Port H Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
2.7.9 Port J Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
2.7.10 Port K Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
2.7.11 Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
2.7.12 Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
Chapter 3
System Clock Description
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2 Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2.1 External High-Frequency Crystal (XOSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2.2 External Low-Frequency Crystal (32kXOSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.2.3 Internal High-Frequency RC Oscillator (IRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.2.4 Internal Low-Frequency RC Oscillator (32kRC) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 System Clock Architecture Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.4 Clock Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.4.1 System Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.4.2 System Clock Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5