Freescale Semiconductor KV31F User manual

KV31F Sub-Family Reference Manual
Supports: MKV31F512VLL12, MKV31F512VLH12
Document Number: KV31P100M120SF7RM
Rev. 3, 7/2014

KV31F Sub-Family Reference Manual , Rev. 3, 7/2014
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Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................43
1.1.1 Purpose.........................................................................................................................................................43
1.1.2 Audience......................................................................................................................................................43
1.2 Conventions..................................................................................................................................................................43
1.2.1 Numbering systems......................................................................................................................................43
1.2.2 Typographic notation...................................................................................................................................44
1.2.3 Special terms................................................................................................................................................44
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................45
2.2 Module Functional Categories......................................................................................................................................45
2.2.1 ARM® Cortex®-M4 Core Modules............................................................................................................46
2.2.2 System Modules...........................................................................................................................................47
2.2.3 Memories and Memory Interfaces...............................................................................................................47
2.2.4 Clocks...........................................................................................................................................................48
2.2.5 Security and Integrity modules....................................................................................................................48
2.2.6 Analog modules...........................................................................................................................................49
2.2.7 Timer modules.............................................................................................................................................49
2.2.8 Communication interfaces...........................................................................................................................50
2.2.9 Human-machine interfaces..........................................................................................................................51
2.3 Orderable part numbers.................................................................................................................................................51
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................53
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Section number Title Page
3.2 Core modules................................................................................................................................................................53
3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................53
3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................55
3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................61
3.2.4 FPU Configuration.......................................................................................................................................62
3.2.5 JTAG Controller Configuration...................................................................................................................62
3.3 System modules............................................................................................................................................................63
3.3.1 SIM Configuration.......................................................................................................................................63
3.3.2 System Mode Controller (SMC) Configuration...........................................................................................64
3.3.3 PMC Configuration......................................................................................................................................64
3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................65
3.3.5 MCM Configuration....................................................................................................................................66
3.3.6 Crossbar-Light Switch Configuration..........................................................................................................67
3.3.7 Peripheral Bridge Configuration..................................................................................................................69
3.3.8 DMA request multiplexer configuration......................................................................................................70
3.3.9 DMA Controller Configuration...................................................................................................................73
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Section number Title Page
3.3.10 External Watchdog Monitor (EWM) Configuration....................................................................................74
3.3.11 Watchdog Configuration..............................................................................................................................76
3.4 Clock modules..............................................................................................................................................................77
3.4.1 MCG Configuration.....................................................................................................................................77
3.4.2 OSC Configuration......................................................................................................................................79
3.5 Memories and memory interfaces.................................................................................................................................79
3.5.1 Flash Memory Configuration.......................................................................................................................79
3.5.2 Flash Memory Controller Configuration.....................................................................................................82
3.5.3 SRAM Configuration...................................................................................................................................83
3.5.4 System Register File Configuration.............................................................................................................84
3.5.5 EzPort Configuration...................................................................................................................................85
3.5.6 FlexBus Configuration.................................................................................................................................86
3.6 Security.........................................................................................................................................................................89
3.6.1 CRC Configuration......................................................................................................................................89
3.6.2 RNG Configuration......................................................................................................................................90
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3.7 Analog...........................................................................................................................................................................91
3.7.1 16-bit SAR ADC Configuration..................................................................................................................91
3.7.2 CMP Configuration......................................................................................................................................98
3.7.3 12-bit DAC Configuration...........................................................................................................................100
3.7.4 VREF Configuration....................................................................................................................................102
3.8 Timers...........................................................................................................................................................................103
3.8.1 PDB Configuration......................................................................................................................................103
3.8.2 FlexTimer Configuration.............................................................................................................................106
3.8.3 PIT Configuration........................................................................................................................................112
3.8.4 Low-power timer configuration...................................................................................................................113
3.9 Communication interfaces............................................................................................................................................115
3.9.1 SPI configuration.........................................................................................................................................115
3.9.2 I2C Configuration........................................................................................................................................119
3.9.3 UART Configuration...................................................................................................................................119
3.9.4 LPUART configuration................................................................................................................................122
3.10 Human-machine interfaces...........................................................................................................................................122
3.10.1 GPIO configuration......................................................................................................................................123
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................125
4.2 System memory map.....................................................................................................................................................125
4.2.1 Aliased bit-band regions..............................................................................................................................127
4.2.2 Flash Access Control Introduction...............................................................................................................128
4.3 Flash Memory Map.......................................................................................................................................................128
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................129
4.4 SRAM memory map.....................................................................................................................................................129
4.5 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................130
4.5.1 Read-after-write sequence and required serialization of memory operations..............................................130
4.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................130
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Section number Title Page
4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................134
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................137
5.2 Programming model......................................................................................................................................................137
5.3 High-Level device clocking diagram............................................................................................................................137
5.4 Clock definitions...........................................................................................................................................................138
5.4.1 Device clock summary.................................................................................................................................139
5.5 Internal clocking requirements.....................................................................................................................................141
5.5.1 Clock divider values after reset....................................................................................................................142
5.5.2 VLPR mode clocking...................................................................................................................................143
5.6 Clock Gating.................................................................................................................................................................144
5.7 Module clocks...............................................................................................................................................................144
5.7.1 PMC 1-kHz LPO clock................................................................................................................................145
5.7.2 IRC 48MHz clock........................................................................................................................................145
5.7.3 WDOG clocking..........................................................................................................................................146
5.7.4 Debug trace clock.........................................................................................................................................147
5.7.5 PORT digital filter clocking.........................................................................................................................147
5.7.6 LPTMR clocking..........................................................................................................................................148
5.7.7 CLKOUT32K clocking................................................................................................................................148
5.7.8 UART clocking............................................................................................................................................149
5.7.9 LPUART0 clocking.....................................................................................................................................149
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................151
6.2 Reset..............................................................................................................................................................................152
6.2.1 Power-on reset (POR)..................................................................................................................................152
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6.2.2 System reset sources....................................................................................................................................152
6.2.3 MCU Resets.................................................................................................................................................156
6.2.4 Reset Pin .....................................................................................................................................................157
6.2.5 Debug resets.................................................................................................................................................158
6.3 Boot...............................................................................................................................................................................159
6.3.1 Boot sources.................................................................................................................................................159
6.3.2 Boot options.................................................................................................................................................159
6.3.3 FOPT boot options.......................................................................................................................................159
6.3.4 Boot sequence..............................................................................................................................................161
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................163
7.2 Clocking modes............................................................................................................................................................163
7.2.1 Partial Stop...................................................................................................................................................163
7.2.2 DMA Wakeup..............................................................................................................................................164
7.2.3 Compute Operation......................................................................................................................................165
7.2.4 Peripheral Doze............................................................................................................................................166
7.2.5 Clock Gating................................................................................................................................................167
7.3 Power Modes Description.............................................................................................................................................167
7.4 Entering and exiting power modes...............................................................................................................................169
7.5 Power mode transitions.................................................................................................................................................170
7.6 Power modes shutdown sequencing.............................................................................................................................171
7.7 Flash Program Restrictions...........................................................................................................................................172
7.8 Module Operation in Low Power Modes......................................................................................................................172
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................177
8.2 Flash Security...............................................................................................................................................................177
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8.3 Security Interactions with other Modules.....................................................................................................................178
8.3.1 Security interactions with FlexBus..............................................................................................................178
8.3.2 Security Interactions with EzPort................................................................................................................178
8.3.3 Security Interactions with Debug.................................................................................................................178
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................181
9.1.1 References....................................................................................................................................................183
9.2 The Debug Port.............................................................................................................................................................183
9.2.1 JTAG-to-SWD change sequence.................................................................................................................184
9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................184
9.3 Debug Port Pin Descriptions.........................................................................................................................................185
9.4 System TAP connection................................................................................................................................................185
9.4.1 IR Codes.......................................................................................................................................................185
9.5 JTAG status and control registers.................................................................................................................................186
9.5.1 MDM-AP Control Register..........................................................................................................................187
9.5.2 MDM-AP Status Register............................................................................................................................189
9.6 Debug Resets................................................................................................................................................................190
9.7 AHB-AP........................................................................................................................................................................191
9.8 ITM...............................................................................................................................................................................191
9.9 Core Trace Connectivity...............................................................................................................................................192
9.10 TPIU..............................................................................................................................................................................192
9.11 DWT.............................................................................................................................................................................192
9.12 Debug in Low Power Modes........................................................................................................................................193
9.12.1 Debug Module State in Low Power Modes.................................................................................................193
9.13 Debug & Security.........................................................................................................................................................194
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................195
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10.2 Signal Multiplexing Integration....................................................................................................................................195
10.2.1 Port control and interrupt module features..................................................................................................196
10.2.2 Clock gating.................................................................................................................................................197
10.2.3 Signal multiplexing constraints....................................................................................................................197
10.3 Pinout............................................................................................................................................................................197
10.3.1 KV31F Signal Multiplexing and Pin Assignments......................................................................................197
10.3.2 KV31F Pinouts.............................................................................................................................................201
10.4 Module Signal Description Tables................................................................................................................................204
10.4.1 Core Modules...............................................................................................................................................204
10.4.2 System Modules...........................................................................................................................................204
10.4.3 Clock Modules.............................................................................................................................................205
10.4.4 Memories and Memory Interfaces...............................................................................................................205
10.4.5 Analog..........................................................................................................................................................208
10.4.6 Timer Modules.............................................................................................................................................210
10.4.7 Communication Interfaces...........................................................................................................................211
10.4.8 Human-Machine Interfaces (HMI)..............................................................................................................213
Chapter 11
Port Control and Interrupts (PORT)
11.1 Introduction...................................................................................................................................................................215
11.2 Overview.......................................................................................................................................................................215
11.2.1 Features........................................................................................................................................................215
11.2.2 Modes of operation......................................................................................................................................216
11.3 External signal description............................................................................................................................................217
11.4 Detailed signal description............................................................................................................................................217
11.5 Memory map and register definition.............................................................................................................................217
11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................224
11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................226
11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................227
11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................228
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