Freescale Semiconductor KV31F User manual

KV31F Sub-Family Reference Manual
Supports: MKV31F512VLL12, MKV31F512VLH12
Document Number: KV31P100M120SF7RM
Rev. 3, 7/2014

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Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................43
1.1.1 Purpose.........................................................................................................................................................43
1.1.2 Audience......................................................................................................................................................43
1.2 Conventions..................................................................................................................................................................43
1.2.1 Numbering systems......................................................................................................................................43
1.2.2 Typographic notation...................................................................................................................................44
1.2.3 Special terms................................................................................................................................................44
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................45
2.2 Module Functional Categories......................................................................................................................................45
2.2.1 ARM® Cortex®-M4 Core Modules............................................................................................................46
2.2.2 System Modules...........................................................................................................................................47
2.2.3 Memories and Memory Interfaces...............................................................................................................47
2.2.4 Clocks...........................................................................................................................................................48
2.2.5 Security and Integrity modules....................................................................................................................48
2.2.6 Analog modules...........................................................................................................................................49
2.2.7 Timer modules.............................................................................................................................................49
2.2.8 Communication interfaces...........................................................................................................................50
2.2.9 Human-machine interfaces..........................................................................................................................51
2.3 Orderable part numbers.................................................................................................................................................51
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................53
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3.2 Core modules................................................................................................................................................................53
3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................53
3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................55
3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................61
3.2.4 FPU Configuration.......................................................................................................................................62
3.2.5 JTAG Controller Configuration...................................................................................................................62
3.3 System modules............................................................................................................................................................63
3.3.1 SIM Configuration.......................................................................................................................................63
3.3.2 System Mode Controller (SMC) Configuration...........................................................................................64
3.3.3 PMC Configuration......................................................................................................................................64
3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................65
3.3.5 MCM Configuration....................................................................................................................................66
3.3.6 Crossbar-Light Switch Configuration..........................................................................................................67
3.3.7 Peripheral Bridge Configuration..................................................................................................................69
3.3.8 DMA request multiplexer configuration......................................................................................................70
3.3.9 DMA Controller Configuration...................................................................................................................73
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3.3.10 External Watchdog Monitor (EWM) Configuration....................................................................................74
3.3.11 Watchdog Configuration..............................................................................................................................76
3.4 Clock modules..............................................................................................................................................................77
3.4.1 MCG Configuration.....................................................................................................................................77
3.4.2 OSC Configuration......................................................................................................................................79
3.5 Memories and memory interfaces.................................................................................................................................79
3.5.1 Flash Memory Configuration.......................................................................................................................79
3.5.2 Flash Memory Controller Configuration.....................................................................................................82
3.5.3 SRAM Configuration...................................................................................................................................83
3.5.4 System Register File Configuration.............................................................................................................84
3.5.5 EzPort Configuration...................................................................................................................................85
3.5.6 FlexBus Configuration.................................................................................................................................86
3.6 Security.........................................................................................................................................................................89
3.6.1 CRC Configuration......................................................................................................................................89
3.6.2 RNG Configuration......................................................................................................................................90
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3.7 Analog...........................................................................................................................................................................91
3.7.1 16-bit SAR ADC Configuration..................................................................................................................91
3.7.2 CMP Configuration......................................................................................................................................98
3.7.3 12-bit DAC Configuration...........................................................................................................................100
3.7.4 VREF Configuration....................................................................................................................................102
3.8 Timers...........................................................................................................................................................................103
3.8.1 PDB Configuration......................................................................................................................................103
3.8.2 FlexTimer Configuration.............................................................................................................................106
3.8.3 PIT Configuration........................................................................................................................................112
3.8.4 Low-power timer configuration...................................................................................................................113
3.9 Communication interfaces............................................................................................................................................115
3.9.1 SPI configuration.........................................................................................................................................115
3.9.2 I2C Configuration........................................................................................................................................119
3.9.3 UART Configuration...................................................................................................................................119
3.9.4 LPUART configuration................................................................................................................................122
3.10 Human-machine interfaces...........................................................................................................................................122
3.10.1 GPIO configuration......................................................................................................................................123
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................125
4.2 System memory map.....................................................................................................................................................125
4.2.1 Aliased bit-band regions..............................................................................................................................127
4.2.2 Flash Access Control Introduction...............................................................................................................128
4.3 Flash Memory Map.......................................................................................................................................................128
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................129
4.4 SRAM memory map.....................................................................................................................................................129
4.5 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................130
4.5.1 Read-after-write sequence and required serialization of memory operations..............................................130
4.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................130
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4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................134
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................137
5.2 Programming model......................................................................................................................................................137
5.3 High-Level device clocking diagram............................................................................................................................137
5.4 Clock definitions...........................................................................................................................................................138
5.4.1 Device clock summary.................................................................................................................................139
5.5 Internal clocking requirements.....................................................................................................................................141
5.5.1 Clock divider values after reset....................................................................................................................142
5.5.2 VLPR mode clocking...................................................................................................................................143
5.6 Clock Gating.................................................................................................................................................................144
5.7 Module clocks...............................................................................................................................................................144
5.7.1 PMC 1-kHz LPO clock................................................................................................................................145
5.7.2 IRC 48MHz clock........................................................................................................................................145
5.7.3 WDOG clocking..........................................................................................................................................146
5.7.4 Debug trace clock.........................................................................................................................................147
5.7.5 PORT digital filter clocking.........................................................................................................................147
5.7.6 LPTMR clocking..........................................................................................................................................148
5.7.7 CLKOUT32K clocking................................................................................................................................148
5.7.8 UART clocking............................................................................................................................................149
5.7.9 LPUART0 clocking.....................................................................................................................................149
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................151
6.2 Reset..............................................................................................................................................................................152
6.2.1 Power-on reset (POR)..................................................................................................................................152
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6.2.2 System reset sources....................................................................................................................................152
6.2.3 MCU Resets.................................................................................................................................................156
6.2.4 Reset Pin .....................................................................................................................................................157
6.2.5 Debug resets.................................................................................................................................................158
6.3 Boot...............................................................................................................................................................................159
6.3.1 Boot sources.................................................................................................................................................159
6.3.2 Boot options.................................................................................................................................................159
6.3.3 FOPT boot options.......................................................................................................................................159
6.3.4 Boot sequence..............................................................................................................................................161
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................163
7.2 Clocking modes............................................................................................................................................................163
7.2.1 Partial Stop...................................................................................................................................................163
7.2.2 DMA Wakeup..............................................................................................................................................164
7.2.3 Compute Operation......................................................................................................................................165
7.2.4 Peripheral Doze............................................................................................................................................166
7.2.5 Clock Gating................................................................................................................................................167
7.3 Power Modes Description.............................................................................................................................................167
7.4 Entering and exiting power modes...............................................................................................................................169
7.5 Power mode transitions.................................................................................................................................................170
7.6 Power modes shutdown sequencing.............................................................................................................................171
7.7 Flash Program Restrictions...........................................................................................................................................172
7.8 Module Operation in Low Power Modes......................................................................................................................172
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................177
8.2 Flash Security...............................................................................................................................................................177
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8.3 Security Interactions with other Modules.....................................................................................................................178
8.3.1 Security interactions with FlexBus..............................................................................................................178
8.3.2 Security Interactions with EzPort................................................................................................................178
8.3.3 Security Interactions with Debug.................................................................................................................178
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................181
9.1.1 References....................................................................................................................................................183
9.2 The Debug Port.............................................................................................................................................................183
9.2.1 JTAG-to-SWD change sequence.................................................................................................................184
9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................184
9.3 Debug Port Pin Descriptions.........................................................................................................................................185
9.4 System TAP connection................................................................................................................................................185
9.4.1 IR Codes.......................................................................................................................................................185
9.5 JTAG status and control registers.................................................................................................................................186
9.5.1 MDM-AP Control Register..........................................................................................................................187
9.5.2 MDM-AP Status Register............................................................................................................................189
9.6 Debug Resets................................................................................................................................................................190
9.7 AHB-AP........................................................................................................................................................................191
9.8 ITM...............................................................................................................................................................................191
9.9 Core Trace Connectivity...............................................................................................................................................192
9.10 TPIU..............................................................................................................................................................................192
9.11 DWT.............................................................................................................................................................................192
9.12 Debug in Low Power Modes........................................................................................................................................193
9.12.1 Debug Module State in Low Power Modes.................................................................................................193
9.13 Debug & Security.........................................................................................................................................................194
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................195
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10.2 Signal Multiplexing Integration....................................................................................................................................195
10.2.1 Port control and interrupt module features..................................................................................................196
10.2.2 Clock gating.................................................................................................................................................197
10.2.3 Signal multiplexing constraints....................................................................................................................197
10.3 Pinout............................................................................................................................................................................197
10.3.1 KV31F Signal Multiplexing and Pin Assignments......................................................................................197
10.3.2 KV31F Pinouts.............................................................................................................................................201
10.4 Module Signal Description Tables................................................................................................................................204
10.4.1 Core Modules...............................................................................................................................................204
10.4.2 System Modules...........................................................................................................................................204
10.4.3 Clock Modules.............................................................................................................................................205
10.4.4 Memories and Memory Interfaces...............................................................................................................205
10.4.5 Analog..........................................................................................................................................................208
10.4.6 Timer Modules.............................................................................................................................................210
10.4.7 Communication Interfaces...........................................................................................................................211
10.4.8 Human-Machine Interfaces (HMI)..............................................................................................................213
Chapter 11
Port Control and Interrupts (PORT)
11.1 Introduction...................................................................................................................................................................215
11.2 Overview.......................................................................................................................................................................215
11.2.1 Features........................................................................................................................................................215
11.2.2 Modes of operation......................................................................................................................................216
11.3 External signal description............................................................................................................................................217
11.4 Detailed signal description............................................................................................................................................217
11.5 Memory map and register definition.............................................................................................................................217
11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................224
11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................226
11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................227
11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................228
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11.5.5 Digital Filter Enable Register (PORTx_DFER)...........................................................................................228
11.5.6 Digital Filter Clock Register (PORTx_DFCR)............................................................................................229
11.5.7 Digital Filter Width Register (PORTx_DFWR)..........................................................................................229
11.6 Functional description...................................................................................................................................................230
11.6.1 Pin control....................................................................................................................................................230
11.6.2 Global pin control........................................................................................................................................231
11.6.3 External interrupts........................................................................................................................................231
11.6.4 Digital filter..................................................................................................................................................232
Chapter 12
System Integration Module (SIM)
12.1 Introduction...................................................................................................................................................................235
12.1.1 Features........................................................................................................................................................235
12.2 Memory map and register definition.............................................................................................................................236
12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................237
12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................238
12.2.3 System Options Register 2 (SIM_SOPT2)..................................................................................................239
12.2.4 System Options Register 4 (SIM_SOPT4)..................................................................................................241
12.2.5 System Options Register 5 (SIM_SOPT5)..................................................................................................244
12.2.6 System Options Register 7 (SIM_SOPT7)..................................................................................................245
12.2.7 System Options Register 8 (SIM_SOPT8)..................................................................................................247
12.2.8 System Device Identification Register (SIM_SDID)...................................................................................249
12.2.9 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................251
12.2.10 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................253
12.2.11 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................255
12.2.12 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................258
12.2.13 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................258
12.2.14 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................261
12.2.15 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................263
12.2.16 Unique Identification Register High (SIM_UIDH).....................................................................................264
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12.2.17 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................264
12.2.18 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................265
12.2.19 Unique Identification Register Low (SIM_UIDL)......................................................................................265
12.3 Functional description...................................................................................................................................................265
Chapter 13
Kinetis Flashloader
13.1 Chip-Specific Information............................................................................................................................................267
13.2 Introduction...................................................................................................................................................................267
13.3 Functional Description..................................................................................................................................................269
13.3.1 Memory Maps..............................................................................................................................................269
13.3.2 Kinetis Flashloader......................................................................................................................................269
13.3.3 Start-up Process............................................................................................................................................270
13.3.4 Clock Configuration.....................................................................................................................................270
13.3.5 Flashloader Protocol....................................................................................................................................271
13.3.6 Flashloader Packet Types.............................................................................................................................275
13.3.7 Flashloader Command API..........................................................................................................................282
13.3.8 Flashloader Exit state...................................................................................................................................300
13.4 Peripherals Supported...................................................................................................................................................302
13.4.1 I2C Peripheral..............................................................................................................................................302
13.4.2 SPI Peripheral..............................................................................................................................................303
13.4.3 UART Peripheral.........................................................................................................................................305
13.5 Get/SetProperty Command Properties..........................................................................................................................308
13.5.1 Property Definitions.....................................................................................................................................309
13.6 Kinetis Flashloader Status Error Codes........................................................................................................................311
Chapter 14
Reset Control Module (RCM)
14.1 Introduction...................................................................................................................................................................313
14.2 Reset memory map and register descriptions...............................................................................................................313
14.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................314
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14.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................315
14.2.3 Reset Pin Filter Control register (RCM_RPFC)..........................................................................................317
14.2.4 Reset Pin Filter Width register (RCM_RPFW)...........................................................................................318
14.2.5 Mode Register (RCM_MR).........................................................................................................................319
14.2.6 Sticky System Reset Status Register 0 (RCM_SSRS0)...............................................................................320
14.2.7 Sticky System Reset Status Register 1 (RCM_SSRS1)...............................................................................321
Chapter 15
System Mode Controller (SMC)
15.1 Introduction...................................................................................................................................................................323
15.2 Modes of operation.......................................................................................................................................................323
15.3 Memory map and register descriptions.........................................................................................................................325
15.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................326
15.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................327
15.3.3 Stop Control Register (SMC_STOPCTRL).................................................................................................329
15.3.4 Power Mode Status register (SMC_PMSTAT)...........................................................................................330
15.4 Functional description...................................................................................................................................................331
15.4.1 Power mode transitions................................................................................................................................331
15.4.2 Power mode entry/exit sequencing..............................................................................................................334
15.4.3 Run modes....................................................................................................................................................336
15.4.4 Wait modes..................................................................................................................................................338
15.4.5 Stop modes...................................................................................................................................................339
15.4.6 Debug in low power modes.........................................................................................................................342
Chapter 16
Power Management Controller (PMC)
16.1 Introduction...................................................................................................................................................................345
16.2 Features.........................................................................................................................................................................345
16.3 Low-voltage detect (LVD) system................................................................................................................................345
16.3.1 LVD reset operation.....................................................................................................................................346
16.3.2 LVD interrupt operation...............................................................................................................................346
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16.3.3 Low-voltage warning (LVW) interrupt operation.......................................................................................346
16.4 I/O retention..................................................................................................................................................................347
16.5 Memory map and register descriptions.........................................................................................................................347
16.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................348
16.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................349
16.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................350
Chapter 17
Low-Leakage Wakeup Unit (LLWU)
17.1 Introduction...................................................................................................................................................................353
17.1.1 Features........................................................................................................................................................353
17.1.2 Modes of operation......................................................................................................................................354
17.1.3 Block diagram..............................................................................................................................................355
17.2 LLWU signal descriptions............................................................................................................................................356
17.3 Memory map/register definition...................................................................................................................................356
17.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................357
17.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................358
17.3.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................359
17.3.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................360
17.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................361
17.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................363
17.3.7 LLWU Flag 2 register (LLWU_F2).............................................................................................................365
17.3.8 LLWU Flag 3 register (LLWU_F3).............................................................................................................366
17.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)..............................................................................................368
17.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)..............................................................................................369
17.4 Functional description...................................................................................................................................................370
17.4.1 LLS mode.....................................................................................................................................................371
17.4.2 VLLS modes................................................................................................................................................371
17.4.3 Initialization.................................................................................................................................................371
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Chapter 18
Miscellaneous Control Module (MCM)
18.1 Introduction...................................................................................................................................................................373
18.1.1 Features........................................................................................................................................................373
18.2 Memory map/register descriptions...............................................................................................................................373
18.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................374
18.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................374
18.2.3 Crossbar Switch (AXBS) Control Register (MCM_PLACR).....................................................................375
18.2.4 Interrupt Status and Control Register (MCM_ISCR)..................................................................................376
18.2.5 Compute Operation Control Register (MCM_CPO)...................................................................................379
18.3 Functional description...................................................................................................................................................380
18.3.1 Interrupts......................................................................................................................................................380
Chapter 19
Crossbar Switch Lite (AXBS-Lite)
19.1 Introduction...................................................................................................................................................................381
19.1.1 Features........................................................................................................................................................381
19.2 Memory Map / Register Definition...............................................................................................................................382
19.3 Functional Description..................................................................................................................................................382
19.3.1 General operation.........................................................................................................................................382
19.3.2 Arbitration....................................................................................................................................................383
19.4 Initialization/application information...........................................................................................................................384
Chapter 20
Peripheral Bridge (AIPS-Lite)
20.1 Introduction...................................................................................................................................................................387
20.1.1 Features........................................................................................................................................................387
20.1.2 General operation.........................................................................................................................................387
20.2 Functional description...................................................................................................................................................388
20.2.1 Access support.............................................................................................................................................388
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Chapter 21
Direct Memory Access Multiplexer (DMAMUX)
21.1 Introduction...................................................................................................................................................................389
21.1.1 Overview......................................................................................................................................................389
21.1.2 Features........................................................................................................................................................390
21.1.3 Modes of operation......................................................................................................................................390
21.2 External signal description............................................................................................................................................391
21.3 Memory map/register definition...................................................................................................................................391
21.3.1 Channel Configuration register (DMAMUX_CHCFGn)............................................................................392
21.4 Functional description...................................................................................................................................................393
21.4.1 DMA channels with periodic triggering capability......................................................................................393
21.4.2 DMA channels with no triggering capability...............................................................................................395
21.4.3 Always-enabled DMA sources....................................................................................................................395
21.5 Initialization/application information...........................................................................................................................397
21.5.1 Reset.............................................................................................................................................................397
21.5.2 Enabling and configuring sources................................................................................................................397
Chapter 22
Enhanced Direct Memory Access (eDMA)
22.1 Introduction...................................................................................................................................................................401
22.1.1 eDMA system block diagram......................................................................................................................401
22.1.2 Block parts...................................................................................................................................................402
22.1.3 Features........................................................................................................................................................403
22.2 Modes of operation.......................................................................................................................................................405
22.3 Memory map/register definition...................................................................................................................................405
22.3.1 TCD memory...............................................................................................................................................405
22.3.2 TCD initialization........................................................................................................................................406
22.3.3 TCD structure...............................................................................................................................................406
22.3.4 Reserved memory and bit fields...................................................................................................................408
22.3.1 Control Register (DMA_CR).......................................................................................................................418
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22.3.2 Error Status Register (DMA_ES)................................................................................................................421
22.3.3 Enable Request Register (DMA_ERQ).......................................................................................................423
22.3.4 Enable Error Interrupt Register (DMA_EEI)...............................................................................................425
22.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)..................................................................................427
22.3.6 Set Enable Error Interrupt Register (DMA_SEEI)......................................................................................428
22.3.7 Clear Enable Request Register (DMA_CERQ)...........................................................................................429
22.3.8 Set Enable Request Register (DMA_SERQ)...............................................................................................430
22.3.9 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................431
22.3.10 Set START Bit Register (DMA_SSRT)......................................................................................................432
22.3.11 Clear Error Register (DMA_CERR)............................................................................................................433
22.3.12 Clear Interrupt Request Register (DMA_CINT).........................................................................................434
22.3.13 Interrupt Request Register (DMA_INT)......................................................................................................435
22.3.14 Error Register (DMA_ERR)........................................................................................................................437
22.3.15 Hardware Request Status Register (DMA_HRS)........................................................................................440
22.3.16 Enable Asynchronous Request in Stop Register (DMA_EARS).................................................................443
22.3.17 Channel n Priority Register (DMA_DCHPRIn)..........................................................................................445
22.3.18 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................446
22.3.19 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................446
22.3.20 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................447
22.3.21 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO).................................448
22.3.22 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................449
22.3.23 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES).....................................................................................................450
22.3.24 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................451
22.3.25 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................452
22.3.26 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................452
22.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES)...........................................................................................................453
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22.3.28 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO)............................................................................................................454
22.3.29 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)..........455
22.3.30 TCD Control and Status (DMA_TCDn_CSR)............................................................................................456
22.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES)...........................................................................................................458
22.3.32 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO)............................................................................................................459
22.4 Functional description...................................................................................................................................................460
22.4.1 eDMA basic data flow.................................................................................................................................460
22.4.2 Fault reporting and handling........................................................................................................................463
22.4.3 Channel preemption.....................................................................................................................................465
22.4.4 Performance.................................................................................................................................................465
22.5 Initialization/application information...........................................................................................................................470
22.5.1 eDMA initialization.....................................................................................................................................470
22.5.2 Programming errors.....................................................................................................................................472
22.5.3 Arbitration mode considerations..................................................................................................................472
22.5.4 Performing DMA transfers..........................................................................................................................473
22.5.5 Monitoring transfer descriptor status...........................................................................................................477
22.5.6 Channel Linking...........................................................................................................................................479
22.5.7 Dynamic programming................................................................................................................................480
Chapter 23
External Watchdog Monitor (EWM)
23.1 Introduction...................................................................................................................................................................485
23.1.1 Features........................................................................................................................................................485
23.1.2 Modes of Operation.....................................................................................................................................486
23.1.3 Block Diagram.............................................................................................................................................487
23.2 EWM Signal Descriptions............................................................................................................................................488
23.3 Memory Map/Register Definition.................................................................................................................................488
23.3.1 Control Register (EWM_CTRL).................................................................................................................488
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Section number Title Page
23.3.2 Service Register (EWM_SERV)..................................................................................................................489
23.3.3 Compare Low Register (EWM_CMPL)......................................................................................................489
23.3.4 Compare High Register (EWM_CMPH).....................................................................................................490
23.3.5 Clock Prescaler Register (EWM_CLKPRESCALER)................................................................................491
23.4 Functional Description..................................................................................................................................................491
23.4.1 The EWM_out Signal..................................................................................................................................491
23.4.2 The EWM_in Signal....................................................................................................................................492
23.4.3 EWM Counter..............................................................................................................................................493
23.4.4 EWM Compare Registers............................................................................................................................493
23.4.5 EWM Refresh Mechanism...........................................................................................................................493
23.4.6 EWM Interrupt.............................................................................................................................................494
23.4.7 Counter clock prescaler................................................................................................................................494
Chapter 24
Watchdog Timer (WDOG)
24.1 Introduction...................................................................................................................................................................495
24.2 Features.........................................................................................................................................................................495
24.3 Functional overview......................................................................................................................................................497
24.3.1 Unlocking and updating the watchdog.........................................................................................................498
24.3.2 Watchdog configuration time (WCT)..........................................................................................................499
24.3.3 Refreshing the watchdog..............................................................................................................................500
24.3.4 Windowed mode of operation......................................................................................................................500
24.3.5 Watchdog disabled mode of operation.........................................................................................................500
24.3.6 Debug modes of operation...........................................................................................................................501
24.4 Testing the watchdog....................................................................................................................................................501
24.4.1 Quick test.....................................................................................................................................................502
24.4.2 Byte test........................................................................................................................................................502
24.5 Backup reset generator..................................................................................................................................................503
24.6 Generated resets and interrupts.....................................................................................................................................504
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24.7 Memory map and register definition.............................................................................................................................504
24.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)...........................................................505
24.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................507
24.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH).................................................................507
24.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)..................................................................508
24.7.5 Watchdog Window Register High (WDOG_WINH)..................................................................................508
24.7.6 Watchdog Window Register Low (WDOG_WINL)...................................................................................509
24.7.7 Watchdog Refresh register (WDOG_REFRESH).......................................................................................509
24.7.8 Watchdog Unlock register (WDOG_UNLOCK).........................................................................................509
24.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH).................................................................510
24.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL)..................................................................510
24.7.11 Watchdog Reset Count register (WDOG_RSTCNT)..................................................................................511
24.7.12 Watchdog Prescaler register (WDOG_PRESC)..........................................................................................511
24.8 Watchdog operation with 8-bit access..........................................................................................................................511
24.8.1 General guideline.........................................................................................................................................511
24.8.2 Refresh and unlock operations with 8-bit access.........................................................................................512
24.9 Restrictions on watchdog operation..............................................................................................................................513
Chapter 25
Multipurpose Clock Generator (MCG)
25.1 Introduction...................................................................................................................................................................515
25.1.1 Features........................................................................................................................................................515
25.1.2 Modes of Operation.....................................................................................................................................519
25.2 External Signal Description..........................................................................................................................................519
25.3 Memory Map/Register Definition.................................................................................................................................519
25.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................520
25.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................521
25.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................522
25.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................523
25.3.5 MCG Control 5 Register (MCG_C5)...........................................................................................................524
KV31F Sub-Family Reference Manual , Rev. 3, 7/2014
20 Freescale Semiconductor, Inc.