Freescale Semiconductor MC68332 User manual

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M68300 Family
MC68332
User’s Manual
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MC68332
USER’S MANUAL
Paragraph Title Page
SECTION 1 INTRODUCTION
SECTION 2NOMENCLATURE
2.1 Symbols and Operators .................................................................................. 2-1
2.2 CPU32 Registers ............................................................................................ 2-2
2.3 Pin and Signal Mnemonics ............................................................................. 2-3
2.4 Register Mnemonics ....................................................................................... 2-4
2.5 Conventions ................................................................................................... 2-5
SECTION 3OVERVIEW
3.1 MC68332 Features ......................................................................................... 3-1
3.1.1 System Integration Module (SIM) ........................................................... 3-1
3.1.2 Central Processing Unit (CPU) ............................................................... 3-1
3.1.3 Time Processor Unit (TPU) .................................................................... 3-1
3.1.4 Queued Serial Module (QSM) ................................................................ 3-2
3.1.5 Static RAM Module with TPU Emulation Capability (TPURAM) ............. 3-2
3.2 System Block Diagram and Pin Assignment Diagrams .................................. 3-2
3.3 Pin Descriptions ............................................................................................. 3-5
3.4 Signal Descriptions ......................................................................................... 3-7
3.5 Intermodule Bus ............................................................................................. 3-9
3.6 System Memory Map ..................................................................................... 3-9
3.6.1 Internal Register Map ........................................................................... 3-10
3.6.2 Address Space Maps ........................................................................... 3-10
3.7 System Reset ............................................................................................... 3-15
3.7.1 SIM Reset Mode Selection ................................................................... 3-15
3.7.2 MCU Module Pin Function During Reset ............................................. 3-16
SECTION 4 SYSTEM INTEGRATION MODULE
4.1 General ........................................................................................................... 4-1
4.2 System Configuration and Protection ............................................................. 4-2
4.2.1 Module Mapping ..................................................................................... 4-3
4.2.2 Interrupt Arbitration ................................................................................. 4-3
4.2.3 Show Internal Cycles .............................................................................. 4-4
4.2.4 Factory Test Mode ................................................................................. 4-4
4.2.5 Register Access ..................................................................................... 4-4
4.2.6 Reset Status ........................................................................................... 4-4
4.2.7 Bus Monitor ............................................................................................ 4-5
4.2.8 Halt Monitor ............................................................................................ 4-5
4.2.9 Spurious Interrupt Monitor ...................................................................... 4-5
TABLE OF CONTENTS
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TABLE OF CONTENTS
4.2.10 Software Watchdog ................................................................................ 4-5
4.2.11 Periodic Interrupt Timer .......................................................................... 4-7
4.2.12 Low-Power Stop Operation .................................................................... 4-8
4.2.13 Freeze Operation ................................................................................... 4-9
4.3 System Clock ................................................................................................. 4-9
4.3.1 Clock Sources ...................................................................................... 4-10
4.3.2 Clock Synthesizer Operation ................................................................ 4-10
4.3.3 External Bus Clock ............................................................................... 4-15
4.3.4 Low-Power Operation ........................................................................... 4-15
4.3.5 Loss of Reference Signal ..................................................................... 4-16
4.4 External Bus Interface .................................................................................. 4-17
4.4.1 Bus Signals .......................................................................................... 4-18
4.4.1.1 Address Bus ................................................................................. 4-18
4.4.1.2 Address Strobe ............................................................................ 4-18
4.4.1.3 Data Bus ...................................................................................... 4-18
4.4.1.4 Data Strobe .................................................................................. 4-18
4.4.1.5 Read/Write Signal ........................................................................ 4-18
4.4.1.6 Size Signals ................................................................................. 4-19
4.4.1.7 Function Codes ............................................................................ 4-19
4.4.1.8 Data and Size Acknowledge Signals ........................................... 4-19
4.4.1.9 Bus Error Signal ........................................................................... 4-20
4.4.1.10 Halt Signal .................................................................................... 4-20
4.4.1.11 Autovector Signal ......................................................................... 4-20
4.4.2 Dynamic Bus Sizing ............................................................................. 4-20
4.4.3 Operand Alignment .............................................................................. 4-21
4.4.4 Misaligned Operands ........................................................................... 4-22
4.4.5 Operand Transfer Cases ...................................................................... 4-22
4.5 Bus Operation .............................................................................................. 4-22
4.5.1 Synchronization to CLKOUT ................................................................ 4-23
4.5.2 Regular Bus Cycles .............................................................................. 4-23
4.5.2.1 Read Cycle ................................................................................... 4-24
4.5.2.2 Write Cycle ................................................................................... 4-25
4.5.3 Fast Termination Cycles ....................................................................... 4-26
4.5.4 CPU Space Cycles ............................................................................... 4-27
4.5.4.1 Breakpoint Acknowledge Cycle .................................................... 4-28
4.5.4.2 LPSTOP Broadcast Cycle ............................................................ 4-31
4.5.5 Bus Exception Control Cycles .............................................................. 4-31
4.5.5.1 Bus Errors .................................................................................... 4-33
4.5.5.2 Double Bus Faults ........................................................................ 4-33
4.5.5.3 Retry Operation ............................................................................ 4-34
4.5.5.4 Halt Operation .............................................................................. 4-34
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USER’S MANUAL
(Continued)
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TABLE OF CONTENTS
4.5.6 External Bus Arbitration ........................................................................ 4-35
4.5.6.1 Slave (Factory Test) Mode Arbitration ......................................... 4-36
4.5.6.2 Show Cycles ................................................................................ 4-36
4.6 Reset ............................................................................................................ 4-37
4.6.1 Reset Exception Processing ................................................................ 4-37
4.6.2 Reset Control Logic .............................................................................. 4-38
4.6.3 Reset Mode Selection .......................................................................... 4-38
4.6.3.1 Data Bus Mode Selection ............................................................. 4-39
4.6.3.2 Clock Mode Selection .................................................................. 4-41
4.6.3.3 Breakpoint Mode Selection .......................................................... 4-41
4.6.4 MCU Module Pin Function During Reset ............................................. 4-41
4.6.5 Pin State During Reset ......................................................................... 4-42
4.6.5.1 Reset States of SIM Pins ............................................................. 4-42
4.6.5.2 Reset States of Pins Assigned to Other MCU Modules ............... 4-43
4.6.6 Reset Timing ........................................................................................ 4-43
4.6.7 Power-On Reset ................................................................................... 4-44
4.6.8 Reset Processing Summary ................................................................. 4-45
4.6.9 Reset Status Register .......................................................................... 4-46
4.7 Interrupts ...................................................................................................... 4-46
4.7.1 Interrupt Exception Processing ............................................................ 4-46
4.7.2 Interrupt Priority and Recognition ......................................................... 4-46
4.7.3 Interrupt Acknowledge and Arbitration ................................................. 4-47
4.7.4 Interrupt Processing Summary ............................................................. 4-48
4.7.5 Interrupt Acknowledge Bus Cycles ....................................................... 4-49
4.8 Chip Selects ................................................................................................. 4-49
4.8.1 Chip-Select Registers ........................................................................... 4-51
4.8.1.1 Chip-Select Pin Assignment Registers ........................................ 4-52
4.8.1.2 Chip-Select Base Address Registers ........................................... 4-53
4.8.1.3 Chip-Select Option Registers ....................................................... 4-53
4.8.1.4 PORTC Data Register .................................................................. 4-55
4.8.2 Chip-Select Operation .......................................................................... 4-55
4.8.3 Using Chip-Select Signals for Interrupt Acknowledge .......................... 4-55
4.8.4 Chip-Select Reset Operation ................................................................ 4-56
4.9 Parallel Input/Output Ports ........................................................................... 4-58
4.9.1 Pin Assignment Registers .................................................................... 4-58
4.9.2 Data Direction Registers ...................................................................... 4-58
4.9.3 Data Registers ...................................................................................... 4-58
4.10 Factory Test ................................................................................................. 4-58
SECTION 5 CENTRAL PROCESSING UNIT
5.1 General ........................................................................................................... 5-1
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TABLE OF CONTENTS
5.2 CPU32 Registers ............................................................................................ 5-2
5.2.1 Data Registers ........................................................................................ 5-3
5.2.2 Address Registers .................................................................................. 5-5
5.2.3 Program Counter .................................................................................... 5-5
5.2.4 Control Registers .................................................................................... 5-5
5.2.4.1 Status Register ............................................................................... 5-5
5.2.4.2 Alternate Function Code Registers ................................................ 5-6
5.2.5 Vector Base Register (VBR) ................................................................... 5-6
5.3 Memory Organization ..................................................................................... 5-6
5.4 Virtual Memory ............................................................................................... 5-8
5.5 Addressing Modes .......................................................................................... 5-8
5.6 Processing States .......................................................................................... 5-8
5.7 Privilege Levels .............................................................................................. 5-9
5.8 Instructions ..................................................................................................... 5-9
5.8.1 M68000 Family Compatibility ............................................................... 5-12
5.8.2 Special Control Instructions .................................................................. 5-13
5.8.2.1 Low Power Stop (LPSTOP) ......................................................... 5-13
5.8.2.2 Table Lookup and Interpolate (TBL) ............................................ 5-13
5.9 Exception Processing ................................................................................... 5-13
5.9.1 Exception Vectors ................................................................................ 5-13
5.9.2 Types of Exceptions ............................................................................. 5-14
5.9.3 Exception Processing Sequence .......................................................... 5-15
5.10 Development Support ................................................................................... 5-15
5.10.1 M68000 Family Development Support ................................................. 5-15
5.10.2 Background Debugging Mode .............................................................. 5-16
5.10.2.1 Enabling BDM .............................................................................. 5-17
5.10.2.2 BDM Sources ............................................................................... 5-17
5.10.2.3 Entering BDM ............................................................................... 5-18
5.10.2.4 BDM Commands .......................................................................... 5-19
5.10.2.5 Background Mode Registers ........................................................ 5-20
5.10.2.6 Returning from BDM .................................................................... 5-20
5.10.2.7 Serial Interface ............................................................................. 5-20
5.10.3 Recommended BDM Connection ......................................................... 5-22
5.10.4 Deterministic Opcode Tracking ............................................................ 5-22
5.10.5 On-Chip Breakpoint Hardware ............................................................. 5-23
5.11 Loop Mode Instruction Execution ................................................................. 5-23
SECTION 6QUEUED SERIAL MODULE
6.1 General ........................................................................................................... 6-1
6.2 QSM Registers and Address Map .................................................................. 6-2
6.2.1 QSM Global Registers ........................................................................... 6-2
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TABLE OF CONTENTS
6.2.1.1 Low-Power Stop Operation ........................................................... 6-2
6.2.1.2 Freeze Operation .......................................................................... 6-3
6.2.1.3 QSM Interrupts .............................................................................. 6-3
6.2.2 QSM Pin Control Registers ................................................................... 6-3
6.3 Queued Serial Peripheral Interface ................................................................ 6-4
6.3.1 QSPI Registers ...................................................................................... 6-6
6.3.1.1 Control Registers ........................................................................... 6-7
6.3.1.2 Status Register .............................................................................. 6-7
6.3.2 QSPI RAM ............................................................................................. 6-7
6.3.2.1 Receive RAM ................................................................................. 6-7
6.3.2.2 Transmit RAM ................................................................................ 6-8
6.3.2.3 Command RAM ............................................................................. 6-8
6.3.3 QSPI Pins ............................................................................................... 6-8
6.3.4 QSPI Operation ...................................................................................... 6-9
6.3.5 QSPI Operating Modes ........................................................................ 6-10
6.3.5.1 Master Mode ................................................................................ 6-17
6.3.5.2 Master Wraparound Mode ........................................................... 6-20
6.3.5.3 Slave Mode .................................................................................. 6-20
6.3.5.4 Slave Wraparound Mode ............................................................. 6-22
6.3.6 Peripheral Chip Selects ........................................................................ 6-22
6.4 Serial Communication Interface ................................................................... 6-22
6.4.1 SCI Registers ....................................................................................... 6-22
6.4.1.1 Control Registers ......................................................................... 6-22
6.4.1.2 Status Register ............................................................................. 6-25
6.4.1.3 Data Register ............................................................................... 6-25
6.4.2 SCI Pins .............................................................................................. 6-25
6.4.3 SCI Operation ....................................................................................... 6-25
6.4.3.1 Definition of Terms ....................................................................... 6-25
6.4.3.2 Serial Formats .............................................................................. 6-26
6.4.3.3 Baud Clock ................................................................................... 6-26
6.4.3.4 Parity Checking ............................................................................ 6-27
6.4.3.5 Transmitter Operation .................................................................. 6-27
6.4.3.6 Receiver Operation ...................................................................... 6-28
6.4.3.7 Idle-Line Detection ....................................................................... 6-29
6.4.3.8 Receiver Wakeup ......................................................................... 6-30
6.4.3.9 Internal Loop ................................................................................ 6-30
6.5 QSM Initialization ......................................................................................... 6-31
SECTION 7TIME PROCESSOR UNIT
7.1 General ........................................................................................................... 7-1
7.2 TPU Components ........................................................................................... 7-2
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TABLE OF CONTENTS
7.2.1 Time Bases ............................................................................................ 7-2
7.2.2 Timer Channels ...................................................................................... 7-2
7.2.3 Scheduler ............................................................................................... 7-2
7.2.4 Microengine ............................................................................................ 7-2
7.2.5 Host Interface ......................................................................................... 7-2
7.2.6 Parameter RAM ...................................................................................... 7-3
7.3 TPU Operation ............................................................................................... 7-3
7.3.1 Event Timing .......................................................................................... 7-3
7.3.2 Channel Orthogonality ............................................................................ 7-4
7.3.3 Interchannel Communication .................................................................. 7-4
7.3.4 Programmable Channel Service Priority ................................................ 7-4
7.3.5 Coherency .............................................................................................. 7-4
7.3.6 Emulation Support .................................................................................. 7-4
7.3.7 TPU Interrupts ........................................................................................ 7-5
7.4 Standard and Enhanced Standard Time Functions ....................................... 7-6
7.4.1 Discrete Input/Output (DIO) .................................................................... 7-6
7.4.2 Input Capture/Input Transition Counter (ITC) ......................................... 7-6
7.4.3 Output Compare (OC) ............................................................................ 7-6
7.4.4 Pulse-Width Modulation (PWM) ............................................................. 7-7
7.4.5 Synchronized Pulse-Width Modulation (SPWM) .................................... 7-7
7.4.6 Period Measurement with Additional Transition Detect (PMA) .............. 7-7
7.4.7 Period Measurement with Missing Transition Detect (PMM) ................. 7-7
7.4.8 Position-Synchronized Pulse Generator (PSP) ...................................... 7-7
7.4.9 Stepper Motor (SM) ................................................................................ 7-8
7.4.10 Period/Pulse-Width Accumulator (PPWA) .............................................. 7-8
7.4.11 Quadrature Decode (QDEC) .................................................................. 7-9
7.5 Motion Control Time Functions ...................................................................... 7-9
7.5.1 Table Stepper Motor (TSM) .................................................................... 7-9
7.5.2 New Input Capture/Transition Counter (NITC) ....................................... 7-9
7.5.3 Queued Output Match (QOM) .............................................................. 7-10
7.5.4 Programmable Time Accumulator (PTA) ............................................. 7-10
7.5.5 Multichannel Pulse-Width Modulation (MCPWM) ................................ 7-10
7.5.6 Fast Quadrature Decode (FQD) ........................................................... 7-10
7.5.7 Universal Asynchronous Receiver/Transmitter (UART) ....................... 7-11
7.5.8 Brushless Motor Commutation (COMM) .............................................. 7-11
7.5.9 Frequency Measurement (FQM) .......................................................... 7-11
7.5.10 Hall Effect Decode (HALLD) ................................................................. 7-11
7.6 Host Interface Registers ............................................................................... 7-11
7.6.1 System Configuration Registers ........................................................... 7-12
7.6.1.1 Prescaler Control for TCR1 .......................................................... 7-12
7.6.1.2 Prescaler Control for TCR2 .......................................................... 7-12
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TABLE OF CONTENTS
7.6.1.3 Emulation Control ......................................................................... 7-13
7.6.1.4 Low-Power Stop Control .............................................................. 7-13
7.6.2 Channel Control Registers ................................................................... 7-14
7.6.2.1 Channel Interrupt Enable and Status Registers ........................... 7-14
7.6.2.2 Channel Function Select Registers .............................................. 7-14
7.6.2.3 Host Sequence Registers ............................................................ 7-14
7.6.2.4 Host Service Registers ................................................................. 7-14
7.6.2.5 Channel Priority Registers ........................................................... 7-14
7.6.3 Development Support and Test Registers ........................................... 7-15
SECTION 8STANDBY RAM WITH TPU EMULATION
8.1 General ........................................................................................................... 8-1
8.2 TPURAM Register Block ................................................................................ 8-1
8.3 TPURAM Array Address Mapping .................................................................. 8-1
8.4 TPURAM Privilege Level ................................................................................ 8-2
8.5 Normal Operation ........................................................................................... 8-2
8.6 Standby Operation ......................................................................................... 8-2
8.7 Low-Power Stop Operation ............................................................................ 8-3
8.8 Reset .............................................................................................................. 8-3
8.9 TPU Microcode Emulation .............................................................................. 8-3
APPENDIX A ELECTRICAL CHARACTERISTICS
APPENDIX B MECHANICAL DATA AND ORDERING INFORMATION
APPENDIX CDEVELOPMENT SUPPORT
C.1 M68MMDS1632 Modular Development System ........................................... C-1
C.2 M68MEVB1632 Modular Evaluation Board ................................................... C-2
APPENDIX D REGISTER SUMMARY
D.1 Central Processing Unit ................................................................................. D-1
D.1.1 CPU32 Register Model .......................................................................... D-2
D.1.2 SR — Status Register ........................................................................... D-3
D.2 System Integration Module ............................................................................ D-3
D.2.1 SIMCR — Module Configuration Register ............................. $YFFA00 D-5
D.2.2 SIMTR — System Integration Test Register .......................... $YFFA02 D-6
D.2.3 SYNCR — Clock Synthesizer Control Register .................... $YFFA04 D-6
D.2.4 RSR — Reset Status Register .............................................. $YFFA07 D-7
D.2.5 SIMTRE — System Integration Test Register (ECLK)........... $YFFA08 D-7
D.2.6 PORTE0/PORTE1 — Port E Data Register..........$YFFA11, $YFFA13 D-8
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