GOWIN GW1NSE Series User manual

GW1NSE series of SecureFPGA Products
Package & Pinout User Guide
UG874-1.0E, 06/28/2019

Copyright © 2019 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.
, LittleBee, and GOWIN are trademarks of Guangdong Gowin Semiconductor
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or otherwise, without the prior written consent of GOWINSEMI.
Disclaimer
GOWINSEMI assumes no liability and provides no warranty (either expressed or implied)
and is not responsible for any damage incurred to your hardware, software, data, or
property resulting from usage of the materials or intellectual property except as outlined in
the GOWINSEMI Terms and Conditions of Sale. GOWINSEMI may make changes to this
document at any time without prior notice. Anyone relying on this documentation should
contact GOWINSEMI for the current documentation and errata.

Revision History
Date
Version
Description
06/28/2019
1.0E
Initial version published.

Contents
UG874-1.0E
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Contents
Contents.................................................................................................................i
List of Figures.....................................................................................................ii
List of Tables......................................................................................................iii
1 About This Guide.............................................................................................1
1.1 Purpose ..............................................................................................................................1
1.2 Related Documents ............................................................................................................1
1.3 Terminology and Abbreviations...........................................................................................2
1.4 Support and Feedback .......................................................................................................2
2 Overview...........................................................................................................3
2.1 PB-Free Package ............................................................................................................... 3
2.2 Package and Max. User I/O Information ............................................................................ 3
2.3 Power Pin ...........................................................................................................................4
2.4 Pin Quantity ........................................................................................................................5
2.4.1 Quantity of GW1NSE-2C Pins......................................................................................... 5
2.5 Pin Definitions.....................................................................................................................5
2.6 I/O BANK Introduction ........................................................................................................8
3 View of Pin Distribution ................................................................................10
3.1 View of GW1NSE-2C Pins Distribution .............................................................................11
3.1.1 View of QN48 Pins Distribution ......................................................................................11
3.1.2 View of LQ144Pins Distribution .....................................................................................12
4 Package Diagrams.........................................................................................13
4.1 QN48 Package Outline (6mm x 6mm)..............................................................................13
4.2 LQ144 Package Outline (22mm x 22mm) ........................................................................14

List of Figures
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List of Figures
Figure 2-1 GW1NSE series of SecureFPGA Products I/O Bank Distribution.................................... 8
Figure 3-1 View of GW1NSE-2C QN48 Pins Distribution (Top View)................................................ 11
Figure 3-2 View of GW1NSE-2C LQ144 Pins Distribution (Top View) ..............................................12
Figure 4-1 Package Outline QN48..................................................................................................... 13
Figure 4-2 LQ144 Package Outline ...................................................................................................14

List of Tables
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List of Tables
Table 1-1 Abbreviation and Terminology............................................................................................ 2
Table 2-1 Package, Max. User I/O Information, and LVDS Paris ......................................................3
Table 2-2 GW1NSE Power Pins ........................................................................................................ 4
Table 2-3 Quantity of GW1NSE-2CPins .............................................................................................5
Table 2-4 Definition of the Pins in the GW1NSE series of FPGA products ....................................... 6
Table 3-1 Other pins in GW1NSE-2C QN48......................................................................................11
Table 3-2 Other pins in GW1NSE-2C LQ144 ....................................................................................12

1 About This Guide
1.1 Purpose
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1About This Guide
1.1 Purpose
This manual contains an introduction to the GW1NSE series of
SecureFPGA products together with a definition of the pins, list of pin
numbers, distribution of pins, and package diagrams.
1.2 Related Documents
The user guides are available on the GOWINSEMI Website. You can
find the related documents at www.gowinsemi.com:
1. DS871, GW1NSE series of SecureFPGA products Data Sheet
2. UG290, Gowin FPGA products Programming and Configuration User
Guide
3. UG874, GW1NSE series of SecureFPGA products Package and
Pinout
4. UG872, GW1NSE-2C Pinout

1 About This Guide
1.3 Terminology and Abbreviations
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1.3 Terminology and Abbreviations
The terminology and abbreviations used in this manual are as shown in
below Table 1-1 .
Table 1-1 Abbreviation and Terminology
Terminology and Abbreviations
Full Name
FPGA
Field Programmable Gate Array
GPIO
Gowin Programmable IO
QN48
QFN48
LQ144
LQFP144
1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly by the following ways.
Website: www.gowinsemi.com
E-mail:[email protected]

2 Overview
2.1 PB-Free Package
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2Overview
GOWIN SecureFPGA products provide a Root of Trust based on
SRAM PUF technology. Each device is factory provisioned with a unique
key pair that is never exposed outside of the device or to the internal
development space. The Intrinsic ID BroadKey-Pro security library is
provided with GOWIN SecureFPGA devices allowing easy integration of
common security features into user applications. The GOWIN
SecureFPGA feature set is widely applicable and can used for a variety of
consumer and industrial IoT, edge, and server management applications.
2.1 PB-Free Package
The GW1NSE series of SecureFPGA products are PB free in line with
the EU ROHS environmental directives. The substances used in the
GW1NSE series of SecureFPGA products are in full compliance with the
IPC-1752 standards.
2.2 Package and Max. User I/O Information
Table 2-1 Package, Max. User I/O Information, and LVDS Paris
Package
Pitch (mm)
Size (mm)
GW1NSE-2C
QN48
0.4
6 x 6
39(7)
LQ144
0.5
22 x 22
91(11)
Note!
In this manual, abbreviations are employed to refer to the package types. See
1.3Terminology and Abbreviations.
The JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The data in
this table is when the loaded four JTAG pins (TCK, TDI, TDO, and TMS) are used as
I/O; When mode [2:0] = 001, JTAGSEL_N and the four JTAG pins (TCK, TDI, TDO,
and TMS) can be used as GPIO simultaneously, and the Max. user I/O plus one.

2 Overview
2.3 Power Pin
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2.3 Power Pin
Table 2-2 GW1NSE Power Pins
VCC
VCCO0
VCCO1
VCCO2
VCCO3
VCCX
VSS
NC
VCCPLL
VCCP

2 Overview
2.4 Pin Quantity
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2.4 Pin Quantity
2.4.1 Quantity of GW1NSE-2C Pins
Table 2-3 Quantity of GW1NSE-2CPins
Pin Type
GW1NSE-2C
QN48
LQ144
I/O Single end / Differential
pair / LVDS1
BANK0
11/5/0
29/14/0
BANK1
9/4/2
16/8/3
BANK2
11/5/4
26/13/6
BANK3
8/3/1
20/9/2
Max. User I/O 2
39
91
Differential Pair
17
44
True LVDS output
7
11
VCCX
0
0
VCCO0
0
0
VCCO1
1
1
VCCO2
1
2
VCCO3
0
2
VDDDUSB
0
1
VBUSPAD
0
1
VCCO0
0
3
VCCO0/VCCO3
1
0
VCC/VCCPLL3
2
0
VCC/VCCPLL/VDDPL
0
3
VCCP/VCCX
2
0
VCCX/VDDAUSB
0
3
VSS
2
10
MODE0
0
0
MODE1
0
0
MODE2
0
0
JTAGSEL_N
1
1
NC
0
21
Note!
[1]Single end/ Differential I/O quantity include CLK pins, and download pins;
[2]The JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The data
in this table is when the loaded four JTAG pins (TCK, TDI, TDO, and TMS) are used
as I/O;
[3]Pin multiplexing.
2.5 Pin Definitions
The location of the pins in the GW1NSE series of SecureFPGA

2 Overview
2.5 Pin Definitions
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products varies according to the different packages.
Table 2-4 provides a detailed overview of user I/O, multi-function pins,
dedicated pins, and other pins.
Table 2-4 Definition of the Pins in the GW1NSE series of FPGA products
Pin Name
I/O
Description
Max. User I/O
IO[End][Row/Column
Number][A/B]
I/O
[End] indicates the pin location, including
L(left) R(right) B(bottom), and T(top)
[Row/Column Number] indicates the pin
Row/Column number.If [End] is T(top) or
B(bottom), the pin indicates the column
number of the corresponding CFU. If
[End] is L(left) or R(right), the pin
indicates the Row number of the
corresponding CFU.
[A/B] indicates differential signal pair
information.
Multi-Function Pins
IO[End][Row/Column Number][A/B]/MMM
/MMM represents one or more of the
other functions in addition to being
general purpose user I/O. These pins
can be used as user I/O when the
functions are not used.
RECONFIG_N
I, internal weak
pull-up
Start new GowinCONFIG mode when
low pulse
READY
I/O
When high level, the device can be
programmed and configured
When low level, the device cannot be
programmed and configured
DONE
I/O
High level indicates successful program
and configure
Low level indicates incomplete or failed
to program and configure
FASTRD_N /D3
I/O
In MSPI mode, FASTRD_N is used as
Flash access speed port. Low indicates
high-speed Flash access mode; high
indicates regular Flash access mode.
Data port D3 in CPU mode
MCLK /D4
I/O
Clock output MCLK in MSPI mode
Data port D4 in CPU mode
MCS_N /D5
I/O
Enable signal MCS_N in MSPI mode,
active-low
Data port D5 in CPU mode
MI /D7
I/O
MISO in MSPI mode: Master data
input/Slave data output
Data port D7 in CPU mode
MO /D6
I/O
MISO in MSPI mode: Master data
output/Slave data input
Data port D6 in CPU mode
SSPI_CS_N/D0
I/O
Enable signal SSPI_CS_N in SSPI mod,
active-low, Internal Weak Pull Up
Data port D0 in CPU mode
SO /D1
I/O
MISO in MSPI mode: Master data

2 Overview
2.5 Pin Definitions
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Pin Name
I/O
Description
input/Slave data output
Data port D1 in CPU mode
SI /D2
I/O
MISO in MSPI mode: Master data
output/Slave data input
Data port D2 in CPU mode
TMS
I, internal weak
pull-up
Serial mode input in JTAG mode
TCK
I
Serial clock input in JTAG mode, which
needs to be connected with 4.7 K
drop-down resistance on PCB
TDI
I, internal weak
pull-up
Serial data input in JTAG mode
TDO
O
Serial data output in JTAG mode
JTAGSEL_N
I, internal weak
pull-up
Select signal in JTAG mode, active-low
SCLK
I
Clock input in SSPI, SERIAL, and CPU
mode
DIN
I, internal weak
pull-up
Input data in SERIAL mode
DOUT
O
Output data in SERIAL mode
CLKHOLD_N
I, internal weak
pull-up
High level, SCLK will be connected
internally in SSPI mode or CPU mode
Low level, SCLK will be disconnected
from SSPI mode or CPU mode
WE_N
I
Select data input/output of D[7:0] in CPU
mode
GCLKT_[x]
I
Pins for global clock input, T(True), [x]:
global clock No.
GCLKC_[x]
I
Pins for Global clock input, C(Comp), [x]:
global clock No.
LPLL_T_fb/RPLL_T_fb
I
L/R PLL feedback input pin, T(True)
LPLL_C_fb/RPLL_C_f
b
I
L/R PLL feedback input pin, C(Comp)
LPLL_T_in/RPLL_T_in
I
L/R PLL clock input pin, T(True)
LPLL_C_in/RPLL_C_in
I
L/R PLL clock input pin, C(Comp)
CH[7:0]
I
Eight-channel analog input
MODE2
I, interna weak
pull-up
GowinCONFIG modes selection pin.
MODE1
I, internal weak
pull-up
GowinCONFIG modes selection pin.
MODE0
I, internal weak
pull-up
GowinCONFIG modes selection pin.
Other Pins
NC
NA
Reserved.
VSS
NA
Ground pins
VCC
NA
Power supply pins for internal core logic.
VCCO#
NA
Power supply pins for the I/O voltage of
I/O BANK#.
VCCX
NA
Power supply pins for auxiliary voltage.
VCCP
NA
FLASH Power supply pin (1.8V)

2 Overview
2.6 I/O BANK Introduction
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Pin Name
I/O
Description
VCCPLL
NA
Power supply pins in PLL
USB Power supply pin
DM
NA
USB data pin Data-
DP
NA
USB data pin Data+
REXT
NA
12.7K high-accuracy resistance
XIN
NA
Crystal input signals
XOUT
NA
Crystal oscillator signals
IDPAD
NA
ID signal
VBUSPAD
NA
VBUS signal
VDDA
NA
Analog power supply voltage,
VDDA=3.3V
VDDAUSB
NA
Analog power supply pin (3.3V)
VDDDUSB
NA
Analog power supply pin (3.3V)
VDDPL
NA
Power supply pin for driver (1.2V)
2.6 I/O BANK Introduction
There are four I/O Banks in the GW1NSE series of SecureFPGA
products. The I/O BANK Distribution of the GW1NSE series of
SecureFPGA products is as shown in Figure 2-1.
Figure 2-1 GW1NSE series of SecureFPGA Products I/O Bank Distribution
GW1NS
I/O BANK0
I/O BANK2
I/O BANK1 I/O BANK3
This manual provides an overview of the distribution view of the pins in
the GW1NSE series of SecureFPGA products. The eight I/O Banks that
form the GW1NSE series of SecureFPGA products are marked with eight
different colors.
Various symbols are used for the user I/O, power, and ground. The
various symbols and colors used for the various pins are defined as
follows:
" " denotes the I/O in BANK0. The filling color changes with the

2 Overview
2.6 I/O BANK Introduction
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BANK;
" " denotes the I/O in BANK1. The filling color changes with the
BANK;
" " denotes the I/O in BANK2. The filling color changes with the
BANK;
" " denotes the I/O in BANK3. The filling color changes with the
BANK;
" " denotes VCC, VCCX, and VCCO. The filling color does not
change;
" " denotes VSS, the filling color does not change;
" " denotes NC.

3 View of Pin Distribution
2.6 I/O BANK Introduction
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3View of Pin Distribution

3 View of Pin Distribution
3.1 View of GW1NSE-2C Pins Distribution
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3.1 View of GW1NSE-2C Pins Distribution
3.1.1 View of QN48 Pins Distribution
Figure 3-1 View of GW1NSE-2C QN48 Pins Distribution (Top View)
Table 3-1 Other pins in GW1NSE-2C QN48
VCCO1
25
VCCO2
13
VCCX/VCCP
8, 36
VCC/VCCPLL
12, 37
VCCO0/VCCO3
1
VSS
2, 26

3 View of Pin Distribution
3.1 View of GW1NSE-2C Pins Distribution
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3.1.2 View of LQ144Pins Distribution
Figure 3-2 View of GW1NSE-2C LQ144 Pins Distribution (Top View)
Table 3-2 Other pins in GW1NSE-2C LQ144
VCCO1
91
VCCO2
37, 55
VCCO3
5, 26
VCCO0
144, 109, 127
VCC/VDDPL/VCCPLL
36, 73, 108
VCCX/VDDAUSB
78, 31, 103
VBUSPAD
82
VDDDUSB
85
VSS
2, 17, 33, 35, 53, 74, 89, 105, 107, 125

4Package Diagrams
4.1QN48 Package Outline (6mm x 6mm)
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4Package Diagrams
4.1 QN48 Package Outline (6mm x 6mm)
Figure 4-1 Package Outline QN48

4 Package Diagrams
4.2 LQ144 Package Outline (22mm x 22mm)
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4.2 LQ144 Package Outline (22mm x 22mm)
Figure 4-2 LQ144 Package Outline