i-See IGEP SMARC iMX6 Application guide

Document: MAN-BASE0040-001
Revision: 1.1
Date: 29/06/2016
ISEE
Integration Software & Electronics Engineering.
c/ Marcos Redondo, 5 Valldoreix
E08197 - Sant Cugat del Vallès
SPAIN
[phone]
[email protected]om
https://www.isee.biz/
IGEP TM SMARC EXPANSION
HARDWARE REFERENCE
MANUAL

IGEPTM SMARC iMX6
Hardware Reference Manual
ISEE 2007 S.L. All rights reserved, IGEP is a registered trademark from ISEE 2007 S.L. The following is provided for informational purposes only.
NIF:ESB64377005 Document: MAN-BASE0040-001 / Revision: 1.1 / Date: 29/06/2016
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Table of contents
Table of contents 2
1USER INFORMATION 4
1.1 ABOUT THIS DOCUMENT 4
1.2 COPYRIGHT NOTICE 4
1.3 TRADEMARKS 4
1.4 STANDARDS 4
1.5 WARRANTY 4
1.6 TECHNICAL SUPPORT 5
2OVERVIEW 6
2.1 IGEPTM SMARC EXPANSION DESCRIPTION 6
2.2 IGEPTM SMARC EXPANSION FEATURES 7
2.3 The IGEPTM SMARCEXPANSION BLOCK DIAGRAM 8
3ON-BOARD INTERFACES 9
3.1 SUMMARY 9
3.2 ETHERNET 11
3.3 USB 3.0 OTG 12
3.4 USB 2.0 HOST 13
3.5 HDMI 14
3.6 BUTTON LED 15
3.7 POWER SUPPLY 15
3.8 RTC BATTERY 16
3.9 EXPANSION HEADERS 17
3.9.1 EXPANSION 28 PINS HEADER 17
3.9.2 TERMINAL 6 PINS PLUG 18
3.9.3 SERIAL HEADER EXPANSION 19
3.9.4 SERIAL DEBUG 3V3 INTERFACE HEADER 20
3.9.5 BOOT SELECT HEADER 21
3.10 CSI CONNECTOR 22
3.11 MICRO SD CONNECTOR 23
3.12 AUDIO 24
3.13 DVI 25

IGEPTM SMARC iMX6
Hardware Reference Manual
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3.14 mSATA CONNECTOR 26
3.15 GSM 27
4MECHANICAL SPECIFICATIONS 28
5ELECTRICAL CHARACTERISTICS 29
6LIST OF TABLES 30
7LIST OF FIGURES 30
8CHANGE HISTORY 31

IGEPTM SMARC iMX6
Hardware Reference Manual
ISEE 2007 S.L. All rights reserved, IGEP is a registered trademark from ISEE 2007 S.L. The following is provided for informational purposes only.
NIF:ESB64377005 Document: MAN-BASE0040-001 / Revision: 1.1 / Date: 29/06/2016
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1USER INFORMATION
1.1 ABOUT THIS DOCUMENT
This document provides information about products from ISEE 2007 SL and/or its subsidiaries. No warranty of
suitability, purpose, or fitness is implied. While every attempt has been made to ensure that the information
in this document is accurate, the information contained within is supplied “as-is” and is subject to change
without notice.
For the circuits, descriptions and tables indicated, ISEE 2007 SL assumes no responsibility as far as patents or
other rights of third parties are concerned.
1.2 COPYRIGHT NOTICE
This document is copyrighted, 2013-2016, by ISEE 2007 SL.
All rights are reserved. ISEE reserves the right to make improvements to the products described in this
manual at any time without notice. No part of this manual may be reproduced, copied, translated or
transmitted in any form or by any means without the prior written permission of the original manufacturer.
Information provided in this manual is intended to be accurate and reliable. However, the original
manufacturer assumes no responsibility for its use, nor for any infringements upon the rights of third parties,
which may result from its use.
1.3 TRADEMARKS
IGEPTM ® is trademark of ISEE. ISEE is trademark or registered trademark of ISEE 2007 SL.
Product names, logos, brands and other trademarks featured or referred to within this user’s guide, or the
ISEE website, are the property of their respective trademark holders. These trademark holders are not
affiliated with ISEE, our products or our website.
1.4 STANDARDS
ISEE 2007 S.L. is going to be certified to ISO 9001:2015
1.5 WARRANTY
THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN
LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user
indemnifies ISEE 2007 SL from all claims arising from the handling or use of the goods. Due to the open
construction of the product, it is the user’s responsibility to take any and all appropriate precautions with
regard to electrostatic discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE
TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
ISEE 2007 SL currently deals with a variety of customers for products, and therefore our arrangement with the
user is not exclusive. ISEE assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein.

IGEPTM SMARC iMX6
Hardware Reference Manual
ISEE 2007 S.L. All rights reserved, IGEP is a registered trademark from ISEE 2007 S.L. The following is provided for informational purposes only.
NIF:ESB64377005 Document: MAN-BASE0040-001 / Revision: 1.1 / Date: 29/06/2016
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Please read specifically, the Warnings and Restrictions notice in this manual prior to handling the product.
This notice contains important safety information about temperatures and voltages. For additional
information on IGEPTM environmental and/or safety programs, please contact with ISEE
([e-mail]).
No license is granted under any patent right or other intellectual property right of ISEE covering or relating to
any machine, process, or combination in which such ISEE products or services might be or are used.
NOTE: It could be found a detailed warranty and sales conditions of IGEPTM on ISEE website: https://www.isee.biz
1.6 TECHNICAL SUPPORT
Technicians and engineers from ISEE 2007 SL and/or its subsidiaries are available for technical support. We
are committed to make our product easy to use and will help you use our products in your systems.
Please consult our Website at https://www.isee.biz for the latest product documentations: hardware
resources (schematics, mechanical drawings, layouts, etc.) and software resources (firmware binaries and
sources). You can also contact directly with our Technical Department and we will assist you with any queries
or problems you may have ([e-mail]).

IGEPTM SMARC iMX6
Hardware Reference Manual
ISEE 2007 S.L. All rights reserved, IGEP is a registered trademark from ISEE 2007 S.L. The following is provided for informational purposes only.
NIF:ESB64377005 Document: MAN-BASE0040-001 / Revision: 1.1 / Date: 29/06/2016
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2OVERVIEW
2.1 IGEPTM SMARC EXPANSION DESCRIPTION
The IGEP™ SMARC EXPANSION is a fully tested, highly reliable, scalable, efficient and high performing base
board that allows customers to have access to IGEP™ SMARC family boards functionalities and focus on their
end application through this base board. It’s designed for industrial and commercial purposes and can also be
used to develop and test your application over IGEP™ SMARC family processors boards before building a
prototype, saving cost and time-to-market.
Highlights:
Open source hardware and software to helps develop your custom embedded solutions.
1x Ethernet.
1x USB 3.0 OTG.
3x USB 2.0 HOST.
1x HDMI output.
1x Button LED.
1x RTC battery.
1x Expansion 28 pins header.
1x Terminal 6 pins plug.
1x Serial header expansion.
1x Serial debug 3V3 interface header.
1x Boot select header.
1x CSI connector.
1x Micro SD connector.
1x Line-in audio mini jack.
1x Headphones audio mini jack.
1x Mic-in audio mini jack.
1x DVI-D.
1x mSATA connector.
1x USB modem miniPCIe connector.
1x SIM connector.

IGEPTM SMARC iMX6
Hardware Reference Manual
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2.2 IGEPTM SMARC EXPANSION FEATURES
Feature
Specifications
Ethernet
10/100/1000 Mbps base T 1x RJ45 connector
USB 3.0 OTG
1x USB 3.0 type micro AB receptacle
USB 2.0 HOST
3x USB 2.0 type A receptacle
HDMI output
1x HDMI type A receptacle
Button LED
1x Button with blue and red LEDs integrated
RTC battery
Allow to maintain running the Real Time Clock
Expansion 28 pins header
Multiple peripherals: 2x SPI, 1x I2C, 1x I2S, 1x CAN, 2x PWM, RESET…
1x Male header 2x14 pins 2,54mm pitch spacing
Terminal 6 pins plug
Power (5V), RS485 and CAN interfaces are accessible
1x Male header 1x6 pins 5 mm pitch spacing
Serial header expansion
2x RS232 ports
1x Male header 2x5 pins 2,54 mm pitch spacing
Serial debug 3V3 interface header
Serial TTL 3V3 debug port
1x Male header 1x6 pins 2,54 mm pitch spacing
Boot select header
Header to select the boot interface
1x Male header 2x3 pins 2,54 mm pitch spacing
CSI connector
Used to connect cameras with MIPI CSI2 interface
Micro SD connector
Used to insert SD cards
Line-in audio mini jack
1x Stereo audio in
Headphones audio mini jack
1x Stereo audio out
Mic-in audio mini jack
1x Mic-in
DVI-D
DVI-D Interface on HDMI type A receptacle
mSATA connector
Used to connect mSATA disks
USB modem miniPCIe connector
Used to connect miniPCIe modems through USB interface
SIM connector
Used to insert SIM cards
Processor Board Interface
1x SMARC 314 expansion interface
Table 1 Main features

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Feature
Specifications
Power
Supply Voltage +5V DC +-10%
Power from terminal 6 pins plug
Supply Voltage +5V DC +-10%
Table 2 Power
2.3 The IGEPTM SMARCEXPANSION BLOCK DIAGRAM
Figure 1 IGEPTM SMARC EXPANSION block diagram
Figure 2 IGEPTM SMARC EXPANSION kit view (IGEP0046RCxx+BASE0040RBxx)

IGEPTM SMARC iMX6
Hardware Reference Manual
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3ON-BOARD INTERFACES
3.1 SUMMARY
Feature
IGEPTM SMARC
EXPANSION
IGEPTM SMARC BOARDS interface
Ethernet
J400
GBE
USB 3.0 OTG
J602
USB0 (OTG) and AFB_DIFF0, AFB_DIFF1 (USB3.0)
USB 2.0 HOST
J600(Type A dual)
and J601 (Type A)
USB1 (USB hub)
HDMI output
J500 (Type A)
HDMI
Button LED
S1200
GPIO9 (button), GPIO10 (blue LED) and GPIO11 (red LED).
RTC battery
BT300
VDD_RTC
Expansion 28 pins header
J1003
SPI0, I2S1, SPI1, AFB1_OUT (PWM), LCD_BKLT_PWM,
WDT_TIME_OUT#, SLEEP#, I2C_PM, AUDIO_MCK and
RESET_IN#
Terminal 6 pins plug
J1002
CAN, SER2 and 5V
Serial header expansion
J800
SER0 and SER3 (RS232)
Serial debug 3V3 interface
header
J801
SER1
Boot select header
J1202
BOOT_SEL0#, BOOT_SEL1# and BOOT_SEL2#
CSI connector
J1001
CSI1, GPIO7, GPIO8, I2C_CAM and CAM_MCK
Micro SD connector
J1200
SDIO
Line-in audio mini jack
J904
I2S0, I2C_GP, AUDIO_MCK and GPIO4 (reset) (audio codec)
Headphones audio mini jack
J900
I2S0, I2C_GP, AUDIO_MCK and GPIO4 (reset) (audio codec)
Mic-in audio mini jack
J902
I2S0, I2C_GP, AUDIO_MCK and GPIO4 (reset) (audio codec)
DVI-D
J501
LVDS (converted to DVI lines)
mSATA connector
J1103
SATA
modem miniPCIe connector
J1100
USB1 (USB hub)
SIM connector
J1102
-
Processor Board Interface
J200
Table 3 Interface summary

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Figure 3 IGEPTM SMARC EXPANSION interface connectors map top view
Figure 4 IGEPTM SMARC EXPANSION interface connectors map bot view

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Hardware Reference Manual
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3.2 ETHERNET
IGEPTM SMARC EXPANSION includes a RJ45 connector (J400), provided for Ethernet Auto-MDIX Full Duplex
10/100/1000 Base T interface. This port is supported by Ethernet Physical Layer Transceiver (PHY) included
into IGEPTM SMARC family processor board. The base board only makes a direct link with the Ethernet port.
The Ethernet interface supports the following features:
Fully compliant with IEEEE 802.3/802.3u standards.
10BASE-T, 100BASE-T and 1000BASE-T support.
Full-and Half-duplex support and full-duplex flow control.
Industrial temperature range (-40ºC to 85ºC).
Figure 5 J400 ethernet connector schematic
The ethernet signals are available through next connector pins:
Signal Name
SMARC pin
Description
GBE_MDI3-
P19
Analog Transmit/Receive Data 3 Negative. Differential output to magnetics.
GBE_MDI3+
P20
Analog Transmit/Receive Data 3 Positive. Differential output to magnetics.
GBE_LINK100#
P21
Active Low. Means 1000/100 Mbps speed. Inactive if 10 Mbps.
GBE_MDI2-
P23
Analog Transmit/Receive Data 2 Negative. Differential output to magnetics.
GBE_MDI2+
P24
Analog Transmit/Receive Data 2 Positive. Differential output to magnetics.
GBE_LINK_ACT#
P25
Active Low. Indicates valid link and blinks when there is activity.
GBE_MDI1-
P26
Analog Transmit/Receive Data 1 Negative. Differential output to magnetics.
GBE_MDI1+
P27
Analog Transmit/Receive Data 1 Positive. Differential output to magnetics.
GBE_CTREF
P28
Center-Tap reference voltage for Ethernet magnetic (if required by PHY).
GBE_MDI0-
P29
Analog Transmit/Receive Data 0 Negative. Differential output to magnetics.
GBE_MDI0+
P30
Analog Transmit/Receive Data 0 Positive. Differential output to magnetics.
Table 4 Ethernet signals in J400 RJ45 connector

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3.3 USB 3.0 OTG
IGEPTM SMARC EXPANSION includes a single USB 3.0 OTG port (J602) directly connected to the USB OTG
pins of the IGEPTM SMARC family interface.
J602 is an USB 3.0 type mini AB receptacle connector, next figure shows the connection to this port:
Figure 6 J602 USB 3.0 OTG connector schematic
The USB 3.0 OTG interface is implemented with the IGEPTM SMARC family USB OTG controller:
Operates either as the function controller of a Super/High/Full Speed USB peripheral or as host in
point-to-point or multipoint communications.
Complies with the USB 3.0 standard for SuperSpeed (5 Gbps) function and with on-the-go (OTG)
supplement.
Supports USB 3.0 peripheral at SuperSpeed (5 Gbps), High Speed (480 Mbps) and Full Speed (12
Mbps).
Supports USB 3.0 host at SuperSpeed (5 Gbps), High Speed (480 Mbps), Full Speed (12 Mbps) and
Low Speed (1,5 Mbps).
The USB 3.0 OTG signals are available through next connector pins:
Signal Name
SMARC
pin
Description
USB0+
P60
Analog D+ data pin of the USB0
USB0-
P61
Analog D- data pin of the USB0
USB0_VBUS_DET
P63
USB host power detection, when this port is used as a device
USB0_OTG_ID
P64
USB OTG ID input, active high
AFB_DIFF0+ (USB_TX_P)
S62
USB 3.0 transmission line +
AFB_DIFF0- (USB_TX_N)
S63
USB 3.0 transmission line -
AFB_DIFF1+ (USB_RX_P)
S65
USB 3.0 reception line +
AFB_DIFF1- (USB_RX_N)
S66
USB 3.0 reception line -
Table 5 USB 3.0 OTG signals in J602 connector

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3.4 USB 2.0 HOST
IGEPTM SMARC EXPANSION includes an USB 2.0 Hi-Speed hub controller providing 3x USB 2.0 HS HOST
ports available through Type A connectors, J600 and J601 (double and simple respectively). Hardware
provides power on/off switch control and up to 500 mA of current limit at 5V on each of 3 ports. The fourth
port of the hub is used for Modem miniPCIe connector.
Next figure shows the connection to these ports:
Figure 7 J600 and J601 USB 2.0 HOST connector schematic
The USB 2.0 HOST signals are available through next connector pins:
Signal Name
SMARC pin
Description
USB1+
P65
Analog D+ data pin of the USB1
USB1-
P66
Analog D- data pin of the USB1
USB1_EN_OC#
P67
Active Low. Over current Indication to module
GPIO0
P108
GPIO used to reset HUB controlller
GPIO1
P109
GPIO used to enable or disable 5VUSB1
GPIO2
P110
GPIO used to enable or disable 5VUSB2
GPIO3
P111
GPIO used to enable or disable 5VUSB3
Table 6 USB 2.0 HOST signals in J600 and J601 connector

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3.5 HDMI
IGEPTM SMARC EXPANSION includes an HDMI type A receptacle connector (J500).
Next figure shows its connection:
Figure 8 J500 connector schematic
The HDMI signals are available through next connector pins:
Signal Name
SMARC pin
Description
HDMI_D2+
P92
HDMI data differential pair D2 +
HDMI_D2-
P93
HDMI data differential pair D2 -
HDMI_D1+
P95
HDMI data differential pair D1 +
HDMI_D1-
P96
HDMI data differential pair D1 -
HDMI_D0+
P98
HDMI data differential pair D0 +
HDMI_D0-
P99
HDMI data differential pair D0 -
HDMI_CK+
P101
HDMI differential clock output pair +
HDMI_CK-
P102
HDMI differential clock output pair -
HDMI_HPD
P104
HDMI Hot Plug Detect input
HDMI_CTRL_CK
P105
I2C bus clock
HDMI_CTRL_DAT
P106
I2C bus data
HDMI_CEC
P107
HDMI Consumer Electronics Control
Table 7 HDMI signals in J500 connector

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3.6 BUTTON LED
IGEPTM SMARC EXPANSION includes a button with red and blue LEDs integrated (s1200), next figure shows
its connection:
Figure 9 S1200 button schematic
The BUTTON LED signals are available through next connector pins:
Signal Name
SMARC pin
Description
GPIO9
P117
GPIO used to read S1200 input (USER_BUTTON)
GPIO10
P118
GPIO used to control S1200 blue LED (USER_LED_BLUE)
GPIO11
P119
GPIO used to control S1200 red LED (USER_LED_RED)
Table 8 BUTTON LED signals
3.7 POWER SUPPLY
IGEPTM SMARC EXPANSION must be powered by +5Vdc power source and 5Adc current capacity should be
enough to use all board functionalities through J300 or through J1002
Next figure shows J300 and J1002 connections to power the board:
Figure 10 J300 and J1002 schematics

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3.8 RTC BATTERY
IGEPTM SMARC EXPANSION includes a backup battery (BT300) that powers the backup state as far as the
input voltage is high enough. It is used VL1220-1VC battery.
Next figure shows BT300 connection:
Figure 11 BT300 schematics
The BUTTON LED signals are available through next connector pin:
Signal Name
SMARC pin
Description
VDD_RTC
S147
Low current RTC circuit backup power.
Table 9 RTC BATTERY signals

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3.9 EXPANSION HEADERS
3.9.1 EXPANSION 28 PINS HEADER
IGEPTM SMARC EXPANSION includes an expansion header (J1003) that contains a lot of features as it is shown
in next figure:
Figure 12 J1003 schematic
EXPANSION 28 PINS HEADER signals are available through next connection pins:
Signal Name
SMARC pin
Description
SPI0_CS1#
P31
SPI0 chip select 1 signal (connected to pin 12)
SPI0_CS0#
P43
SPI0 chip select 0 signal (connected to pin 10)
SPI0_CK
P44
SPI0 clock (connected to pin 8)
SPI0_DIN
P45
SPI0 Master Input-Slave Output(MISO) (connected to pin 6)
SPI0_DO
P46
SPI0 Master Output –Slave Input (MOSI) (connected to pin 4)
SPI1_CS1#
P54
SPI1 chip select 1 signal (connected to pin 11)
SPI1_CS0#
P55
SPI1 chip select 0 signal (connected to pin 9)
SPI1_CK
P56
SPI1 clock (connected to pin 7)
SPI1_DIN
P57
SPI1 Master Input-Slave Output(MISO) (connected to pin 5)
SPI1_DO
P58
SPI1 Master Output –Slave Input (MOSI) (connected to pin 3)
I2C_PM_CK
P121
I2C bus clock (connected to pin 26)
I2C_PM_DAT
P122
I2C bus data (connected to pin 23)
RESET_IN#
P127
Reset input from Carrier board (connected to pin 25)
CAN1_TX
P145
CAN1 Transmission line (connected to pin 13)
CAN1_RX
P146
CAN1 Reception line (connected to pin 15)

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AFB1_OUT
S18
PWM output (connected to pin 24)
AUDIO_MCK
S38
Master clock output to Audio codecs (connected to pin 22)
I2S1_LRCK
S43
I2S1 Transmit Frame Sync signal (connected to pin 18)
I2S1_SDOUT
S44
I2S1 Data Transmit signal (connected to pin 20)
I2S1_SDIN
S45
I2S1 Data Receive signal (connected to pin 14)
I2S1_CK
S46
I2S1 Transmit Clock signal (connected to pin 16)
LCD_BKLT_PWM
S141
Display backlight (connected to pin 19)
WDT_TIME_OUT#
S145
Watch-Dog-Timer Output (connected to pin 17)
SLEEP#
S149
Sleep indicator from Carrier board (connected to pin 21)
Table 10 EXPANSION 28 PINS HEADER signals
3.9.2 TERMINAL 6 PINS PLUG
IGEPTM SMARC EXPANSION includes a terminal plug (J1002) that contains power, CAN and RS485 interfaces.
It is important to say that CAN signals are CAN bus standard compatible.
Next figure shows J1002 connections:
Figure 13 J1002 schematic
TERMINAL 6 PINS PLUG signals are available through next connection pins with RS485 and CAN transceivers:
Signal Name
SMARC pin
Description
SER2_TX
P136
SER2 Transmit Data Output
SER2_RX
P137
SER2 Receive Data Input
SER2_RTS#
P138
SER2 RTSn Output
SER2_CTS#
P139
SER2 CTSn Input
CAN0_TX
P143
CAN0 Transmission Line
CAN0_RX
P144
CAN0 Reception Line
Table 11 TERMINAL 6 PINS PLUG signals

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3.9.3 SERIAL HEADER EXPANSION
IGEPTM SMARC EXPANSION includes a serial header expansion (J800) which is a 5x2 pins double row 2,54 mm
male header.
The 5x2 Header follow the IDC-10 (AT-Everex) configuration. So, it is needed null modem configuration
(connection between two computers). RX and TX lines are crossed in this null modem configuration between
two equipment (TX1->RX2 / TX2->RX1).
Next figure shows SERIAL HEADER EXPANSION connections:
Figure 14 J800 schematic
Figure 15 IDC-10 to DB9 cable

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SERIAL HEADER EXPANSION signals are available through next connection pins with RS232 transceiver:
Signal Name
SMARC pin
Description
SER0_TX
P129
SER0 Transmit Data Output (RS232_TX2)
SER0_RX
P130
SER0 Receive Data Input (RS232_RX2)
SER3_TX
P140
SER3 Transmit Data Output (RS232_TX1)
SER3_RX
P141
SER3 Receive Data Input (RS232_RX1)
Table 12 SERIAL HEADER EXPANSION signals
3.9.4 SERIAL DEBUG 3V3 INTERFACE HEADER
IGEPTM SMARC EXPANSION includes a serial debug header (J801) connected through TXS0102 voltage translator to
protect IGEPTM SMARC family boards of latch up currents. J801 has 7 pins with 2.54 mm pitch spacing. This connector
lets you debug system using USB to 3V3 TTL level serial like TTL-232R-3V3 converter from FTDI
(http://www.ftdichip.com/Products/Cables/USBTTLSerial.htm) or compatible reference. The TTL-232R-3V3 converter
has 6 pins and IGEPTM SMARC EXPANSION adds a 7th way (3v3 power).
Next figure shows SERIAL DEBUG 3V3 INTERFACE HEADER connections:
Figure 16 J801 schematic
SERIAL DEBUG 3V3 INTERFACE HEADER signals are available through next connection pins:
Signal Name
SMARC pin
Description
SER1_TX
P134
SER1 Transmit Data Output (DEBUG_TX)
SER1_RX
P135
SER1 Receive Data Input (DEBUG_RX)
Table 13 SERIAL DEBUG 3V3 INTERFACE HEADER signals