Icom IC-756PRO III User manual

HF/50MHz ALL BAND TRANSCEIVER
i756PRO
SERVICE
MANUAL

VERSION
U.S.A.
Europe
France
SYMBOL
USA
EUR
FRA
INTRODUCTION
This service manual describes the latest service information
for the IC-756PRO HF/50MHz ALL BAND TRANSCEIVER.
DANGER
NEVER connect the transceiver to an AC outlet or to a DC
power supply that uses more than 16 V. This will ruin the
transceiver.
DO NOT expose the transceiver to rain, snow or any liquids.
DO NOT reverse the polarities of the power supply when
conecting the transceiver.
DO NOT apply an RF signal of more than 20 dBm (100 mW)
to the antenna connector. This could damage the
transceIer’s front end.
ORDERING PARTS
Be sure to include the following four points when ordering
replacement parts:
1. 10-digit order numbers
2. Component part number and name
3. Equipment model name and unit name
4. Quantity required
<SAMPLE ORDER>
1110000960 S.IC NJM4558M IC-756PRO MAIN UNIT 5 pieces
8810005770 Screw BiH M3×8 ZK IC-756PRO Top cover 10 pieces
Addresses are provided on the inside back cover for your
convenience.
REPAIR NOTES
1. Make sure a problem is internal before disassembling the
transceiver.
2. DO NOT open the transceiver until the transceiver is
disconnected from its power source.
3. DO NOT force any of the variable components. Turn
them slowly and smoothly.
4. DO NOT short any circuits or electronic parts. An insu-
lated tuning tool MUST be used for all adjustments.
5. DO NOT keep power ON for a long time when the trans-
ceiver is defective.
6. DO NOT transmit power into a signal generator or a
sweep generator.
7. ALWAYS connect a 50 dB to 60 dB attenuator between
the transceiver and a deviation meter or spectrum ana-
lyzer when using such test equipment.
8. READ the instructions of test equipment thoroughly
before connecting equipment to the transceiver.
MODEL
IC-756PRO
To upgrade quality, any electrical or mechanical parts and
internal circuits are subject to change without notice or
obligation.

TABLE OF CONTENTS
SECTION 1 SPECIFICATIONS
SECTION 2 INSIDE VIEWS
SECTION 3 CIRCUIT DESCRIPTION
3 - 1 RECEIVER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 1
3 - 2 TRANSMITTER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 - 4
3 - 3 PLL CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 6
3 - 4 ANTENNA TUNER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 7
3 - 5 SCOPE CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 8
3 - 6 POWER SUPPLY CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 9
3 - 7 LOGIC CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 10
SECTION 4 ADJUSTMENT PROCEDURES
4 - 1 PREPARATION BEFORE SERVICING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 1
4 - 2 PLL ADJUSTMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 2
4 - 3 RECEIVER ADJUSTMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 4
4 - 4 TRANSMITTER ADJUSTMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 8
4 - 5 TUNER ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 10
SECTION 5 PARTS LIST
SECTION 6 MECHANICAL PARTS
SECTION 7 SEMI-CONDUCTOR INFORMATION
SECTION 8 BOARD LAYOUTS
8 - 1 PBT, RIT AND MIC BOARDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 1
8 - 2 DISPLAY BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 2
8 - 3 MODE, PHONE, KEY AND TEN-KEY BOARDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 4
8 - 4 RF UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 6
8 - 5 PLL UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 8
8 - 6 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 10
8 - 7 DSP BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 12
8 - 8 MEMORY BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 13
8 - 9 PA UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 14
8 - 10 FILTER UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 15
8 - 11 TUNER BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 16
8 - 12 CTRL UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 17
SECTION 9 BLOCK DIAGRAM
SECTION 10 VOLTAGE DIAGRAM
10 - 1 FRONT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 1
10 - 2 DSP BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 2
10 - 3 TUNER, MEMORY BOARDS AND CTRL UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 3
10 - 4 MAIN UNIT (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 4
10 - 5 MAIN UNIT (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 5
10 - 6 PLL UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 6
10 - 7 PAAND FILTER UNITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 7
10 - 8 RF UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 8

SECTION 1 SPECIFICATIONS
1 - 1
■GENERAL
• Frequency coverage:
Receive 0.030–60.000 MHz*1, *2
Transmit 1.800–1.999 MHz*23.500–3.999 MHz*2
7.000–7.300 MHz*210.100–10.150 MHz*2
14.000–14.350 MHz*218.068–18.168 MHz*2
21.000–21.450 MHz*224.890–24.990 MHz*2
28.000–29.700 MHz*250.000–54.000 MHz*2
*1Some frequency bands are not guaranteed.
*2Depending on version.
• Mode : USB, LSB, CW, RTTY, AM, FM
• Number of memory channels
: 101 (99 regular, 2 scan edges)
• Antenna connector : SO-239 ✕2 and phono [(RCA); 50 Ω]
• Usable temp. range: –10˚C to +50˚C (14˚F to 122˚F)
• Frequency stability : Less than ±0.5 ppm from 1 min. after
power ON.
• Freq. resolution : 1 Hz
• Power supply : 13.8 V DC ±15 % (negative ground)
requirement
• Current consumption:
Transmit max. power 23 A
Receive stand-by 3.0 A (typical)
max. audio 3.3 A (typical)
• Dimensions : 340 (W) ✕111(H) ✕285(D) mm
133⁄8(W) ✕43⁄8(H) ✕117⁄32(D) in
• Weight : 9.6 kg (21 lb 1 oz)
• ACC 1 connector : 8-pin DIN connector
• ACC 2 connector : 7-pin DIN connector
• CI-V connector : 2-conductor 3.5(d) mm (1⁄8")
• Display : 5-inch (diagonal) TFT color LCD
■TRANSMITTER
• Output power :
SSB/CW/RTTY/FM 5–100 W
AM 5–40 W
• Modulation system :
SSB PSN modulation
AM Low power modulation
FM Phase modulation
• Spurious emission : Less than –50 dB (HF bands)
Less than –60 dB (50 MHz band)
• Carrier suppression: More than 40 dB
• Unwanted sideband suppression: More than 55 dB
• ∆TX variable range : ±9.999 kHz
• Mic. connector : 8-pin connector (600 Ω)
• ELE-KEY connector: 3-conductor 6.35(d) mm (1⁄4")
• KEY connector : 3-conductor 6.35(d) mm (1⁄4")
• SEND connector : Phono (RCA)
• ALC connector : Phono (RCA)
■RECEIVER
• Receive system : Triple-conversion superheterodyne
• Intermediate frequencies:
1st IF frequency 64.455 MHz
2nd IF frequency 455 kHz
3rd IF frequency 36 kHz
• Sensitivity :
SSB, CW, RTTY (at 2.4 kHz bandwidth)
1.8–29.99 MHz*10.16 µV (10 dB S/N)
50.0–54.0 MHz*20.13 µV (10 dB S/N)
AM (at 6.0 kHz bandwidth)
0.5–1.799 MHz 13 µV (10 dB S/N)
1.8–29.99 MHz*12.0 µV (10 dB S/N)
50.0–54.0 MHz*21.0 µV (10 dB S/N)
FM (at 15 kHz bandwidth)
28.0–29.99 MHz*10.5 µV (12 dB SINAD)
50.0–54.0 MHz*20.32 µV (12 dB SINAD)
*1Pre-amp 1 ON *2Pre-amp 2 ON
• Squelch sensitivity : (Pre-amp OFF)
SSB/CW/RTTY Less than 5.6 µV
FM Less than 1.0 µV
• Selectivity :
SSB/RTTY (at 2.4 kHz bandwidth)
More than 2.4 kHz/–6 dB
Less than 2.8 kHz/–60 dB
CW (at 500 Hz bandwidth)
More than 500 Hz/–6 dB
Less than 700 Hz/–60 dB
AM (at 6 kHz bandwidth)
More than 6.0 kHz/–6 dB
Less than 15.0 kHz/–60 dB
FM (at 15 kHz bandwidth)
More than 12 kHz/–6 dB
Less than 20 kHz/–60 dB
• Spurious and image: More than 70 dB
rejection ratio (except IF through in 50 MHz band)
• RIT variable range : ±9.999 kHz
• Audio output power: More than 2.0 W at 10 % distortion
(at 13.8 V DC) with an 8 Ωload
• PHONES connector: 3-conductor 6.35 (d) mm (1⁄4")
• EXT SP connector : 2-conductor 3.5 (d) mm (1⁄8") 8 Ω
■ANTENNA TUNER
• Matching impedance range:
HF bands 16.7 to 150 Ωunbalanced*1
50 MHz band 20 to 125 Ωunbalanced*2
*1Less than VSWR 3:1; *2Less than VSWR 2.5:1
• Minimum operating input power:
HF bands : 8 W
50 MHz band : 15 W
• Tuning accuracy : VSWR 1.5:1 or less
• Insertion loss : Less than 1.0 dB
(after tuning)
All stated specifications are subject to change without notice or obligation.

SECTION 2 INSIDE VIEWS
2 - 1
• BOTTOM VIEW
VCO-B circuit
YGR amplifier (IC151: µPC1678G) Pre amplifier (IC451: µPC1658G) FM IF IC (IC841: TA31136FN) RF unit 1st IF filter (FI132: SFPC455E-TC01) 2nd IF filter (FI111: CFK455E10) 3rd mixer (IC151: NJM1496V) MAIN unit
PLL unit MEMORY board DSP board VCO-A circuit Ceramic filter
(FI842: CFJ455K8)

2 - 2
•TOP VIEW
FILTER unit Current transformer (L1: LR-364) C-MOS IC (IC14: TC74AC04F)
FAN TUNER unit
Fan control circuit Antenna tuner CPU (IC5: M38022M2-138FP)
CTRL unit Common filter (L501, L502: LR-386) PA unit Drive amplifier

SECTION 3 CIRCUIT DESCRIPTION
3 - 1
3-1 RECEIVER CIRCUITS
3-1-1 RF SWITCHING CIRCUIT
(CTRL AND RF UNITS)
The RF switching circuit leads receive signals to bandpass
filters from an antenna connector while receiving. However,
the circuit leads the signal from the RF power amplifier to the
antenna connector while transmitting.
RF signals from [ANT 1] or [ANT 2] pass through the anten-
na selector (RL3), transmit/receive switching relays (RL1,
RL2, RL4), and low-pass filter (L27, L28, C63–C66, C105),
and are then applied to the RF unit via J2.
The signals from the CTRL unit either bypass or pass
through the 6 dB (RF unit, RL121, R121) and/or 12 dB (RF
unit, RL122, R123) attenuators via the antenna selector
(RL101). By selecting the attenuators, 0 (bypass), 6, 12 and
18 dB attenuations are obtained. The signals are then
applied to the RF filters.
When the [RX ANT] is selected, the RF signals are passed
through the low-pass filter (RF unit, L112, L111,
C111–C116), then applied to the antenna selector (RF unit,
RL101).
3-1-2 RF BANDPASS FILTER CIRCUIT (RF UNIT)
RF bandpass filters pass only the desired band signals and
suppress any undesired band signals. The RF circuit has 11
bandpass filters and 1 low-pass filter.
(1) 0.03–1.6 MHz
The signals pass through the low-pass filter (L181–L183,
C181–C185), attenuator (R181–R183), and are then applied
to the RF amplifiers (Q501, Q601).
(2) 1.6–60 MHz
The signals pass through the high-pass filter (L171–L174,
C171–C174) to suppress excessively strong signals below
1.6 MHz. The filtered signals are applied to one of 11 band-
pass filters as below, and then applied to or bypassed the
pre-amplifier circuit.
3-1-3 PRE-AMPLIFIER CIRCUITS (RF UNIT)
The IC-756PRO has 2 gain levels of pre-amplifier circuits.
One has 10 dB gain over a wide band frequency range and
the other one has 16 dB gain for the 21–28 MHz bands.
When the [PREAMP] switch is set to [PRE1] or [PRE2], the
signals are applied to the pre-amplifier 1 (Q441, Q442) or
pre-amplifier 2 (IC451) circuit, respectively. Pre-amplified or
bypassed signals are applied to the RF amplifier circuits
(Q501, Q601).
3-1-4 RF AMPLIFIER AND 1ST MIXER CIRCUITS
(RF UNIT)
The 1st mixer circuit mixes the receive signals with the 1st
LO signal to convert the receive signal frequencies into a
64.455 MHz 1st IF signal. The IC-756PRO has two 1st mixer
circuits for the dualwatch function.
The signals from the pre-amplifier circuit, or signals which
bypass the pre-amplifiers, are divided at L491. Each signal
is applied to a 60 MHz cut-off low-pass filter, RF amplifier
(Q501, Q601) and then to a 1st mixer (Q511–Q514 or
Q611–Q614).
Each 1st LO signal (64.4850–124.4550 MHz) enters the RF
unit from the PLL unit via J561 or J661. The LO signals are
amplified at the LO amplifier (Q561 or Q661), filtered by a
low-pass filter, and then applied to each 1st mixer.
•Used RF filter
• Receiver construction
LPF or
BPF 1st LO B
1st LO A
2nd LO
64.0 MHz
Crystal
filter
FI711
1st mixer A
Q511–Q614
1st mixer B
Q611–Q614 2nd mixer
Q941–Q944
3rd LO
491 kHz
3rd mixer
IC151
64.455 MHz
0.03–60.0 MHz
Ceramic
filter
FI132, FI111
455 kHz
to squelch gate
(IC301)
36 kHz DSP
board
RF UNIT MAIN UNIT
Band
0.03–1.6 MHz
1.6–2 MHz
2–3 MHz
3–4 MHz
4–6 MHz
6–8 MHz
8–11 MHz
Band
11–15 MHz
15–22 MHz
22–30 MHz
30–50 MHz
50–54 MHz
54–60 MHz
Control
signal
B7
B8
B9
B10W
B10
B10W
Control
signal
B0
B1
B2
B3
B4
B5
B6
Input
diode
N/A
D191
D211
D2311⁄2
D2311⁄2
D271
D2911⁄2
Input
diode
D311
D231
D2911⁄2
D391
D371
D391

3 - 2
3-1-5 1ST IF CIRCUIT (RF UNIT)
The 1st IF circuit filters and amplifies the 1st IF signal. The
1st IF signal combined at L653 is applied to an MCF
(Monolithic Crystal Filter; FI711a/b) to suppress out-of-band
signals.
The converted 1st IF signal level is adjusted at PIN attenua-
tors (D531–D533, D535 or D631–D632, D635) controlled by
the [BAL] controller for the dualwatch function. The signal is
applied to the 1st IF amplifier (Q551 or Q651) and then com-
bined at L653.
The combined signal passes through the MCFs (FI711a/b)
and PIN attenuator (D781, D783). The signal is amplified at
the 1st IF amplifier (Q721). The amplified signal is then
applied to the 2nd mixer circuit.
3-1-6 2ND MIXER CIRCUIT (RF UNIT)
The 2nd mixer circuit mixes the amplified 1st IF signal and
2nd LO signal (64.00 MHz) for conversion into the 2nd IF
signal.
The 1st IF signal from the 1st IF amplifier (Q721) is convert-
ed into a 455 kHz 2nd IF signal at the 2nd mixer circuit
(Q941–Q944).
The 2nd IF signal is applied to the ceramic filter (MAIN unit,
FI131) to suppress un-desired signals, and then applied to
the noise blanker gate.
3-1-7 NOISE BLANKER CIRCUIT (MAIN UNIT)
The noise blanker circuit detects pulse-type noise, and turns
OFF the signal line when the noise appears.
The 2nd IF signal from the ceramic filter (FI132) is applied to
the noise blanker gate (D112, D116). A portion of the signal
from FI132 is amplified at the noise amplifiers (Q271–Q273),
and is then detected at the noise detector (D271) to convert
the noise components to DC voltages.
The signal is then applied to the noise blanker switch (Q276,
Q278). At the moment the detected voltage exceeds Q276’s
threshold level, Q278 outputs a blanking signal to close the
noise blanker gate (D112, D116). The PLL unlock signal are
also applied to Q278, to control the noise blanker gate.
Some DC voltage from the noise detector circuit is fed back
to the noise amplifiers (Q271–Q273) via the DC amplifiers
(Q274, Q275). The DC amplifiers function as anAGC circuit
to reduce average noise. Therefore, the noise blanker func-
tion shuts off pulse-type noise only.
3-1-8 2ND IF CIRCUIT (MAIN UNIT)
The 2nd IF circuit filters and applies the 2nd IF signal to the
3rd mixer circuit.
The 2nd IF signal from the noise blanker gate (D112, D116)
is passed through the another ceramic filter (FI111). The fil-
tered signal is applied to the 3rd mixer circuit.
3-1-9 3RD MIXER AND 3RD IF CIRCUITS
(MAIN UNIT)
The 3rd mixer circuit mixes the 2nd IF signal and the 3rd LO
signal to obtain the 3rd IF (36 kHz) signal.
The 2nd IF signal from the ceramic filter (FI111) is applied to
the 3rd mixer circuit (IC151, pin 1). The 3rd LO signal from
the PLL unit is applied to the 3rd mixer (IC151, pin 10). The
mixed signal is output from pin 6.
The 3rd IF signal is amplified at the 3rd IF amplifier
(IC201b), and is passed through the low-pass filter (IC201a)
The filtered signal is then applied to the DSP board via DRIF
line.
3-1-10 DSP RECEIVER CIRCUIT (DSP BOARD)
The DSP (Digital Signal Processor) board enables digital IF
filter, digital noise reduction, digital PSN (Phase Shift
Network)/Low Power/Phase demodulation, digital automatic
notch, and etc.
The 36 kHz 3rd IF signal from the low-pass filter (MAIN unit,
IC201a) is amplified at the differential amplifiers (IC2301a/b)
after being passed through the T/R switch (IC2291), and is
then applied to the A/D converter (IC2321). The coverted
signal is level shifted 5V to 3.3 V at the level converter
(IC2051).
Differential
converter A/D converter
DRIF
DRAF
•DSP receiver circuit
6
71
IC2291 IC2301B/A IC2321 Level
converter
IC2051 D/A
converter
IC2052
Level
converter
IC2351
DSP IC
IC2001
LPF
IC2401
T/R switch
13
12
14
IC2372X
15
9
1
IC2372Y HPF
IC2441A Mixer
amplifier
IC2381B
5
3
4
IC2372Z
7
4
1
IC2473
MAIN unit DSP board MAIN unit
36 kHz
3rd IF
signal
AF
signals
“TXS”signal
“TXS”signal “TXS”signal
5
11 10

3 - 3
The level shifted signal is applied to the DSP IC (IC2001) for
36 kHz digital IF filter, demodulation, automatic notch and
noise reduction, etc. The output signal is level shifted 3.3 V
to 5V at the level converter (IC2052), and is applied to the
D/A converter (IC2351) to convert into the analog audio sig-
nals.
The converted audio signals are passed through the active
filter (IC2371a), AF amplifier (IC2371b), analog switches
(IC2372, pins 14, 13 and pins 1, 15) then applied to the low-
pass filter (IC2401). The filtered signals are passed through
the analog switches (IC2372, pins 4, 3 and IC2473), high-
pass filter (IC2441A) and mixer amplifier (IC2471A), and
then applied to the MAIN unit via J2001 (pin 13) as the DTAF
signal.
3-1-11 TWIN PBT CIRCUIT (DSP BOARD)
General PBT (Passband Tuning) circuit shifts the center fre-
quency of IF signal to electronically narrow the passband
width. The IC-756PRO uses the DSP circuit for the digital
PBT function and actually shifts the both lower and higher
passbands of 3rd IF filter within ±1.8 kHz.
The twin PBT circuit in DSP IC (IC2001) controlled by the
[TWIN PBT] controller adjusts the 3rd IF passband width
and rejects interference.
3-1-12 AGC CIRCUIT (DSP BOARD)
The AGC (Automatic Gain Control) circuit reduces IF ampli-
fier gain and attenuates IF signal to keep the audio output at
a constant level.
The receiver gain is determined by the voltage on the AGC
line (IC2461, pin 4). The D/A converter for AGC (IC2461)
supplies control voltage to the AGC line and sets the receiv-
er gain with the [RF/SQL] control.
The 3rd IF signal from the level converter (IC2051) is detect-
ed at the AGC detector section in DSP IC (IC2001), and is
applied to the D/A converter for AGC via the level converter
(IC2052). TheAGC voltage is amplified at the buffer amplifi-
er (IC2471b) and is applied to the MAIN unit to control the
AGC line.
When receiving strong signals, the detected voltage increas-
es and the AGC voltage decreases via the buffer amplifier
(IC2471b). As the AGC voltage is used for the bias voltage
of the IF amplifier (RF unit; Q721), IF amplifier gain is
decreased. And also AGC voltage is amplified at the AGC
amplifier (RF unit; IC871c) and applied to the ATT driver
(Q781, D784) to drive the PIN attenuator (D781, D783).
3-1-13 S-METER CIRCUIT (MAIN UNIT)
The S-meter circuit indicates the relative received signal
strength while receiving by utilizing the AGC voltage which
changes depending on the received signal strength.
A portion of the AGC bias voltage from the DSP board is
applied to the differential amplifier (IC101a, pin 2) where the
difference between theAGC and reference voltage is detect-
ed.
The detected voltage is passed through the analog switch
(IC3631, pins 12, 14) as the SML signal and applied to the
main CPU (IC3501, pin 108) to activate the S/RF meter via
the sub CPU (IC401) on the DISPLAY board.
3-1-14 SQUELCH CIRCUIT (MAIN UNIT)
The squelch circuit mutes audio output when the S-meter
signal is lower than the [RF/SQL] setting level.
The S-meter signal is applied to the main CPU (IC3501, pin
108) and is compared with the threshold level set by the
[RF/SQL] control. The [RF/SQL] setting signal is applied to
the main CPU via the sub CPU (DISPLAY board; IC401, pin
91). The main CPU analyzes the compared signal and out-
puts control signal to the squelch gate (IC301, pin 5) via the
interface IC (IC3653, pin 19) to open or close the squelch as
the SQLS signal.
3-1-15 AF AMPLIFIER CIRCUIT (MAIN UNIT)
TheAF amplifier amplifies the audio signals to a suitable dri-
ving level for the speaker.
The AF signals (DRAF) from the DSP board are passed
through the squelch gate (IC301) and amplified at the AF
amplifier section of IC311 (pins 2, 4) and volume is con-
trolled by the AFGV signal at the VCA section (pins 7–9).
The volume controlledAF signals are passed through theAF
mute gate (IC331, pins 1, 7), then applied to the AF power
amplifier (IC332, pin 1) via the ripple filter (Q331).
The amplified audio signals are passed through the
[PHONES] and [EXT SP] jacks then applied to the internal
speaker when no plug is connected to the jacks.
The AF mute gate is controlled by the [AF] control via the
sub and main CPUs.
[PHONES]
[EXT SP]
Int. speaker
IC332
AF
power
amp.
DRAF
•AF amplifier circuit
7
61
IC301 IC311
Mute switchSquelch gate
Ripple
filter
Q331
MAIN unitDSP board
“SQLS”signal
“AFGV”signal
56
7
1
IC331 “AFMS”signal
2
AMP VCA

3 - 4
3-2 TRANSMITTER CIRCUITS
3-2-1 MICROPHONE AMPLIFIER CIRCUIT
(MAIN UNIT)
The microphone amplifier circuit amplifies microphone audio
signals to a level needed for the DSP.
Audio signals from the [MIC] connector (MIC board; J1, pin
1) are amplified at the audio amplifier section in IC451 (pins
21–23) via the analog switch (IC3002, pins 12, 14), then
applied to the buffer amplifier section (IC451, pin 5) and
VCA section. The gain controlled signals are output from
(IC451, pin 9) and passed through the analog switch
(IC3005, pins 14, 12) and then applied to the DSP circuit as
the DTAF signal.
The VCA section in IC451 (pins 7–9) controls microphone
input gain according to the [MIC GAIN] control level using
the MIGV signal coming from the main CPU via the I/O
expander (IC3751, pin 4).
3-2-2 VOX CIRCUIT (MAIN UNIT)
The VOX (Voice-Operated Transmission) circuit sets trans-
mitting conditions according to voice input.
A portion of the amplified audio signals from the AF amplifi-
er section in IC451 are again amplified at the VOX amplifier
section IC451 (pin 9), also gain contolloed signals at the
VCA section (pin 9) are amplified at the AF amplifier
(IC3004b, pins 6, 7), and then applied to the main CPU
(IC3501, pin 106) after passing through the analog switch
(IC362, pins 6, 1) as the VOXL signal.
The VOGV signal is applied to the VCA section in IC3003
(pin 7–9) from the main CPU via the I/O expander (IC3751,
pin 9) to adjust VOX actionable sensitivity. This is controlled
by the VOX gain set in the VOX SET mode.
3-2-3 DSP TRANSMITTER CIRCUIT (DSP BOARD)
The microphone audio signals from the MAIN unit via the
DTAF line are passed through the analog switch (IC2201,
pins 4 and 3 or 5) and applied to the each modulation cir-
cuits.
(1) When SSB mode
The audio signals from the analog switch (IC2201, pin 5) are
amplified at the limitter amplifier (IC2281b) and applied to
the low-pass filter (IC2281d/c) to limit the transmit passband
width.
The filtered signals are then applied to the differential ampli-
fiers (IC2301a/b) via the analog switch (IC2201) and T/R
switch (IC2291).
(2) When FM/AM modes
The audio signals from the analog switch (IC2201, pin 3) are
applied to the deviation adjustment pots (R2227: FM mode,
R2229:AM mode) via the limitter amplifier, pre-emphasis cir-
cuit (only FM mode) and splatter filter consist of IC2211.
The level adjusted signals are applied to the differential
amplifiers (IC2301a/b) after being passed through the ana-
log switch (IC2201) and T/R switch (IC2291). When AM
mode the pre-emphasis circuit is cancelled by Q2201,
Q2202, Q2211.
The amplified signals at the differential amplifiers
(IC2301a/b) are applied to the A/D converter (IC2321). The
coverted signals are level shifted 5V to 3.3 V at the level
converter (IC2051).
The level shifted signal is applied to the DSP IC (IC2001)
and modulated at the DSP IC to produce the 36 kHz trans-
mit IF signal. The modulated IF signal from the DSP IC is
level shifted 3.3 V to 5V at the level converter (IC2052), and
is applied to the D/A converter (IC2351) to convert into the
analog IF signal.
The converted IF signal is passed through the active filter
(IC2371a), buffer amplifier (IC2371b), analog switch
(IC2372, pins 14, 12) then applied to the low-pass filter
(IC2381c/d). The filtered signal is applied to the MAIN unit
via J2001 (pin 28) as the DTIF signal.
A portion of the filtered signal from the low-pass filter
(IC2381c/d) is amplified at the IF amplifier (IC2381b) and
applied to the transmit monitor circuit for the monitor func-
tion.
3-2-4 SPEECH COMPRESSOR CIRCUIT
(DSP BOARD)
The speech compressor compresses the transmitter audio
input signals to increase the average output level (average
talk power).
When the [COMP] switch is ON, the level shifted signal from
the level converter (IC2051) is applied to the DSP IC
(IC2001) and compressed at the DSP IC to obtain an aver-
age audio level.
At the same time, the compressed signals are modulated at
the DSP IC and applied to the level converter (IC2052).
•Transmitter construction
1st LO
D771
Ceramic
filter
Crystal
filter
FI711
LPF BPFs
FI131
Ceramic
filter
FI133
MIC
Bandwidth
15 kHz
455 kHz
DSP
board
RF UNIT
MAIN UNIT
AMP VCA
FM/AM
modes
other
modes
3rd LO
(491 kHz)
IC221
64.455 kHz
2nd LO
(64.00 MHz)
D741
36 kHz IF
IC451 11
12
13
14
IC3005X
“MOSL”signal
DTAF DTIF

3 - 5
3-2-5 IF AMPLIFIER AND MIXER CIRCUITS
(MAIN AND RF UNITS)
The modulated 3rd IF signal from the DSP board (DTIF: 36
kHz) is applied to the 3rd mixer circuit (MAIN unit; IC221).
The applied 3rd IF signal is mixed with the 3rd LO signal
from the DDS circuit (PLL unit; IC701) to produce a 455 kHz
2nd IF signal.
The 2nd IF signal is output from pin 6 and amplified at the IF
amplifier (MAIN unit; Q241). The amplified signal is passed
through the ceramic bandpass filter (MAIN unit; FI131:
FM/AM modes, FI133: other modes) for unwanted signals
are suppressed. The filtered 2nd IF signal is ampllified at IF
amplifier (MAIN unit; Q261) and applied to the 2nd mixer cir-
cuit on the RF unit via J101.
The 2nd IF signal is mixed with the 64 MHz 2nd LO signal,
coming from the PLL unit, at the 2nd mixer circuit (RF unit;
D741) to obtain a 64.455 MHz 1st IF signal. The 1st IF sig-
nal is passed through the MCF (RF unit; FI711) to cut-off the
undesired signals then amplified at the IF amplifier (RF unit;
Q751) via the T/R switch (RF unit; D711). The amplified 1st
IF signal is applied to the 1st IF mixer circuit (RF unit; D771).
The operating (transmitting) frequency is produced at the 1st
IF mixer circuit (RF unit; D771) by mixing the 1st IF and 1st
LO signals. The mixed signal is then applied to the RF cir-
cuit.
3-2-6 RF CIRCUIT (RF AND PA UNITS)
The RF circuit amplifies operating (transmitting) frequency
to obtain 100 W of RF output.
The signal from the 1st IF mixer is passed through the low-
pass filter (RF unit; L961, L962, C961–C966) and amplified
at the RF amplifier (RF unit; IC961). The amplified signal is
again amplified at the wide-band YGR amplifier (RF unit,
IC151) after passing through one of 11 bandpass (Refer to
page 3-1 for bandpass filters used) and high-pass filters,
and is then applied to the PA unit via J151.
The signal applied from the RF unit is amplified at the pre-
drive (Q1), drive (Q2, Q3) and power amplifiers (Q4, Q5) in
sequence to obtain a stable 100 W of RF output power. The
amplified signal is applied to one of 8 low-pass filters in the
FILTER unit.
3-2-7 LOW-PASS FILTER CIRCUIT (FILTER UNIT)
The low-pass filter circuit contains 8 Chebyschev low-pass
filters to suppress the higher harmonic components.
The signal from the power amplifiers in the PAunit is applied
to one of the low-pass filters, which is selected by the I/O
expander (IC11) in the CTRL unit via the buffer-amplifier
(CTRL unit; IC12).
The filtered signal is then applied to one of 2 antenna con-
nectors via the CTRL only/and TUNER unit/s.
3-2-8 ALC CIRCUIT (MAIN UNIT)
The ALC (Automatic Level Control) circuit controls the gain
of IF amplifiers in order for the transceiver to output a con-
stant RF power set by the [RF POWER] control even when
the supplied voltage shifts, etc.
The RF power level is detected at one of the APC detector
circuits (CTRL unit; D2) to be converted into DC voltage and
applied to the MAIN unit as the FORV signal.
The FORV signal from the CTRL unit is applied to the com-
parator (IC551b, pin 6). The POCV signal, controlled by the
[RF POWER] control via the I/O expander (IC3751, pin 5), is
also applied to the other input (pin 5) for reference. The
compared signal is output from pin 7 and applied to the IF
amplifiers in the MAIN (Q261) and RF (Q751) units to con-
trol amplifying gain.
When the FORV signal exceeds the POCV voltage, ALC
bias voltage from the comparator controls the IF amplifiers.
This adjusts the output power to a specified level from the
[RF POWER] control until the FORV and POCV voltages are
equalized.
In AM mode, the comparator operates as an averaging ALC
amplifier. Q502 turns ON and the POCV voltage is shifted
for 40 W AM output power (maximum) through R510.
DTAF
•DSPTransmitter circuit
LPF
IC2281C/DIC2281B
IC2211A
LPF
IC2211B
MAIN unit DSP board
AF
signal
“MODS”signal
4
95
3
IC2201Z
Mode switch
Differential
converter
A/D
converter DTIF
6
71
IC2291 IC2301A/B
IC2321 Level
converter
IC2051 D/A
converter
IC2052
Level
converter
IC2351
DSP IC
IC2001
LPF
IC2381D/C
T/R switch
13
12
14
IC2372X
MAIN unit
36 kHz IF
“TXS”signal
“TXS”signal
5
12
13 14
IC2201X
Mode switch
11
11
Limitter
Limitter
SSB
mode
FM/AM
mode

3 - 6
TheALC bias voltage is also applied to theALC meter ampli-
fier (IC551a, pin 2) to obtain an ALC meter signal (ALCL).
The amplified signal is passed through the analog switch (IC
3631, pins 13, 14) and applied to the main CPU (IC3501, pin
108) to drive the S/RF meter via the sub CPU (IC401) on the
DISPLAY board.
An external ALC input from the [ALC] jack or [ACC] sockets
is applied to the buffer amplifier (Q521). External ALC oper-
ation is identical to that of the internal ALC.
The FORV signal is also applied to the power meter amplifi-
er (IC571a, pin 3). The amplified signal is passed through
the analog switch (IC3631, pins 1, 15) as an FORL signal
and applied to the main CPU (IC3501, pin 109) to drive the
S/RF meter when the power meter is selected.
3-2-9 APC CIRCUIT (MAIN UNIT)
The APC (Automatic Power Control) circuit protects the
power amplifiers on the PA unit from high SWR and exces-
sive current.
The reflected wave signal appears and increases when the
connected antenna is mismatched to 50 Ω. The APC detec-
tor circuit (CTRL unit; D1 and L1) detects the reflected sig-
nal, and applies it to the APC circuit (IC551c, pin 9) as a
REFV signal.
When the REFV signal level increases, the APC circuit
decreases the ALC voltage to activate the APC.
For the currentAPC, the power transistor current is obtained
by detecting the voltages (ICH and ICL) which appear at
both terminals of the current detector (PA unit, R28). The
detected voltages are applied to the differential amplifier
(IC551d, pins 12, 13). When the current of transistors is
increased, the amplifier controls the ALC line to prevent
excessive current flow.
A portion of the REFV signal is applied to the SWR meter
amplifier (IC571b, pin 5). The amplified signal is passed
through the analog switch (IC3631, pins 3, 4) as an REFL
signal and applied to the main CPU (IC3501, pin 110) to
drive the S/RF meter when the SWR meter is selected.
3-2-10 TEMPERATURE PROTECTION CIRCUIT
(PA UNIT)
The cooling fan (MF1) is activated while transmitting or
when the temperature of the power amplifier exceeds the
preset value. The temperature protection circuit consists of
Q10–Q13 and R50.
While transmitting, Q10 and Q12 are turned ON, and pro-
vide a voltage to the cooling fan to rotate at medium speed.
The thermistor detects the temperature of Q5, and activates
Q11 and Q13 to accelerate the cooling fan when the detect-
ed temperature exceeds 70˚C (158˚F). The cooling fan
rotates at high speed at 80˚C (176˚F) or more.
The thermistor keeps the cooling fan rotating even while
receiving until the Q5 temperature drops to 60˚C (140˚F) or
below.
3-2-11 MONITOR CIRCUIT
(DSP BOARD AND MAIN UNIT)
The microphone audio signals can be monitored to check
voice characteristics.
(1) When FM/AM modes (MAIN UNIT)
Aportion of the microphone audio signals from the VCAsec-
tion in IC451 are applied to the analog switch (IC361). The
selected audio signals are applied to IC371 (pin 2), and the
output signals from pin 9 are applied to the AF amplifier cir-
cuit (IC311, pin 7).
(2) When SSB/RTTY modes (DSP BOARD)
A portion of the transmit IF signal from the low-pass filter
(IC2381c/d) is amplified at the IF (IC2381b) and buffer
(IC2381a) amplifiers and applied to the digital mixer circuit
(IC2302). The applied signal is mixed with a 36 kHz LO sig-
nal from IC2347 to demodulate into the AF signals. The
demodulated signals are passed through the buffer amplifi-
er (IC2381a), low-pass filter (IC2441b/c) and AF amplifier
(IC2441d), and then applied to the MAIN unit as the DMAF
signal.
The DMAF signal from the DSP board is amplified at ALC
amplifier (MAIN unit; IC372) and applied to the VCA section
of IC371 (MAIN unit). The volume controlled AF signals is
applied to the AF amplifier circuit (MAIN unit; IC311, pin 7).
3-3 PLL CIRCUITS
3-3-1 GENERAL
The PLL unit generates a pair of 1st LO frequencies
(64.485–124.455 MHz) for dualwatch and spectrum scope
functions; a 2nd LO frequency (64 MHz), 3rd LO frequency
(491 kHz) and sweep LO frequency for the spectrum scope
function.
The 1st LO PLLs adopt a mixer-less dual loop PLL system
and has 4 VCO circuits. The LOs, except the 2nd, use DDSs
while the 2nd LO uses the fixed frequency of the crystal
oscillator.
3-3-2 1ST LO PLL CIRCUIT
The 1st LO PLLs contain a main and reference loop as a
dual loop system. Both PLLs have equivalent circuits—this
manual describes only the 1st LO PLL A circuit.
The reference loop generates a 10.747 to 10.865 MHz fre-
quency using a DDS circuit, and the main loop generates a
64.485 to 124.455 MHz frequency using the reference loop
frequency.
(1) REFERENCE LOOP PLL
The oscillated signal at the reference VCO (Q151, D151) is
amplified at the amplifiers (Q152, Q102) and is then applied
to the DDS IC (IC101, pin 46). The signal is then divided and
detected on phase with the DDS generated frequency.
The detected signal output from the DDS IC (pin 56) is con-
verted into DC voltage (lock voltage) at the loop filter
(R135–R137, C121, C151) and then fed back to the refer-
ence VCO circuit (Q151, D151).

3 - 7
(2) MAIN LOOP PLL
The oscillated signal at one of the main loop VCOs (Q201,
D201, D202), (Q221, D221, D222), (Q251, D251–D254) and
(Q271, D271–D274) is amplified at the buffer amplifiers
(Q301, IC320) and is then applied to the PLL IC (IC381, pin
6). The signal is then divided and detected on phase with the
reference loop output frequency.
The detected signal output from the PLL IC (pin 2) is con-
verted into a DC voltage (lock voltage) at the loop filter and
then fed back to one of the VCO circuits (Q201, D201,
D202), (Q221, D221, D222), (Q251, D251–D254) and
(Q271, D271–D274).
The oscillated signal is amplified at the buffer amplifiers
(Q301, IC320) and then applied to the RF unit as a 1st LOA
signal after being passed through the bandpass filter (L303,
L351–L354, C304–C307, C351–C356, C358–C360).
3-3-3 2ND LO AND REFERENCE OSCILLATOR
CIRCUITS
The reference oscillator (X52, Q51) generates a 32.00056
MHz frequency for the 4 DDS circuits as a system clock and
for the LO output. The oscillated signal is doubled at the
doubler circuit (Q71, Q81) and the 64.0 MHz frequency is
picked up at the double tuned filter (L81, L82). The 64.0
MHz signal is applied to the RF unit as a 2nd LO signal.
3-3-4 3RD LO CIRCUIT
The DDS IC (IC701) generates a 10-bit digital signal using
the 32 MHz system clock. The digital signal is converted into
an analog wave signal at the D/A converter (R701–R720).
The converted analog wave is passed through the bandpass
filter (L702, L703, C709–C713) and then applied to the
MAIN unit as the 3rd LO signal.
3-3-5 MARKER CIRCUIT
The divided signal at the DDS circuit (IC101) is used for the
marker signals with the IC-756PRO.
The reference signal for the DDS circuit (32.0 MHz) is divid-
ed to produce an acceptable frequency signal, 16 MHz, with
the programmable divider then divided again by 160 to
obtain 100 kHz cycle square-wave signals.
The generated marker signals are output from pin 66 of the
DDS IC (IC101), and are then applied to the RF unit via the
mute switch (IC192) and J851 as the MKR signal.
•PLL CIRCUIT
64.485–
124.455 MHz
10.747–
10.865 MHz
64.485–
124.455 MHz
64.0 MHz
77.8 MHz
ANT
1st mixer A
Q511–Q514
491 kHz
to scope circuit (RF unit, D831) to scope circuit (RF unit, IC841)
IC801IC701
IC101
IC381
IC901
Q71
Q81
Q902
S2LOS3LO3LO2LO
1LOB
1LOA
77.8 MHz
RF unit
PLL unit
MAIN unit
Q202
Q222
Q252
Q272
Q151
1st LO PLL A
circuit
Phase
detector
1/N divider
1/22
Phase
detector
12 bit
D/A
Main loop PLL
Ref. loop PLL
DDS
1st mixer B
1st LO
PLL B
circuit
✕2
DDS
D/A
DDS
D/A
PLL
IC
Crystal
filter
2nd mixer
Q941–Q944 3rd mixer
IC151
64.455 MHz
to DSP board
Reference oscillator
X51: 32.0 MHz
BPF
Loop
filter
LPF
LPF

3 - 8
3-4 ANTENNA TUNER CIRCUITS
3-4-1 MATCHING CIRCUIT (TUNER UNIT)
The matching circuit is a T-network. Using 2 tuning motors,
the matching circuit obtains rapid overall tuning speed.
Using relays (RL1–RL15), the relay control signals from the
antenna tuner CPU (CTRL unit; IC5) via the buffer-amplifier
(IC1, IC2) ground one of the taps of L3–L12 and add capac-
itors (C27–C43). After selecting the coils and capacitors, 2
motors (CTRL unit; MF1, MF2) adjust C44 and C45 using
the antenna tuner CPU (CTRL unit; IC5) and the motor con-
troller (CTRL unit; Q211–Q218, D211–D217) to obtain a low
SWR (Standing Wave Ratio).
3-4-2 DETECTOR CIRCUIT (CTRL UNIT)
(1) SWR detector
Forward and reflected power are picked up by a current
transformer (L1), detected by D2 and D1, and then amplified
at IC1a and IC1b, respectively. The amplified voltages are
applied to the antenna tuner CPU (IC5, pins 2, 3). The tuner
CPU detects the SWR.
(2) Reactance components detector
Reactance components are picked up by comparing the
phases of the RF current and RF voltage. The RF current is
detected by L4 and R16 and buffer-amplified at IC14e and
IC2a and then applied to the phase comparator (IC3a). RF
voltages are detected by C12–C14 and then applied to the
phase comparator (IC3b) after being amplified at the buffer-
amplifiers (IC14c, IC2b). The output signal from the phase
comparator (IC3a, pin 6 for RF current, IC3b pin 7 for RF
voltage) is rectified at D7 and D6 for conversion into DC volt-
age. The rectified voltage signals are combined, then ampli-
fied at the inverter amplifier (IC4b), then applied to the
antenna tuner CPU (IC5, pin 64).
A C-MOS IC is used for the buffer-amplifier (IC14) to
improve functionable sensitivity; the inverter amplifier (IC4)
is very responsive even with a low signal level input.
Together, these ensure quick and stable signal detection
even at low RF signal level input.
(3) Resistance components detector
Resistance components are picked up by L8, and detected
by D8, D9 and Q5. The detected resistance components are
amplified at the inverter amplifier (IC4a), and then applied to
the antenna tuner CPU (IC5, pin 1).
3-4-3 MOTOR CONTROL CIRCUIT
(CTRL AND TUNER UNITS)
The control circuit of the internal antenna tuner consists of
the CPU, EEPROM*, tuning motors and tuning relays.
*Electronically-Erasable Programmable Read Only Memory
(1) CPU and EEPROM (CTRL unit)
The antenna tuner CPU (IC5) controls the tuning motors via
the motor controller (Q211–Q218, D211–D217) and tuning
relays, and memorizes the best preset position in 100 kHz
steps. The memory contents are stored in the EEPROM
(IC6) without a backup battery.
(2) Tuning motors (CTRL and TUNER units)
A motor controller (Q211–Q218, D211–D217) rotates the
tuning motors (TUNER unit; MF1, MF2) to obtain a low
SWR.
(3) Tuning relays (TUNER unit)
According to the operating frequency band and antenna
condition, tuning relays select the capacitors and coils.
3-4-4 ANTENNA TUNER CPU PORT ALLOCATION
(CTRL unit; IC5)
1
2
3
4
6
7
13
15
17
21
22, 23
26
27–32
34–40
41–48
64
Input port for the resistance com-
ponents detection voltage.
Input port for the reflected RF
power voltage.
Inpout port for the forward RF
power voltage.
Input port for the transceiver power
OFF.
Inputs low level signal when oper-
ating the antenna tuner in 50 MHz
band.
Input port for reference voltage set-
ting.
Outputs tuner data signal.
Input port for the serial signal.
Input port for the [TUNER]
ON/OFF signal.
Input port for the TX/RX switching
signal.
Input port for the antenna tunner
CPU system clock.
Outputs the coil selection signal.
High : While 46–60 MHz band is
displayed.
Output the coil selection signal.
Output the capacitor selection sig-
nal.
Output pulse-type control signals
for the tuning motors (M1, M2).
Input port for the reactance compo-
nents detection voltage.
R
REF
FOR
PWRS
STDU
SETI
KEY
START
THRU
SEND
CL1, CL2
DUAL
L24M, L18M,
L14M, L10M,
L7M, L3.5M
CO3, CO2,
CO1, CI3,
CI2, CI1
PZ, PY, PX,
PW, RZ, RY,
RX, RW
P
Pin Port Description
number name

3 - 9
3-5 SCOPE CIRCUITS
3-5-1 SCOPE RECEIVER CIRCUIT (RF UNIT)
A portion of the 64.455 MHz 1st IF signal from the 1st mixer
circuit (Q511–Q514: while receiving) or IF amplifier (Q751:
while transmitting) is amplified at the IF amplifiers (Q811,
Q812), then mixed with the 77.8 MHz scope 2nd LO signal
at the mixer circuit (D831) to produce the 13.345 MHz IF sig-
nal. The mixed IF signal is passed through the ceramic
bandpass filters (FI843, FI841) to suppress unwanted sig-
nals. The filtered IF signal is applied to the FM IF IC (IC841,
pin 16).
The applied 13 MHz IF signal is mixed with the sweep LO
signals from the PLL unit at the FM IF IC (IC841), which
includes the RSSI terminal. The mixed IF signals are filtered
at the ceramic bandpass filter (FI842) then applied to the
limiter amplifier section in the FM IF IC (IC841, pin 5). The
applied IF signals are converted into DC voltages according
to the applied IF signal strength at the RSSI section in the
IC.
The converted voltages are amplified at IC871b then applied
to the MAIN unit as the SCPL signal.
Some of the DC voltages from the FM IF IC are amplified at
IC871a to produceAGC voltages for the IF amplifiers (Q811,
Q812), producing wider dynamic range.
By sweeping LO signals (S3LO) are applied to the mixer
section in the FM IF IC, the spectrum scope function is acti-
vated.
3-5-2 SWEEP LO CIRCUIT (PLL UNIT)
The sweep LO signals (S3LO) are generated by the DDS IC
(IC801) using the 32 MHz system clock. A 10-bit digital sig-
nal is converted into analog wave signals at the D/A con-
verter (R801–R820). The converted analog wave is passed
through the bandpass filter (L802, L803, C809–C813) then
applied to the RF unit after being amplified at the buffer
amplifier (Q802).
3-6 POWER SUPPLY CIRCUITS
3-6-1 PA UNIT
3-6-2 FRONT UNIT
•SCOPE CIRCUIT DIAGRAM
RF unit
1st mixer A
Q511–Q514
Q811
to 2nd mixer circuit
to the MAIN unit SCPL signal
Q812
D831 FI843 FI841
Ceramic
BPF Ceramic BPF
IF
amp.
IC871a
AGC
IC871b
amp.
IF
amp.
Ceramic
BPF
Limiter
amp.
Mixer
IC841
FI842
S3LO signal
(12.79–12.99 MHz*)
S2LO signal
(77.80 MHz)
1st LO
signal
16
12
5
3
2
RSSI
*depending on sweeping passband width
RF signals
LINE
PHV
HV
14 V
14 VA
8 V
5 V
H5V
DESCRIPTION
The voltage from an external power supply via
the common filter circuit (FILTER unit, L501,
L502).
The same voltage as the PHV line passed
through a fuse (F1).
The same voltage as the HV line passed through
the switching relay (RL1).
The same voltage as the 14 V line is applied to
the AF power amplifier (MAIN unit, IC332).
Common 8 V converted from the 14 V line and
regulated by the +8 regulator circuit (IC3).
Common 5 V converted from the 14 V line and
regulated by the +5 regulator circuit (IC2).
Common 5 V converted from the 14 V line and
regulated by the H5V regulator circuit (IC1).
LINE
5V
–15V
–7V
–8V
+18V
DESCRIPTION
Common 5 V converted from the 14 V line and
regulated by the +5 regulator circuit (IC861).
Common –15 V converted from the 14 V line and
converted by the –15 DC-DC converter circuit
(IC841, Q841, D841). The voltage is applied to
the –7 V, –8 V regulator circuits and etc.
Common –7 V converted from the 14 V line and
regulated by the –7 regulator circuit (IC501).
Common –8 V converted from the 14 V line and
regulated by the –8V regulator circuit (IC881).
Common 18 V converted from the 14 V line and
converted by the 18 V DC-DC converter circuit
(IC821, Q821, D822).

3 - 10
3-6-3 MAIN UNIT
3-6-4 CTRL AND PLL UNITS
3-7 LOGIC CIRCUITS
3-7-1 BAND SELECTION DATA
(RF, CTRL AND PLL UNITS)
To select the correct bandpass, low-pass filters and VCOs
on the RF, FILTER and PLL units, the main CPU (MAIN unit,
IC3501) outputs the following band selection data via the I/O
expander (RF unit, IC901, IC902, CTRL unit, IC11) or DDS
IC (PLL unit, IC101, IC401) depending on the displayed fre-
quency.
The D/A convertor (MAIN unit, IC3751) output signal from
pin 7 is amplified at IC101b (pins 5–7) to obtain the band
voltage for external equipment via the [ACC 2] connector pin
4.
0.003–1.599999
1.6–1.999999
2.0–2.999999
3.0–3.999999
4.0–5.999999
6.0–7.999999
8.0–10.999999
11.0–14.999999
15.0–19.999999
20.0–21.999999
22.0–29.999999
30.0–44.999999
45.0–49.999999
50.0–54.000000
54.000001–
60.000000
Frequency
IC901, IC902 IC11 IC101 IC401
[MHz] (RF unit) (CTRL) (PLL) (PLL)
BPF LPF VCO-A VCO-B
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10W
B10
B10W
L1S
L2S
L3S
L4S
L5S
L6S
L7
VA1S
VA2S
VA3S
VA4S
VB1S
VB2S
VB3S
VB4S
LINE
R8V
T8V
DESCRIPTION
Receive 8 V converted from the 14 V line and
regulated by the R8V regulator circuit (Q601,
Q602, D601).
Transmit 8 V converted from the 14 V line and
regulated by the T8V regulator circuit (Q611,
Q612, D611).
LINE
5V
5V
DESCRIPTION
Common 5 V for the antenna tuner CPU (CTRL
unit; IC5) and the EEPROM (CTRL unit; IC6),
converted from the 14 V line and regulated by
the +5 regulator circuit (CTRL unit; IC13).
Common 5 V for each of the PLL-A and PLL-B
circuits regulated from the 8 V line and regulated
by the +5 regulator circuit (PLL unit; IC382: PLL-
A, IC682: PLL-B).

SECTION 4 ADJUSTMENT PROCEDURES
4 - 1
4-1 PREPARATION BEFORE SARVICING
■REQUIRED TEST EQUIPMENT
DC power supply
RF power meter
(terminated type)
Frequency counter
RF voltmeter
FM deviation meter
Modulation analyzer
Distortion meter
Oscilloscope
Audio generator
Standard signal
generator (SSG)
Digital multimeter
AC millivoltmeter
DC voltmeter
DC ammeter
Spectram analyzer
Attenuator
External speaker
Terminator
EQUIPMENT GREDE AND RANGE EQUIPMENT GREDE AND RENGE
Output voltage : 13.8 V DC
Current capacity : 30 A or more
Measuring range : 10–200 W
Frequency range : 1.8–100 MHz
Impedance : 50 Ω
SWR : Less than 1.2 : 1
Frequency range : 0.1–100 MHz
Frequency accuracy : ±0.5 ppm or better
Sensitivity : 100 mV or better
Frequency range : 0.1–100 MHz
Measuring range : 0.01–10 V
Frequency range : DC–500 MHz
Measuring range : 0 to ±5 kHz
Frequency range : At least 90 MHz
Measuring range : 0–100 %
Frequency range : 1 kHz ±10 %
Measuring range : 1–100 %
Frequency range : DC–20 MHz
Measuring range : 0.01–20 V
Frequency range : 300–3000 Hz
Measuring range : 1–500 mV
Frequency range : 0.1–100 MHz
Output level : 0.1 µV–32 mV
(–127 to –17 dBm)
Imput impeadance : 10 MΩ/DC or beter
Measuring range : 10 mV–10 V
Input impedance :
50 kΩ/V DC or better
Measurement capability: 1 A/30 A
Frequency range : At least 90 MHz
Spectraum bandwidth : 100 kHz or more
Power attenuation : 50 or 60 dB
Capacity : 150 W or more
Input impedance : 8 Ω
Capacity : 5 W or more
Resistance : 50 and 150 Ω
Capacity : 150 W or more
‘‘CONNECTIONS
[ANT1] [ANT2]
FM deviation meter
Modulation analyzer
RF power meter
Spectrum analyzer
Attenuator
Distortion meter
DC power supply Ammeter
Standard signal
generator
CAUTION !
DO NOT transmit while
an SSG is connected to
the antenna connector.
to the antenna connector
to [DC 13.8 V]
to [EXT SP]
Speaker
Audio generator
PTT
,.
[MIC]

4 - 2
4-2 PLL ADJUSTMENTS
REFERENCE
FREQUENCY
LPL-A LOCK
VOLTAGE
VCO-A LOCK
VOLTAGE
1LO-A
OUTPUT
LEVEL
LPL-B LOCK
VOLTAGE
VCO-B LOCK
VOLTAGE
1LO-B
OUTPUT
LEVEL
3LO
OUTPUT
LEVEL
S3LO
OUTPUT
LEVEL
ADJUSTMENT
ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT VALUE POINT
UNIT LOCATION UNIT ADJUST
1
2
1
1
2
3
4
1
1
1
2
3
4
1
1
1
•Display frequency: Any
•Turn L52 on the PLL unit to 4 rota-
tion downside for presetting.
•Receiving
•Display frequency: 0.030000 MHz
•Mode : USB
•Receiving
•Display frequency
: 14.999999 MHz
•Mode : USB
•Receiving
•Display frequency
: 19.999999 MHz
•Mode : USB
•Receiving
•Display frequency : 44.999999 MHz
•Mode : USB
•Receiving
•Display frequency : 60.000000 MHz
•Mode : USB
•Receiving
•Display frequency :
0.030000 MHz, 7.999999 MHz
8.000000 MHz, 19.999999 MHz
20.000000 MHz, 44.999999 MHz
45.000000 MHz, 60.000000 MHz
•Receiving
•Sub display freq. : 0.030000 MHz
•Mode : USB
•Receiving
•Sub display freq.
: 7.999999 MHz
•Mode : USB
•Receiving
•Sub display freq. : 19.999999 MHz
•Mode : USB
•Receiving
•Display frequency : 44.999999 MHz
•Mode : USB
•Receiving
•Display frequency : 60.000000 MHz
•Mode : USB
•Receiving
•Sub display freq. :
0.030000 MHz, 7.999999 MHz
8.000000 MHz, 19.999999 MHz
20.000000 MHz, 44.999999 MHz
45.000000 MHz, 60.000000 MHz
•Receiving
•Display frequency
: Any
•Receiving
•Display frequency : Any
•Receiving
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
Connect a frequency
counter to check
point P81.
Connect an RF volt-
meter to check point
P81.
Connect a digital
multimeter or oscillo-
scope to check point
LPA.
Connect a digital
multimeter or oscillo-
scope to check point
LVA.
Connect an RF volt-
meter to check point
P351.
Connect a digital
multimeter or oscillo-
scope to check point
LPB.
Connect a digital
multimeter or oscillo-
scope to check point
LVB.
Connect an RF volt-
meter to check point
P651.
Connect an RF volt-
meter to check point
P701.
Connect an RF volt-
meter to check point
P801.
64.000000 MHz
Maximum level
(0 dB or more)
2.0 V
4.3 V
4.3 V
4.3 V
4.3 V
0 dBm or more
2.0 V
4.3 V
4.3 V
4.3 V
4.3 V
0 dBm or more
–16 dBm or more
–7 dBm or more
PLL
PLL
PLL
PLL
PLL
L52 (R33
for critical
adjustment)
L81, L82
C154
C278
C258
C228
C208
Verify
C454
C578
C558
C528
C508
Verify
Verify
Verify

4 - 3
P81
Reference frequency
check point
L52
L81
C454
LPL-B lock voltage
adjustment
L82
Reference
frequency
adjustment
VCO-A
lock voltage
adjustment
VCO-B
lock voltage
adjustment
•PLL unit
Bottom view of the transceiver
PLL unit
LPB
LPL-B lock voltage
check point
C278
C228
C208
C258
C508
C558
C578
C528
P361
1LO-A output level
check point
R33
Reference
frequency
adjustment
LVA
VCO-A lock voltage
check point
P851
Marker output level
check point
LPA
LPL-A lock voltage
check point
C154
LPL-A lock voltage
adkustment
P801
3LO output level
check point
P651
1LO-B output level
check point
LVB
VCO-B lock voltage
check point
P901
S2LO output level
check point
P701
S3LO output level
check point
PLL ADJUSTMENTS—continued
S2LO
OUTPUT
LEVEL
MARKER
OUTPUT
LEVEL
ADJUSTMENT
ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT VALUE POINT
UNIT LOCATION UNIT ADJUST
1
1
•Display frequency : Any
•Receiving
•Display frequency : Any
•Receiving
PLL
PLL
Connect an RF volt-
meter to check point
P901.
Connect an oscillo-
scope to check point
P851.
0 dBm or more
4 Vp-p or more
Verify
Verify

*This output level of a standard signal generator (SSG) is indicated as SSG’s open circuit.
4 - 4
4-3 RECEIVER ADJUSTMENTS
RX PEAK
MIXER
BALANCE
FM
DISTORTION
ADJUSTMENT
ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT VALUE POINT
UNIT LOCATION UNIT ADJUST
1
2
3
1
2
1
2
•Display frequency: 14.100000 MHz
•Mode : USB
•Filter : 2.4 kHz
•[P.AMP] : P.AMP1
•[ATT] : OFF
•Connect an SSG to [ANT1] con-
nector and set as :
Frequency : 14.101500 MHz
Level : 10 µV* (–87 dBm)
Modulation: 1 kHz/±7.5 kHz dev.
•Receiving
•[DUAL WATCH] : ON
•Sub display freq. : 14.100000 MHz
•Mode : USB
•[BAL] : Max. CW
•Set an SSG as :
Level : 10 µV* (–87 dBm)
•Receiving
•Display frequency: 14.100000 MHz
•Mode : USB
•[DUAL WATCH] : OFF
•Set following selections, controls
and functions as :
Filter : 2.4 kHz, [ATT] : OFF
[AGC]: MID , [BAL] : Center
PBT1 : Center , PBT2 : Center
[NB] : OFF , [RIT] : OFF
[P.AMP] : P.AMP1
[RF/SQL] : Center
[ AUTO NOTCH ]: OFF
[ NOTCH ] : Center
[NR] switch : OFF
[NR] level : Max. CCW
[MONITOR] : OFF
•Connect an SSG to [ANT1] con-
nector and set as :
Frequency : 14.101500 MHz
Level : 1 µV* (–107 dBm)
Modulation: OFF
•Receiving
•Display frequency: 0.030000 MHz
•Sub display freq. : 0.030000 MHz
•Mode : USB
•[BAL] : Max. CCW
•Apply no no RF signal to [ANT1]
connector.
•Receiving
•[BAL] : Max. CW
•Receiving
•Display frequency: 14.100000 MHz
•Sub display freq. : 14.100000 MHz
•Mode : FM
•[BAL] : Max. CCW
•Connect an SSG to [ANT1] con-
nector and set as :
Frequency : 14.100000 MHz
Level : 500 µV* (–53 dBm)
Modulation:
1 kHz/±7.5 kHz Dev.
•Receiving
•[BAL] : Max. CW
•Receiving
Rear
panel
Rear
panel
Rear
panel
Connect an AC milli-
volt meter to [EXT
SP] connector with
an 8 Ωload.
Connect an AC milli-
volt meter to [EXT
SP] connector with
an 8 Ωload.
Connect an distortion
meter to [EXT SP]
connector with an
8 Ωload.
Maximum audio output
level
Minimum noise output
level
Minimum distortion
level
RF
MAIN
RF
RF
L513,
L721,
L722,
L943
L613
L111,
L112,
L113
R516
R616
C555
C655