Icom IC-F510 User manual

SERVICE
MANUAL
VHF TRANSCEIVER
iF510
iF520
iF521

VERSION
Europe
General
U.S.A.
U.S.A.
General
SYMBOL
EUR
GEN
USA
USA
GEN
INTRODUCTION
This service manual describes the latest service information
for the IC-F510,IC-F520 and IC-F521 VHF TRANSCEIVERS
at the time of publication.
DANGER
NEVER connect the transceiver to an AC outlet or to a DC
power supply that uses more than 16 V. This will ruin the
transceiver.
DO NOT expose the transceiver to rain, snow or any liquids.
DO NOT reverse the polarities of the power supply when con-
necting the transceiver.
DO NOT apply an RF signal of more than 20 dBm (100 mW)
to the antenna connector. This could damage the transceiv-
er’s front end.
ORDERING PARTS
Be sure to include the following four points when ordering
replacement parts:
1. 10-digit order numbers
2. Component part number and name
3. Equipment model name and unit name
4. Quantity required
<SAMPLE ORDER>
1110003490 S.IC TA31136FN IC-F510 MAIN UNIT 5 pieces
8810009990 Screw PH BT M3⋅8 ZK IC-F520 Bottom cover 10 pieces
Addresses are provided on the inside back cover for your
convenience.
REPAIR NOTES
1. Make sure a problem is internal before disassembling the
transceiver.
2. DO NOT open the transceiver until the transceiver is
disconnected from its power source.
3. DO NOT force any of the variable components. Turn
them slowly and smoothly.
4. DO NOT short any circuits or electronic parts. An insu-
lated tuning tool MUST be used for all adjustments.
5. DO NOT keep power ON for a long time when the trans-
ceiver is defective.
6. DO NOT transmit power into a signal generator or a
sweep generator.
7. ALWAYS connect a 50 dB to 60 dB attenuator between
the transceiver and a deviation meter or spectrum ana-
lyzer when using such test equipment.
8. READ the instructions of test equipment thoroughly
before connecting equipment to the transceiver.
MODEL
IC-F510
IC-F520
IC-F521
To upgrade quality, any electrical or mechanical parts and
internal circuits are subject to change without notice or
obligation.
Icom, Icom Inc. and are registered trademarks of Icom Incorporated (Japan) in the United States, the United Kingdom,
Germany, France, Spain, Russia and/or other countries.

TABLE OF CONTENTS
SECTION 1 SPECIFICATIONS
SECTION 2 INSIDE VIEW
SECTION 3 DISASSEMBLY INSTRUCTIONS
SECTION 4 CIRCUIT DESCRIPTION
4 - 1 RECEIVER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 1
4 - 2 TRANSMITTER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 2
4 - 3 PLL CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 3
4 - 4 POWER SUPPLY CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 4
4 - 5 OTHER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 - 5
4 - 6 PORT ALLOCATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 5
SECTION 5 ADJUSTMENT PROCEDURES
5 - 1 PREPARATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 1
5 - 2 PLL ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 4
5 - 3 SOFTWARE ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 5
SECTION 6 PARTS LIST
SECTION 7 MECHANICAL PARTS
SECTION 8 SEMI-CONDUCTOR INFORMATION
SECTION 9 BOARD LAYOUTS
9 - 1 FRONT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 1
9 - 2 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 3
SECTION 10 BLOCK DIAGRAM
SECTION 11 VOLTAGE DIAGRAMS
11 - 1 FRONT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 1
11 - 2 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 2
EXPLICIT DEFINITIONS
136 –174 MHz
FREQUENCY COVERAGE
12.5 kHz / 25.0 kHz
15.0 kHz / 30.0 kHz
12.5 kHz / 20.0 kHz
Narrow/Wide-type
Narrow/Middle-type
CHANNEL SPACING

S SECTION 1 SPECIFICATIONS
1 - 1
USA/GEN EUR
GENERAL
Measurement method EIA-152-C/204D or TIA-603 ETS 300 086
Frequency coverage 136.000–174.000 MHz
Type of emission
[N/W]: 8K50F3E/16K0F3E (15 kHz; Narrow/30 kHz; Wide) [USA]
[N/W]: 8K50F3E/16K0F3E (12.5 kHz; Narrow/25 kHz; Wide) [GEN], [EUR]
[N/M]: 8K50F3E/14K0F3E (12.5 kHz; Narrow/20 kHz; Middle) [EUR]
Number of conventional channels Max. 256 ch (16 channels × 16 banks)
Power supply voltage (negative ground) 13.6 V DC nominal 13.2 V DC nominal
Current drain (approx.)
Frequency error 5.0 ppm ±1.5 kHz
Usable temperature range –30ºC to +60ºC (–22ºF to +140ºF) –25ºC to +55ºC
Dimensions (proj. not included) 140(W) ×40(H) ×170(D) mm; 51⁄2(W) ×19⁄16(H) ×611⁄16(D)
Weight 1.2 kg; 2 lb 10 oz
TRANSMITTER
RF output power High/Low2/Low1: 25 W/10 W/2.5 W [25W], 50 W/25 W/5 W [50W]
Modulation system Variable reactance frequency modulation
Maximum permissible deviation ±2.5 kHz [Narrow], ±4.0 kHz [Middle], ±5.0 kHz [Wide]
Spurious emissions 70 dB typical 0.25 µW≤ 1 GHz, 1.0 µW>1 GHz
Adjacent channel power 60 dB [Narrow], 70 dB [Middle]/[Wide]
Audio frequency response +2 dB to –5 dB of 6 dB/octarve
range from 300 Hz to 2550 Hz [Narrow]/3000 Hz [Middle]/[Wide]
Audio harmonic distortion 3% typical at 1 kHz, 40% deviation
FM hum and noise (typical)
(without CCITT filter) 40 dB [Narrow], 46 dB [Wide] –––
Residual modulation (typical)
(with CCITT filter) ––– 50 dB [Narrow], 53 dB [Middle], 55 dB [Wide]
Limiting charact of modulator 70–100% of max. deviation
Microphone connector 8-pin modular (600Ω)
RECEIVER
Receive system Double-conversion superheterodyne system
Intermediate frequencies 1st: 46.35 MHz, 2nd: 450 kHz
Sensitivity (typical) 0.25 µV at 12 dB SINAD –4 dBµV (emf) at 20 dB SINAD
Squelch sensitivity (typical) 0.25 µV –4 dBµV (emf)
Adjacent channel selectivity (typical) 65 dB [Narrow], 75 dB [Middle/Wide]
Spurious response 75 dB
Intermodulation (typical) 74 dB 67 dB
Hum and noise
(typical)
(without CCITT filter) 40 dB [Narrow], 45 dB [Wide] –––
(with CCITT filter) ––– 50 dB [Narrow], 53 dB [Middle], 55 dB [Wide]
Audio output power 4 W typical at 10% distortion with a 4 Ωload
External SP connector 2-conductor 3.5 (d) mm (1/8")/4 Ω
All stated specifications are subject to change without notice or obligation.
RECEIVING TRANSMITTING
Stand-by Max. audio 50 W 25 W
300 mA 1200 mA 14.0 A 7.0 A

SECTION 2 INSIDE VIEW
2 - 1
Power module
8V regurator
(IC9: TA7808F)
AF power amplifier
(IC8: LA4425A)
CPU 5V regurator*
(IC10: AN78L05M)
VCO circuit
CPU*
(IC20: HD64F2268TF)
Antenna switch/
Low-pass filter circuits
1st mixer*
(Q3: 3SK272)
2nd IF filter
(FI2: ALFYM450F=K [N/W]
CFWLB450KGFA
-B0 [N/M])
FM IF IC
(IC1: TA31136FN)
D/A converter
(IC6: M62364FP)
Referance crystal osillator
(X2: CR-664A 15.3 MHz)
PLL IC
(IC4: TB31256FL)
*Located under side of the point.
1st IF filter
(FI1: FL-335 46.35 MHz)
IC3: RA30H1317M-21 [25W]
RA60H1317M-21 [50W]

SECTION 3 DISASSEMBLY INSTRUCTIONS
3 - 1
• Removing the front unit
➀Unscrew 4 screws A, and remove the bottom cover.
➁Disconnect the flat cable Bfrom J2.
➂Unscrew 2 screws c, and remove the front unit.
A
A
B
C
C
J2
•Removing the main unit
➀Unsolder 3 points Dfrom the antenna connector.
➁Remove the clip E.
➂Disconnect the cable Ffrom J5.
➃Unscrew 11 screws G.
G
G
G
F
E
J5
D
➄Lift up the front part of the main unit and remove it.
•Optional unit and cable instllation location
UT-105 SmarTrankII. Logic Board
UT-108 DTMF decoder unit
UT-109 Voice scrambler unit (non-rolling type)
UT-110 Voice scrambler unit (rolling type)
UT-111 Trunking unit
OPC-617 ACC cable
OPC-822 Interface cable
OPC-617
OPC-822
UT-105, UT-108
UT-109, UT-110
UT-111
J1 J6
J9
Continue to right above

4 - 1
4-1 RECEIVER CIRCUITS
4-1-1 ANTENNA SWITCHING CIRCUIT (MAIN UNIT)
The antenna switching circuit functions as a low-pass filter
while receiving and as resonator circuit while transmitting.
The circuit does not allow transmit signals to enter receiver
circuits.
Received signals from the antenna connector (CHASSIS;
J1) are passed through the low-pass filter (L1–L3, C1, C2,
C6–C8, C526), and are then applied to the λ⁄4type antenna
switching circuit (D2, D3, D5).
While receiving, no voltage is applied to D2, D3 and D5.
Thus, the receive line and the ground are disconnected and
received signals are applied to the RF circuits.
4-1-2 RF CIRCUIT (MAIN UNIT)
The RF circuit amplifies signals within the range of frequen-
cy coverage and filters out-of-band signals.
The signals from the antenna switching circuit pass through
the two-stage tunable bandpass filters (D4, D8). The filtered
signals are amplified at the RF amplifier (Q2) and then
passed through another two-stage bandpass filters (D9,
D10) to suppress unwanted signals. The filtered signals are
applied to the 1st mixer circuit (Q3).
The tunable bandpass filters (D4, D8–D10) employ varactor
diodes to tune the center frequency of the RF passband for
wide bandwidth receiving and good image response rejec-
tion. These diodes are controlled by the CPU (IC20) via the
D/A converter (IC7, pins 1–4).
SECTION 4 CIRCUIT DESCRIPTION
4-1-3 1ST MIXER AND 1ST IF CIRCUITS
(MAIN UNIT)
The 1st mixer circuit converts the received signals to a fixed
frequency of the 1st IF signal with the PLL output frequency.
By changing the PLL frequency, only the desired frequency
will pass through a MCF (Monolithic Crystal Filter; FI1) at
the next stage of the 1st mixer.
The RF signals from the bandpass filter are applied to the
1st mixer circuit (Q3). The applied signals are mixed with
the 1st LO signal coming from the RX VCO circuit (Q13) to
produce a 46.35 MHz 1st IF signal. The 1st IF signal passes
through a MCF (FI1) to suppress out-of-band signals. The
filtered signal is amplified at the 1st IF amplifier (Q4) and is
then applied to the 2nd IF circuit.
4-1-4 2ND IF AND DEMODULATOR CIRCUITS
(MAIN UNIT)
The 2nd mixer circuit converts the 1st IF signal to a 2nd IF
signal. A double-conversion superheterodyne system im-
proves the image rejection ratio and obtains stable receiver
gain.
The 1st IF signal from the 1st IF amplifier (Q4) is applied
to the 2nd mixer section of the FM IF IC (IC1, pin 16) and
is then mixed with the 2nd LO signal to be converted into a
450 kHz 2nd IF signal.
The FM IF IC (IC1) contains the 2nd mixer, limiter amplifier,
quadrature detector, active filter and noise amplifier etc.
A 2nd LO signal (45.9 MHz) is produced at PLL circuit by
tripling it's reference frequency (15.3 MHz).
FI2
2nd IF filter
450 kHz
Noise
detector
Q34
Limiter
amp.
Quadrature
detector
Active
filter
AF signals
5V
X1 Discriminator
IC6
Mixer
X2
15.3 MHz
45.9 MHz
1st IF from the IF amplifier (Q4)
NOIS signal to the CPU (IC20)
8
24
23
75
BPF
32
3
161311109
IC1
TA31136FN
Noise
amp.
Noise
comparator
• 2ND IF DEMODULATOR CIRCUIT

4 - 2
The 2nd IF signal from the 2nd mixer section (IC1, pin 3)
passes through a ceramic filter (FI2) to remove unwanted
heterodyned frequencies. It is then amplified at the limiter
amplifier section (IC1, pin 5) and applied to the quadrature
detector section (IC1, pins 10, 11) to demodulate the AF sig-
nals.
The AF signals are output from pin 9 (IC1) and are then ap-
plied to the AF amplifier circuit.
4-1-5 AF AMPLIFIER CIRCUIT (MAIN UNIT)
The AF amplifier circuit amplifies the demodulated AF sig-
nals to drive a speaker.
The AF signals from the FM IF IC (IC1, pin 9) are passed
through the high-pass filter (IC21, pins 5, 7) and then applied
to the de-emphasis section of the compander IC (IC14, pin 3)
with frequency characteristics of –6 dB/octave. The signals
are passed through the low-pass filter, high-pass filter, ex-
pander sections in the compander IC (IC14). The signal out-
put from pin 38 (IC14) and then applied to the D/A converter
(IC6, pins 1, 2).
The output AF signals from the D/A converter (IC6, pin 2) are
applied to the AF amplifier (IC18, pins 3, 4) and AF power
amplifier (IC8, pins 1, 4).
The power amplified AF signals are applied to the internal
speaker that is connected to J5 via [EXT SP] jack (J4).
4-1-6 RECEIVER MUTE CIRCUITS (MAIN UNIT)
• NOISE SQUELCH
The noise squelch circuit cuts out AF signals when no RF
signals are received. By detecting noise components in the
AF signals, the squelch circuit switches the AF mute switch.
Some noise components in the AF signals from the FM IF IC
(IC1, pin 9) are passed through the D/A converter (IC6, pins
23, 24). The signals are applied to the active filter section in
the FM IF IC (IC1, pin 8). The active filter section filters and
amplifies noise components only. The amplified noise signals
are converted into the pulse-type signals at the noise detec-
tor section. The detected signals output from pin 13 (NOIS)
via the noise comparator section.
The NOIS signal from the FM IF IC (IC1, pin 13) is applied
to the CPU (IC20, pin 37). Then the CPU analyzes the noise
condition and outputs the AF mute signal as “AFON” from
the pin 18 to the AF power controller (Q39, Q40, D31, D35).
• CTCSS AND DTCS
The tone squelch circuit detects AF signals and opens the
squelch only when receiving a signal containing a matching
subaudible tone (CTCSS or DTCS). When tone squelch is in
use, and a signal with a mismatched or no subaudible tone is
received, the tone squelch circuit mutes the AF signals even
when the noise squelch is open.
A portion of the AF signals from the FM IF IC (IC1, pin 9)
passes through the low-pass filters (IC5 pins, 1, 2, 5, 7) to
remove AF (voice) signals and is applied to the CTCSS or
DTCS decoder inside the CPU (IC20, pin 46) as the “CDEC”
signals. The CPU outputs the AF mute signal as "AFON"
from the pin 18 to the AF power controller (Q39, Q40, D31,
D35).
Compander IC
(IC14)
AF signal
from FM IF IC (IC1, pin 9) 338 AF
AMP
IC8
Speaker
IC2
IC15
IC21 IC6 D18
Microphone
AMP
12
6
21
PM/FM switch
D/A
converter FM mod.
LPF
"CTCSS/DTCS" signal from
D/A conveter IC (IC6, pin 11)
"TONE" signal from Q38
to TX VCO circuit
(Q14, D17, D53–55)
22
AMP
IC18
FRONT UNIT
2
9
10
341 4
IC6
1
3
4
IC6
D/A
converter
D/A
converter
• AF AND MIC AMPLIFIER CIRCUIT

4 - 3
4-2 TRANSMITTER CIRCUITS
4-2-1 MICROPHONE AMPLIFIER CIRCUIT
(MAIN UNIT)
The microphone amplifier circuit amplifies audio signals
within +6 dB/octave pre-emphasis characteristics from the
microphone to a level needed for the modulation circuit.
The AF signals (MIC) from the microphone (FRONT unit; J1,
pin 6) are applied to the microphone amplifier (FRONT unit;
IC2, pins 3, 4) and then applied to the MAIN unit via J2 (pin 1).
The amplified signals are passed through the D/A converter
(IC6, pins 9, 10) and are then applied to the microphone
amplifier section of the compander IC (IC14, pin 12). The
amplified signals are passed through the compressor, low-
pass filter and high-pass filter sections and output from pin 9
(IC14).
The filtered AF signals are amplified at the buffer amplifier
(Q21) and pre-emphasized with +6dB/octave at the pre-
emphasis circuit (R122, C187), and are then applied to the
IDC amplifier section in IC14 (pin 8).
The amplified AF signals are passed through the limitter
amplifier, low-pass filter, smoothing filter sections after being
passed through the AF mute switch and is then output from
pin 7 (IC14).
The output signals from (IC14) are passed through the PM/
FM switch (IC15, pins 1, 6, 7), splatter filter (IC21, pins 12,
14) and are then applied to the D/A converter (IC6, pins 21,
22). The signals are applied to modulation circuit.
4-2-2 MODULATION CIRCUIT (MAIN UNIT)
The modulation circuit modulates the VCO oscillating signal
(RF signal) using the microphone audio signals.
The AF signals from the D/A converter (IC6, pin 22) change
the reactance of varactor diode (D18) to modulate the oscil-
lated signal at the TX VCO circuit (Q14, D17, D53–D55). The
modulated VCO signal is amplified at the buffer amplifiers
(Q10, Q11) and is then applied to the drive amplifier circuit
via the T/R switch (D14).
The CTCSS/DTCS signals ("CENC0," "CENC1," "CENC2")
from the CPU (IC20, pins 89–91) are combined at resistors
(R267–R269) and are then passed through the low-pass fil-
ter (Q37), D/A converter (IC6, pins 11, 12) and mixer (IC21,
pins 1, 2). The signals are mixed with the AF signals from
the PM/FM switch (IC15, pin 1) and are then applied to D18
in the VCO circuit via the splatter filter (IC21, pins 12, 14).
4-2-3 DRIVE AMPLIFIER CIRCUIT (MAIN UNIT)
The drive amplifier circuit amplifies the VCO oscillating signal
to the level needed at the power amplifier.
The RF signal from the buffer amplifier (Q10) passes through
the T/R switch (D14) and is amplified at the YGR (Q9) and
drive (Q8) amplifiers. The amplified signal is applied to the
power amplifier circuit.
4-2-4 POWER AMPLIFIER CIRCUIT (MAIN UNIT)
The power amplifier circuit amplifies the driver signals to an
output power level.
The RF signal from the drive amplifier (Q8) is applied to the
power module (IC3) to obtain 25 W (for IC-F510/F520, 50
W; for IC-F521) of RF power after pass through the low-pass
filter (L18, C89, C90) and attenuator (D72).
The amplified signal is passed through the low-pass fil-
ter (L15, C387, C388), antenna switching circuit (D2, D3),
low-pass filter (L2, L3, C6–C8) and power detector (D1,
D11), low-pass filter (L1, C1, C2) and is then applied to the
antenna connector (CHASSIS; J1).
Control voltage for the power amplifier (IC3, pin 3) comes
from the APC amplifier (IC2, pin 4) to stabilize the output
power. The transmit mute switch (D32) controls the APC am-
plifier when transmit mute is necessary.
4-2-5 APC CIRCUIT (MAIN UNIT)
The APC circuit protects the power amplifier from a mis-
matched output load and stabilizes the output power.
The power detector circuit (D1, D11) detects forward sig-
nals and reflection signals and converts it into DC voltage.
The detected voltage is at minimum level when the antenna
impedance is matched at 50 Ω, and is increased when it is
mismatched.
The detected voltage is applied to the APC amplifier (IC2,
pin 3), and the power setting “T4” signal from the D/A con-
verter (IC7, pin 4), controlled by the CPU (IC20), is applied to
the another input for reference. When antenna impedance is
mismatched, the detected voltage exceeds the power setting
voltage. Then the output voltage of the APC amplifier (IC2,
pin 4) controls the input voltage of the pre-drive amplifier (Q8),
attenuator (D72), power module (IC3) to reduce the output
power.
POWER
AMP.
ATTE-
NUATOR
APC
AMP.
DRIVE
AMP.
+
–
VCC
to antenna
connector
T4
TMUT
RF signal
from PLL circuit
T8V
APC control circuit
D1
D11
FOR
REV
Q8 D72
Q9
IC2
IC3
YGR
AMP.
• APC CIRCUIT

4-3 PLL CIRCUITS
4-3-1 PLL CIRCUIT
A PLL circuit provides stable oscillation of the transmit fre-
quency and receive 1st LO frequency. The PLL output com-
pares the phase of the divided VCO frequency to the refer-
ence frequency. The PLL output frequency is controlled by
the divided ratio (N-data) of a programmable divider.
The PLL circuit contains the RX VCO (Q13, D16, D50–D52)
and TX VCO (Q14, D17, D53–D55). The oscillated signal is
amplified at the buffer amplifiers (Q11, Q12) and then ap-
plied to the PLL IC (IC4, pin 17) via the low-pass filter (L32,
C298, C299, C509).
The PLL IC (IC4) contains a prescaler, programmable coun-
ter, programmable divider and phase detector, etc. The ap-
plied signal is divided at the prescaler and programmable
counter section by the N-data ratio from the CPU (IC20). The
reference signal is generated at the reference oscillator (X2)
and is applied to the PLL IC. The PLL IC detects the out-of-
step phase using the reference frequency and outputs it from
pin 13. The output signal is passed thorough the charge
pump (Q50, Q51, Q54, Q55) and loop filter (Q52, Q53), and
is then applied to the VCO circuit as the lock voltage.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.
4-3-2 VCO CIRCUIT
The VCO circuit contains a separate RX VCO (Q13, D16,
D50–D52) and TX VCO (Q14, D17, D53–D55). The oscil-
lated signal is amplified at the buffer amplifiers (Q10, Q11)
and is then applied to the T/R switch circuit (D14, D15). Then
the receive 1st LO (Rx) signal is applied to the 1st mixer (Q3)
and the transmit (Tx) signal to the YGR amplifier circuit (Q9).
A portion of the signal from the buffer amplifier (Q11) is fed
back to the PLL IC (IC4, pin 17) via the buffer amplifier (Q12)
and low-pass filter (L32, C298, C299, C509) as the compari-
son signal.
Controller
×3
Prescaler
Phase
detector
Loop
filter
Programable
counter
Programable
divider
X2
15.3 MHz
45.9 MHz signal
to the FM IF IC 10
Q13, D16
RX VCO
TX VCO
Buffer
Buffer
Buffer
Q10
Q12
Q11
Q34
20
19
21
22
FSW2
IC4 (PLL IC)
SO
SCK
to transmitter circuit
to 1st mixer circuit
D15
D14
13 17
Q14, D17
LPF
• PLL CIRCUIT
4 - 4
4-4 POWER SUPPLY CIRCUITS
LINE DESCRIPTION
HV The voltage from a DC power supply.
VCC
The same voltage as the HV line which is
controlled by the power switching circuit
(Q23, Q24). When the [ ] switch is pushed,
the CPU outputs the "PWR" control signal to
the power switching circuit to turn the circuit
ON.
CPU5V
Common 5 V converted from the HV line
at the CPU5V regulator circuit (IC10). The
output voltage is applied to the CPU (IC20),
EEPROM (IC23), etc.
5V
Common 5 V converted from the VCC line at
the 5 V regulator circuit (Q27, Q28). The out-
put voltage is applied to the FM IF IC (IC1),
PLL IC (IC4), etc.
8V
Common 8 V converted from the VCC line
at the 8 V regulator circuit (IC9). The out-
put voltage is applied to the buffer amplifier
(Q11), AF amplifier (IC16), etc.
T8V
Transmit 8 V controlled by the T8V regulator
circuit (Q25, Q29, D23) using the "TMUT"
signal from the CPU (IC20, pin 17). The out-
put voltage is applied to the YGR amplifier
(Q9), driver amplifier (Q10), etc.
R8V
Receive 8 V controlled by the R8V regulator
circuit (Q26, Q30, D24) using the "TXC" sig-
nal from the CPU (IC20, pin 16). The output
voltage is applied to the RF amplifier (Q2),
1st IF amplifier (Q4), etc.

4 - 5
4-5 OTHER CIRCUITS
4-5-1 COMPANDER CIRCUIT (MAIN UNIT)
IC-F510 series have compander circuit which can improve
S/N ratio and become wide dynamic range. The circuit is
composed in the compander IC (IC14).
(1) IN CASE OF RECEIVING
The demodulated AF signals from the FM IF IC (IC1, pin
9) are applied to the amplifier section in the compander IC
(IC14, pin 3), and then pass through the low-pass filter and
high-pass filter sections to suppress unwanted signals. The
filtered signals are applied to the expander circuit to expand
AF signals.
The output signals from the compander IC (IC14, pin 38)
is applied to the AF amplifier circuit after amplified at the
amplifier section.
(2) IN CASE OF TRANSMITTING
The audio signals from the microphone amplifer (FRONT
UNIT; IC2) are applied to the compander IC (IC14, pin 12)
via the D/A converter (IC6, pins 9, 10). The signals are
amplified at the amplifier section, and are then applied to
the compressor circuit to compress the audio signals. The
signals are pass through the low-pass filter and high-pass
filter sections and are then applied to the limiter amplifer
section after being passed through the high-pass filter
section.
The filtered signals pass through the splatter filter section,
and are then applied to the modulation circuit (D18) via the
PM/FM switch (IC15, pins1, 6, 7) and D/A converter (IC6,
pins 21, 22).
• COMPANDER IC BLOCK DIAGRAM
4-6 PORT ALLOCATIONS
4-6-1 OUTPUT EXPANDER (FRONT UNIT; IC1)
Pin
number
Port
name Description
1–3 KS0–
KS2
Output ports for the programmable
function keys (P0–P4, , , , ).
4, 5 DIM1,
DIM2
Output LCD backlight control signals.
7 HORN
Outputs external device control signal.
High: When matched 2/5 tone sig-
nals are received.
DIM1 DIM2 LIGHT
HIGH HIGH ON
HIGH LOW OFF
LOW HIGH DIM
LOW LOW OFF
4-6-2 D/A CONVERTER (MAIN UNIT; IC7)
Pin
number
Port
name Description
1–3 T1–T3 Output the bandpass filters (D4, D8,
D9) tuning signals.
4T4
• Outputs the bandpass filter (D10)
tuning signal while receiving.
• Outputs the TX power control
signal which selects High, Low1,
Low2 of TX power while trans-
mitting. The output signal is ap-
plied to the APC amplifier (IC2,
pin 1).
EXPANDER
DEMOD
MSK
AMP LPF
LPF
HPF AMP AMP
LPF
TX OUT
RX OUT
LIMIT
AMP
AMP
HPF
HPF
AMP
BPF MOD
MSK
COM-
PRESSOR
3
TX IN
MSK IN
RX IN
5
12 6
38

4 - 6
4-6-3 CPU (MAIN UNIT; IC2)
Pin
number
Port
name Description
1 DSDA I/O port for data signal to the D/A con-
verter (IC7).
2 DAST Outputs strobe signals to the D/A con-
verter (IC6).
8, 9 LINH,
LCS
Output LCD control signals to the
LCD driver (FRONT unit; IC1).
10 LSCK Outputs clock signal to the LCD driver
(FRONT unit; IC1).
11 LSO Outputs data signal to the LCD driver
(FRONT unit; IC1).
13 PLST Outputs strobe signal to the PLL IC
(IC4).
16 TXC
Outputs the R8 regulator circuit (Q26,
Q30, D24) control signal.
Low: During receive.
17 TMUT
Outputs the T8 regulator circuit (Q25,
Q29, D23) control signal.
Low: During transmit.
18 AFON
Outputs control signal for AF mute cir-
cuit (Q39, Q40, D31).
High: While AF amplifier (IC8) is
activated.
19 NWC
Outputs IF band width control signal.
High: While IF bandwidth is nar-
row.
20 DDSD Input port for data signal from the
DTMF decoder IC (IC19, pin 9).
21 DDAC Outputs clock signal to the DTMF de-
coder IC (IC19, pin 10).
22 SO
Outputs data signal to the PLL IC
(IC4), D/A converter (IC6), compand-
er IC (IC14) and optional unit (connect
to J1), etc.
23 SI Input port for clock signal from the op-
tional unit via J1.
24 SCK
Outputs clock signal to the PLL IC
(IC4), D/A converter (IC6), D/A con-
verter (IC7), compander IC (IC14) and
optional unit (connect to J1), etc.
25 CCS Outputs chip select signal for the op-
tional unit via J1.
26–28 KR0–
KR2
Input ports for the programmable
function keys (P0–P4, , , , ).
29 PTTO
Input ports for the PTT switch from
the optional unit via J1.
Low: External PTT switch is ON.
30 HANG
Input port for the microphone hanger
detection signal.
Low: When microphone is on the
hook.
31 BUSY Outputs BUSY detection signal for the
optional unit via J1.
32 RMUT
Input port for the AF mute signal from
the optional unit via J1.
Low: While RX audio is muted.
Pin
number
Port
name Description
33 MMUT
Input port for the microphone mute
signal from the optional unit via J1.
Low: The microphone audio is
muted.
34–36 OPT1–
OPT3 I/O ports for the optional unit.
37 NOIS Input port for the noise signal from the
FM IF IC (IC1, pin 13).
38 POSW Input port for the [ ] switch.
Low: The [ ] switch is pushed.
39 DDST Input port for DTMF detection signal
from the DTMF decoder IC (IC19).
40 IGSW
Input port for the remote power con-
trol signal from external connector
(J8).
41 PWON
Outputs control signal for the power
switch circuit (Q23, Q24) via D28.
High: While power ON.
43 SENC Output single tone signal.
44 BEEP Outputs beep audio signal.
45 SDEC Input port for single tone signal from
the LPF (IC21, pin 8).
46 CDEC Input port for CTCSS/DTCS signal
from the LPF (IC5, pin 1).
47 ULCK
Input port for the PLL unlock signal
from the PLL IC (IC4).
Low: The PLL circuit is unlocked.
48 BATV Input port for the connected battery
for the low battery detection.
49 LVIN Input port for the PLL lock voltage.
50 RSSI Input port for the S-meter signal from
the FM IF IC (IC1, pin 12).
51 TEMP Input port for the transceiver’s internal
temperature detecting signal.
52 AFVI
Input port for the AF volume control
(FRONT unit; R12).
High: [AF VOLUME] is maximum
clockwise.
55 EPTT
Input port for the PTT switch from the
external connector (J6).
Low: External PTT switch is ON.
59 RES Input port for the reset signal.
68 CLO Outputs the cloning signal.
69 CLI Input port for the cloning signal.
71 DUSE
Outputs cut-off frequency control
signal to the low-pass filter (IC5) for
CTCSS/DTCS switch.
74 XCTS Input port for the connected modem
unit via external connector (J9).
75 XRTS Output port for the connected modem
unit via external connector (J9).

4 - 7
Pin
number
Port
name Description
76 XTXD
Input port for the MAP27 data signals
from the connected unit via the exter-
nal connector (J9).
77 XRXD
Outputs the MAP27 data signals for
the connected unit via the external
connector (J9).
79 NTXD
Outputs the NMEA data signals for
the connected unit via external con-
nector (J8).
80 NRXD
Input port for the NMEA data signals
from the connected unit via external
connector (J8).
88 DIM
Input port for the LCD backlight con-
trol signal from the external connector
(J6).
Low: While LCD backlight is
dimmed.
89–91 CENC1–
CENC3 Output the CTCSS/DTCS signals.
92 AFCL Outputs reset signal for the compand-
er IC (IC14).
96 APST Outputs strobe signal to the com-
pander IC (IC14).
97 PMFM
Outputs the control signal for the MSK
PM/FM switch circuit (IC15).
Low: While PM is selected.
98 ESDA I/O port for data signals from/to the
EEPROM (IC23).
99 ESCL Outputs clock signal to the EEPROM
(IC23).

MREQUIRED TEST EQUIPMENT
EQUIPMENT GRADE AND RANGE EQUIPMENT GRADE AND RANGE
DC power supply Output voltage : 13.6 (13.2) V DC
Current capacity : 20 A or more Audio generator Frequency range : 300–3000 Hz Measuring range : 1–500 mV
FM deviation meter Frequency range : DC–600 MHz
Measuring range : 0 to ±10 kHz Attenuator Power attenuation : 50 or 60 dB Capacity : 100 W
Frequency counter
Frequency range : 0.1–600 MHz
Frequency accuracy : ±1 ppm or better
Sensitivity : 100 mV or better
Standard signal
generator (SSG)
Frequency range : 0.1–600 MHz
Output level : 0.1 µV to 32 mV
(–127 to –17 dBm)
Digital multimeter Input impedance : 10 MΩ/V DC or more AC millivoltmeter Measuring range : 10 mV to 10 V
RF power meter
Measuring range : 1–75 W
Frequency range : 100–800 MHz
Impedance : 50 Ω
SWR : Better than 1.2 : 1
Oscilloscope Frequency rang : DC–20 MHz
Measuring range : 0.01–20 V
External speaker Input impedance : 4 Ω
Capacity : 7 W or more
SECTION 5 ADJUSTMENT PROCEDURES
5 - 1
5-1 PREPARATION
When adjusting IC-F510, IC-F520 or IC-F521, the optional CS-F500 ADJ ADJUSTMENT SOFTWARE (Rev. 2.0 or later)* and the
OPC-1122* JIG CABLE (modified OPC1122 CLONING CABLE; see illustration page 5-3) are required.
*The CS-F500 ADJ (Rev. 2.0 or later) are requied for BIIS version.
SYSTEM REQUIREMENTS
• Microsoft®Windows®95/98/Me
• RS-232C serial port (D-sub 9 pin)
ADJUSTMENT SOFTWARE INSTALLATION
qQuit all applications when Windows is running.
wInsert the CD into the appropriate CD drive.
eDouble-click the “Setup.exe” contained in the ‘CS-F500
ADJ’ folder in the CD drive.
rThe “Welcome to the InstallShield Wizard for CS-F500
ADJ” will appear. Click [Next>].
tThe “Choose Destination Location” will appear. Then click
[Next>] to install the software to the destination folder. (e.g.
C:\Program Files\Icom\CS-F500 ADJ)
y
After the installation is completed, the “InstallShield Wiz-
ard Complete” will appear. Then click [Finish].
uEject the CD.
iProgram group ‘CS-F500 ADJ’ appears in the ‘Programs’
folder of the start menu, and ‘CS-F500 ADJ’ icon appears
on the desk top screen.
BEFORE STARTING SOFTWARE ADJUSTMENT
Program the adjustment frequencies into the transceiver
using with the CS-F500 before starting the software adjust-
ment. Otherwise, the transceiver can not start software ad-
justment.
CAUTION!: BACK UP the originally programmed mem-
ory data in the transceiver before program-
ming the adjustment frequencies.
When program the adjustment frequencies into
the transceiver, the transceiver’s memory data
will be overwritten and lose original memory
data at the same time.
STARTING SOFTWARE ADJUSTMENT
qConnect the transceiver and PC with the OPC-1122*.
wTurn the transceiver power ON.
eBoot up Windows, and click the program group ‘CS-F500
ADJ’ in the ‘Programs’ folder of the [Start] menu, then
CS-F500 ADJ’s window appears.
rClick ‘Connect’ on the CS-F500 ADJ’s window, then ap-
pears the transceiver’s adjustment screen.
tSet or modify adjustment data as desired.
• ADJUSTMENT FREQUENCY LIST
CH FREQUENCY CONDITION
1 155.000 MHz TX power
Mode
: Low1
: Wide
2 155.000 MHz TX power
Mode
: Low2
: Wide
3 155.000 MHz TX power
Mode
: High
: Wide
4 155.000 MHz TX power
Mode
: Low1
: Narrow
5 155.000 MHz
TX power
Mode
CTCSS
DTCS code
: Low1
: Wide
: 88.5 Hz
: 007
6 174.000 MHz TX power
Mode
: Low1
: Wide
7 174.000 MHz TX power
Mode
: Low1
: Narrow
8 136.000 MHz TX power
Mode
: Low1
: Wide
Microsoft and Windows are registered trademarks of
Microsoft Corporation in the U.S.A. and other countries.

5 - 2
CS-F500 ADJ Rev.2.0
File
COM 1: OPEN
Option
Connect Reload (F5) Disp para
[A / D]
VIN : 156 : 9Ch : 12.24 V
TEMPS : 187 : BBh : 30.81 'C
LVIN : 57 : 32h : 0.98 V
SD : 36 : 24h : 0.71 V
Power (Hi) : 181 [ # # # # # # # # # # # # # # – – – – – – ]
Power (L2) : 120 [ # # # # # # # # # – – – – – – – – – – – ]
Power (L1) : 69 [ # # # # # – – – – – – – – – – – – – – – ]
Ballance : 54 [ # # # # – – – – – – – – – – – – – – – – ]
MOD W : 157 [ # # # # # # # # # # # # – – – – – – – – ]
MOD N : 83 [ # # # # # # # – – – – – – – – – – – – – ]
CTCS/DTCS : 67 [ # # # # # – – – – – – – – – – – – – – – ]
SQL : 0 [ – – – – – – – – – – – – – – – – – – – – ]
BPF ALL : [Enter] to sweep
BPF T1 : 0 [ # # # # # # # # # – – – – – – – – – – – ] [Enter] to sweep
BPF T2 : 0 [ # # # # # # # # # – – – – – – – – – – – ] [Enter] to sweep
BPF T3 : 0 [ # # # # # # # # # – – – – – – – – – – – ] [Enter] to sweep
BPF T4 : 0 [ # # # # # # # # # – – – – – – – – – – – ] [Enter] to sweep
TXF : [Enter] to start
S-METER : [Enter] to start
[D / A]
BPF T1 : 50 : 32h : 0.98 V
BPF T2 : 50 : 32h : 0.98 V
BPF T3 : 50 : 32h : 0.98 V
T4/POW : 50 : 32h : 0.98 V
REF : 45 : 2Dh : 0.88 V
MOD BAL : 54 : 36h : 21.18 %
Dev : 157 : 9Dh : 3.08 V
CTCSS : 66 : 42h : 1.29 V
SQL Lev : 0 : 00h : 0.00 %
CH No. : 01 RX Freq = 440.050, TX Freq = <– RF Power: High Mode: Wide
: Transceiver's connection state
: Reload adjustment data
:
Receive sensitivity measurement
: Connected DC voltage
NOTE:
1
5
4
6
10
11
12
15
9
14
1
2
3
4
9
10
: PLL lock voltage
:
Operating channel select
: RF output power
: Modulation balance
5
6
7
8
11
12
: FM deviation
:
CTCSS/DTCS deviation
: Squelch level
: Receive sensitivity
(automatically)
13 :
Receive sensitivity (manually)
: Reference frequency
: S-meter
14
15
The above values for settings are example only.
Each transceiver has its own specific values for each setting.
3
2
8
7
13
• CS-F500 ADJ'S SCREEN EXAMPLE

FM deviation meter
(DC measurable)
Attenuator
50 dB or 60 dB
to the MIC
connector
to the antenna connector
to DC cable
IC-F510 series
to an RS-232C port
DB9 female plug
Personal
computer
Standard signal generator
–127 to –17 dBm
(0.1 V to 32 mV)
CAUTION:
DO NOT transmit while
SSG is connected to
the antenna connector.
RF power meter
50Ω/ 1–75 W
DC power supply
13.6 (13.2) V / 20 A
Frequency
counter
RS-232C cable
(straight)
OPC-1122*
(JIG CABLE) AC millivoltmeter
Audio generator
+Audio generator
300 Hz to 3 kHz
AC
millivoltmeter
MICE
MIC
PTT
PTT switch
PTTE
Add a jumper wire here
• OPC-1122* (JIG CABLE)
Electrolytic
capacitor
47 µF
OPC-1122
(Cloning cable)
5 - 3
• CONNECTION
• JIG CABLE

5 - 4
5-2 PLL ADJUSTMENT
ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT VALUE ADJUSTMENT
UNIT LOCATION UNIT ADJUST
PLL LOCK
VOLTAGE
1 • Operating CH
• Receiving
: CH8 MAIN Connect a digital
multimeter or an oscil-
loscope to the check
point, "LV".
1.4 V MAIN C133
2 • Transmitting 1.0 V C134
3 • Operating CH
• Receiving
: CH6 3.5–4.5 V Verify
4 • Transmitting 3.0–4.0 V
LV
PLL lock voltage
check point
C134
PLL lock voltage
adjustment for TX
C133
PLL lock voltage
adjustment for RX
DC power supply
13.6 (13.2) V / 20 A

5 - 5
ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT VALUE
UNIT LOCATION
REFERENCE
FREQUENCY
[TXF]
1 • Operating CH : CH6 Rear
panel
Loosely couple a frequency
counter to the antenna con-
nector.
174.0000 MHz
• Connect an RF power meter or 50 Ω
dummy load to the antenna connector.
• Transmitting
OUTPUT
POWER
[Power (Hi)]
1 • Operating CH
• Transmitting
: CH3 Rear
panel
Connect an RF power meter
to the antenna connector.
25.0 W [25W]
50.0 W [50W]
[Power (L2)] 2 • Operating CH
• Transmitting
: CH2 10.0 W [25W]
25.0 W [50W]
[Power (L1)] 3 • Operating CH
• Transmitting
: CH1 2.5 W [25W]
5.0 W [50W]
MODULATION
BALANCE
[Balance]
1 • Operating CH : CH1 Rear
panel
Connect an FM deviation me-
ter with an oscilloscope to the
antenna connector through an
attenuator.
Set to square wave
form
• Preset [MOD W] : 100
• No audio is applied to the [MIC] connec-
tor.
• Set an FM deviation meter as:
HPF
LPF
De-emphasis
Detector
: OFF
: 20 kHz
: OFF
: (P–P)/2
• Push [P0] while transmitting
FM
DEVIATION
[MOD W]
1• Operating CH : CH1 Rear
panel
Connect an FM deviation me-
ter to the antenna connector
through an attenuator.
±4.10 kHz [W/N]
±3.30 kHz [M/N]
• Connect an audio generator to the [MIC]
connector through the JIG cable and set
as
: 1.0 kHz/40 mVrms
• Set an FM deviation meter as:
HPF
LPF
De-emphasis
Detector
• Transmitting
: OFF
: 20 kHz
: OFF
: (P–P)/2
[MOD N] 2 • Operating CH
• Transmitting
: CH4 ±2.10 kHz
CTCSS/DTCS
DEVIATION
[CTCSS/DTCS]
1• Operating CH : CH5 Rear
panel
Connect an FM deviation me-
ter to the antenna connector
through an attenuator.
±0.70 kHz [W/N]
±0.56 kHz [M/N]
• No audio is applied to the [MIC] connec-
tor.
• Transmitting
5-3 SOFTWARE ADJUSTMENT (TRANSMITTING)
Select an operation using [↑] / [↓] keys, then set specified value using [←] / [→] keys on the connected computer keyboard.

5 - 6
ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT VALUE
UNIT LOCATION
RX
SENSITIVITY
[BPF T1]–
[BPF T4]
1 • Operating CH : CH8 Rear
panel
Connect a SINAD meter with
a 4 Ω load to the external
[SP] jack.
Minimum distortion
level
• Connect an SSG to the antenna connector
and set as:
Frequency
Level
Modulation
Deviation
• Receiving
: 136.000 MHz
: 10 µV* (–87 dBm)
: 1 kHz
: ±3.5 kHz [W/N]
±2.8 kHz [M/N]
CONVENIENT:
The BPF T1–BPF T4 can be adjustment automatically.
q-1: Set the cursor to "BPF ALL" and then push [ENTER] key.
q-2: The connected PC tunes BPF T1–BPF T4 to peak levels.
or
w-1: Set the cursor to one of BPF T1, T2, T3 or T4 as desired.
w-2: Push [ENTER] key to start tuning.
w-3: Repeat w-1 and w-2 to perform additional BPF tuning.
S-METER
[S-METER]
1 • Operating CH : CH8 Push the [ENTER] key on the connected computer's key-
board to set "S3" level.
• Connect an SSG to the antenna connector
and set as:
Frequency
Level
Modulation
Deviation
• Receiving
: 136.000 MHz
: 14 µV* (–84 dBm)
: 1 kHz
: ±3.5 kHz [W/N]
±2.8 kHz [M/N]
2 Set an SSG as:
Level
Deviation
• Receiving
: 0.45 µV* (–114 dBm)
: ±3.5 kHz [W/N]
±2.8 kHz [M/N]
Push the [ENTER] key on the connected computer's key-
board to set "S1" level.
SQUELCH
LEVEL
[SQL]
1 • Operating CH : CH4 Rear
panel
Connect a speaker to the
external [SP] jack.
Set SQL level to
close squelch.
Then set SQL level
at the point where
the audio signals
just appears.
• Connect an SSG to the antenna connector
and set as:
Frequency
Level
Modulation
Deviation
• Receiving
: 155.000 MHz
: 0.2 µV* (–121 dBm)
: 1 kHz
: ±1.75 kHz
*The output level of the standard signal generator (SSG) is indicated as the SSG's open circuit.
SOFTWARE ADJUSTMENT (RECEIVING)
• Select an operation using [↑] / [↓]keys, then set specified value using [←] / [→] keys on the connected computer keyboard.
• Need to adjust "S-METER ADJUSTMENT" after "RX SENSITIVITY ADJUSTMENT" is adjusted.
Otherwise , "S-METER ADJUSTMENT" will not be adjusted properly.

6 - 1
SECTION 6 PARTS LIST
M.=Mounted side (T: Mounted on the Top side, B: Mounted on the Bottom side)
[FRONT UNIT]
REF ORDER DESCRIPTION M. H/V
NO. NO.
LOCATION
[FRONT UNIT]
REF ORDER DESCRIPTION M. H/V
NO. NO.
LOCATION
IC1 1130010800 S.IC LC75824W B 80.9/24.4
IC2 1130008560 S.IC TC75S51F (TE85L) B 25.4/22.7
Q1 1590000720 S.TR DTA144EUA T106 B 52.8/22.4
Q2 1590000430 S.TR DTC144EUA T106 B 55.8/22.3
Q3 1590000430 S.TR DTC144EUA T106 B 55.9/25.4
Q4 1590000720 S.TR DTA144EUA T106 B 52.8/25.5
D1 1790001670 S.DIO RB706F-40T106 T 9.8/6.4
D2 1790001670 S.DIO RB706F-40T106 B 11/27.2
D3 1790001670 S.DIO RB706F-40T106 B 16.1/21.2
D4 1790001250 S.DIO MA2S111-(TX) B 56.6/17.4
D5 1790001250 S.DIO MA2S111-(TX) B 62.1/18
D6 1790001250 S.DIO MA2S111-(TX) B 62.7/15
L1 6200003960 S.COL MLF1608A 1R0K-T T 13.7/17.6
R1 7030003440 S.RES ERJ3GEYJ 102 V (1 kΩ) T 7.1/17.6
R2 7030003440 S.RES ERJ3GEYJ 102 V (1 kΩ) B 15.5/18.2
R3 7030003390 S.RES ERJ3GEYJ 391 V (390
Ω) B 48.1/21
R4 7030003390 S.RES ERJ3GEYJ 391 V (390
Ω) B 101.6/21.2
R5 7030003520 S.RES ERJ3GEYJ 472 V (4.7 kΩ) B 31.4/23.2
R6 7030003440 S.RES ERJ3GEYJ 102 V (1 kΩ) B 65.9/5.5
R7 7030000330 S.RES MCR10EZHJ 390
Ω(391) B 53.4/20.2
R8 7410000950 S.ARY EXB-V8V 102JV B 72.6/20.5
R9 7410000770 S.ARY EXB-V4V 102JV (1 kΩ) B 54.8/27.8
R10 7030003680 S.RES ERJ3GEYJ 104 V (100 kΩ) B 18.1/18.2
R11 7030003680 S.RES ERJ3GEYJ 104 V (100 kΩ) B 11/25.3
R12 7210003020 VAR EVU-F2KFK1 B14 (10KB)
R13 7030003730 S.RES ERJ3GEYJ 274 V (270 kΩ) B 76.5/14
R14 7030003680 S.RES ERJ3GEYJ 104 V (100 kΩ) T 11.8/6.4
R16 7030003440 S.RES ERJ3GEYJ 102 V (1 kΩ) B 32.3/10.1
R17 7030003560 S.RES ERJ3GEYJ 103 V (10 kΩ) B 82.3/14
R18 7030003560 S.RES ERJ3GEYJ 103 V (10 kΩ) B 80.3/16
R19 7030003560 S.RES ERJ3GEYJ 103 V (10 kΩ) B 78.4/14
R20 7030003520 S.RES ERJ3GEYJ 472 V (4.7 kΩ) B 21.7/20.4
R21 7030003800 S.RES ERJ3GEYJ 105 V (1 MΩ) B 23/23.2
R22 7030003560 S.RES ERJ3GEYJ 103 V (10 kΩ) B 28.5/20.2
R23 7030003560 S.RES ERJ3GEYJ 103 V (10 kΩ) B 25.8/20.2
R24 7030003480 S.RES ERJ3GEYJ 222 V (2.2 kΩ) B 19.8/25.5
R25 7030003640 S.RES ERJ3GEYJ 473 V (47 kΩ) T 18.2/20
C1 4030007090 S.CER C1608 CH 1H 470J-T B 69.6/30.3
C2 4030007090 S.CER C1608 CH 1H 470J-T B 68.3/30.3
C3 4030007090 S.CER C1608 CH 1H 470J-T B 67/30.3
C4 4030007090 S.CER C1608 CH 1H 470J-T B 65.7/30.3
C5 4030007090 S.CER C1608 CH 1H 470J-T B 64.4/30.3
C6 4030007090 S.CER C1608 CH 1H 470J-T B 63.1/30.3
C7 4030007090 S.CER C1608 CH 1H 470J-T B 61.8/30.3
C8 4030007090 S.CER C1608 CH 1H 470J-T B 60.5/30.3
C9 4030007090 S.CER C1608 CH 1H 470J-T B 59.2/30.3
C10 4030007090 S.CER C1608 CH 1H 470J-T B 59.5/21.5
C11 4030007090 S.CER C1608 CH 1H 470J-T B 60.8/21.5
C12 4030007090 S.CER C1608 CH 1H 470J-T B 62.1/21.5
C13 4030007090 S.CER C1608 CH 1H 470J-T B 63.4/21.5
C14 4030007090 S.CER C1608 CH 1H 470J-T B 64.7/21.5
C15 4030007090 S.CER C1608 CH 1H 470J-T B 66/21.5
C16 4030007090 S.CER C1608 CH 1H 470J-T B 67.3/21.5
C17 4030007090 S.CER C1608 CH 1H 470J-T B 68.6/21.5
C18 4030007090 S.CER C1608 CH 1H 470J-T B 16.8/18.2
C19 4030006860 S.CER C1608 JB 1H 102K-T T 16.3/17.6
C20 4030007090 S.CER C1608 CH 1H 470J-T B 9.3/17.2
C21 4030007090 S.CER C1608 CH 1H 470J-T B 9/9.9
C22 4030007090 S.CER C1608 CH 1H 470J-T T 4.5/17.6
C23 4030007090 S.CER C1608 CH 1H 470J-T B 6.5/9.9
C24 4030007090 S.CER C1608 CH 1H 470J-T B 72.1/5.5
C25 4030007090 S.CER C1608 CH 1H 470J-T B 90.8/7.4
C26 4030007090 S.CER C1608 CH 1H 470J-T B 122.6/25.6
C27 4030007090 S.CER C1608 CH 1H 470J-T B 122.6/30.4
C28 4030007090 S.CER C1608 CH 1H 470J-T B 122.6/15.6
C29 4030007090 S.CER C1608 CH 1H 470J-T B 110.6/2.8
C30 4030011600 S.CER C1608 JB 1E 104K-T B 79.7/14
C31 4030011600 S.CER C1608 JB 1E 104K-T B 83.6/14
C32 4030011600 S.CER C1608 JB 1E 104K-T B 81/14
C33 4030007130 S.CER C1608 CH 1H 101J-T B 76.5/15.3
C34 4030007090 S.CER C1608 CH 1H 470J-T B 29.5/10.1
C35 4030007090 S.CER C1608 CH 1H 470J-T B 70.9/30.3
C37 4550000550 S.TAN TEESVA 1V 224M8L B 19.8/22.1
C39 4030006900 S.CER C1608 JB 1H 103K-T B 27.8/24.2
C40 4550005980 S.TAN TEESVA 1A 475M8L B 20.8/28.6
C41 4030006860 S.CER C1608 JB 1H 102K-T B 19/27.4
J1 6450002210 CNR 3017-8821 <KIN>
J2 6510023090 S.CNR 20FLT-SM1-TB B 64.5/25.9
DS1 5040002310 S.LED SML-311YTT86 T 46.1/22.8
DS2 5040002310 S.LED SML-311YTT86 T 57.7/22.8
DS3 5040002310 S.LED SML-311YTT86 T 69.3/22.8
DS4 5040002310 S.LED SML-311YTT86 T 104.1/22.8
DS5 5040002310 S.LED SML-311YTT86 T 92.5/22.8
DS6 5040002310 S.LED SML-311YTT86 T 81/22.8
DS7 5040002310 S.LED SML-311YTT86 T 28.2/23.2
DS8 5040002310 S.LED SML-311YTT86 T 35/5.3
DS9 5040002310 S.LED SML-311YTT86 T 66.5/4.7
DS10 5040002310 S.LED SML-311YTT86 T 100.5/4.7
DS11 5040002310 S.LED SML-311YTT86 T 122/23.2
DS12 5030002780
W1 8900010950 CBL OPC-1126 (P=0.5 N=20 L=90)
EP2 8930057820 LCT SRCN-2526-SP-N-W
S.=Surface mount
[MAIN UNIT]
REF ORDER DESCRIPTION M. H/V
NO. NO.
LOCATION
IC1 1110003490 S.IC TA31136FN (D,EL) T 101.7/49.9
IC2 1110002750 S.IC TA75S01F (TE85R) T 56/67.2
IC3 1150002041 IC RA30H1317M-21 [25W]
1150002071 IC RA60H1317M-21 [50W]
IC4 1130010860 S.IC TB31256FL (EB) T 82.1/39.4
IC5 1110005330 S.IC NJM12904V-TE1 T 82.7/21.9
IC6 1190001350 S.IC M62364FP 600D T 103.2/29.5
IC7 1190001340 S.IC M62334FP 600C T 81.4/61.1
IC8 1110003090 IC LA4425A
IC9 1180001250 S.IC TA7808F (TE16L) T 21.4/71.1
IC10 1180000970 S.IC AN78L05M-(E1) B 49.7/74
IC11 1130008560 S.IC TC75S51F (TE85L) B 106.6/40.7
IC14 1130009330 S.IC TC35453F (BR,DRY) B 108.1/11.6
IC15 1130006220 S.IC TC4W53FU (TE12L) B 113.5/21.7
IC18 1110002750 S.IC TA75S01F (TE85R) B 18.1/57.2
IC19 1130009700 S.IC LC73872M-TRM B 93.2/9
IC20 1140010190 S.IC HD64F2268TF20 B 44.1/34.4
IC21 1110005340 S.IC NJM12902V-TE1 B 101.4/27.6
IC22 1130004200 S.IC TC4S66F (TE85R) B 82.9/22.6
IC23 1140009240 S.IC HN58X24128FPI T 60.3/10.3
IC24 1110005770 S.IC S-80942CNMC-G9C-T2 T 46.2/45.8
IC25 1130004200 S.IC TC4S66F (TE85R) B 23.4/50.8
IC26 1180002400 S.REG S-812C30AMC-C2K-T2 T 86.4/32.1
Q1 1560000840 S.FET 2SK1829 (TE85R) T 92.5/52.3
Q2 1580000730 S.FET 3SK293 (TE85L) B 90.4/53.1
Q3 1580000660 S.FET 3SK272-(TX) B 78.3/52.5
Q4 1530002600 S.TR 2SC4215-O (TE85R) B 93.2/48.6
Q5 1530002850 S.TR 2SC4116-BL (TE85R) T 97.7/55.3
Q6 1590000720 S.TR DTA144EUA T106 B 92.7/32.6
Q8 1530002620 S.TR 2SC3585-T1B R (R44) B 47.3/62.9
Q9 1530003310 S.TR 2SC5107-O (TE85R) B 52.5/62
Q10 1530003310 S.TR 2SC5107-O (TE85R) T 59.8/43.1
Q11 1530003310 S.TR 2SC5107-O (TE85R) T 66.7/42
Q12 1530003310 S.TR 2SC5107-O (TE85R) T 69.9/41.7
Q13 1530002920 S.TR 2SC4226-T1 R25 T 71.7/36.5
Q14 1530002920 S.TR 2SC4226-T1 R25 T 63.2/36.6
Q15 1590001400 S.TR XP1214 (TX) B 68.6/35
Q16 1590000430 S.TR DTC144EUA T106 B 65.4/32.6
Q17 1530002850 S.TR 2SC4116-BL (TE85R) B 55.7/47.2
Q18 1560000540 S.FET 2SK880-Y (TE85R) B 75.6/27.7
Q19 1530002600 S.TR 2SC4215-O (TE85R) B 96.3/42.2
Q20 1530003090 S.TR 2SC4213-B (TE85R) B 114.1/25
Q21 1530002850 S.TR 2SC4116-BL (TE85R) T 114.3/22.9
Q22 1590000430 S.TR DTC144EUA T106 B 92.4/29.9
Q23 1550000020 S.FET 2SJ377 (TE16L) T 10/70.3