Infineon TriCore TC1.6P User manual

V1.0 2013-07
32-bit
Microcontrollers
TriCore®TC1.6P & TC1.6E
Instruction Set
32-bit Unified Processor Core
Microcontrollers
User Manual (Volume 2)

Edition 2013-07
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2013 Infineon Technologies AG
All Rights Reserved.
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32-bit
Microcontrollers
TriCore®TC1.6P & TC1.6E
Instruction Set
32-bit Unified Processor Core
V1.0 2013-07
Microcontrollers
User Manual (Volume 2)

TriCore®TC1.6P & TC1.6E
32-bit Unified Processor Core
TriCore®User Manual (Volume 2)R
evision History: V1.0 2013-07
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Trademarks
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TriCore®TC1.6P & TC1.6E
32-bit Unified Processor Core
V1.0 2013-07
User Manual (Volume 2) 1-1
Preface 1
Instruction Set Information 1
Instruction Syntax 1
Operand Definitions 1
Instruction Mnemonic 1
Operation Modifiers 2
Data Type Modifiers 3
Opcode Formats 3
16-bit Opcode Formats 3
32-bit Opcode Formats 4
Opcode Field Definitions 5
Instruction Operation Syntax 6
RTL Functions 8
Cache RTL Functions 9
Floating Point Operation Syntax 11
Coprocessor Instructions 13
PSW Status Flags (User Status Bits) 14
List of OS and I/O Privileged Instructions 14
Instruction Set Overview 1
Integer Arithmetic 1
Move 1
Addition and Subtraction 1
Multiply and Multiply-Add 2
Division 2
Absolute Value, Absolute Difference 2
Min, Max, Saturate 2
Conditional Arithmetic Instructions 2
Logical 3
Count Leading Zeros, Ones and Signs 3
Shift 4
Bit-Field Extract and Insert 4
Packed Arithmetic 6
PSW (Program Status Word) Status Flags and
Arithmetic Instructions 8
Usage 8
Saturation 8
DSP Arithmetic 8
Scaling 8
Special Case: -1 * -1 9
Guard Bits 9
Rounding 9
Overflow and Saturation 9
Sticky Advance Overflow and Block Scaling if
FFT 9
Multiply and MAC 9
Packed Multiply and Packed MAC 10
Compare Instructions 11
Simple Compare 11
Accumulating Compare 11
Compare with Shift 12
Packed Compare 12
Bit Operations 13
Simple Bit Operations 13
Accumulating Bit Operations 14
Shifting Bit Operations 14
Address Arithmetic 15
Address Comparison 15
Branch Instructions 16
Unconditional Branch 16
Conditional Branch 17
Loop Instructions 18
Load and Store Instructions 19
Load/Store Basic Data Types 19
Load Bit 20
Store Bit and Bit Field 20
Context Related Instructions 21
Lower Context Saving and Restoring 21
Context Loading and Storing 21
System Instructions 22
System Call 22
Synchronization Primitives (DYSNC and ISYNC)
22
Access to the Core Special Function Registers
(CSFRs) 23
Enabling and Disabling the Interrupt System 23
Return (RET) and Return From Exception (RFE)
Instructions 24
Trap Instructions 24
No-Operation (NOP) 24
Coprocessor (COP) Instructions 24
16-bit Instructions 24
Instruction Set 1
CPU Instructions 1
FPU Instructions 411
MMU Instructions 434
MULTITHREAD Instructions 441
PSEUDO Instructions 443
LS and IP Instruction Summary Lists 445
List of LS Instructions 445
List of IP Instructions 447
List of Instructions by Shortname 1
List of Instructions by Longname 5

TriCore®TC1.6P & TC1.6E
32-bit Unified Processor Core
Preface
V1.0 2013-07
User Manual (Volume 2) P-1
Preface
TriCore™ is a unified, 32-bit microcontroller-DSP, single-core architecture optimized for real-time embedded
systems.
This document has been written for system developers and programmers, and hardware and software engineers.
• Volume 1 provides a detailed description of the Core Architecture and system interaction.
• Volume 2 (this volume) gives a complete description of the TriCore Instruction Set including optional
extensions for the Memory Management Unit (MMU) and Floating Point Unit (FPU).
It is important to note that this document describes the TriCore architecture, not an implementation. An
implementation may have features and resources which are not part of the Core Architecture. The documentation
for that implementation will describe all implementation specific features.
When working with a specific TriCore based product always refer to the appropriate supporting documentation.
TriCore Versions
There have been several versions of the TriCore Architecture implemented in production devices. This manual
documents the following architectures:
•TriCore1.6.1
•TriCoreS
Please note that:
• Unless stated otherwise in the text, all descriptions are common to all TriCore versions listed in this preface.
Additional Information
For information and links to documentation for Infineon products that use TriCore, visit:
http://www.infineon.com/32-bit-microcontrollers

TriCore®TC1.6P & TC1.6E
32-bit Unified Processor Core
Preface
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Text Conventions
This document uses the following text conventions:
• The default radix is decimal.
– Hexadecimal constants are suffixed with a subscript letter ‘H’, as in: FFCH.
– Binary constants are suffixed with a subscript letter ‘B’, as in: 111B
• Register reset values are not generally architecturally defined, but require setting on startup in a given
implementation of the architecture. Only those reset values that are architecturally defined are shown in this
document. Where no value is shown, the reset value is not defined. Refer to the documentation for a specific
TriCore implementation.
• Bit field and bits in registers are in general referenced as ‘Register name.Bit field’, for example PSW.IS. The
Interrupt Stack Control bit of the PSW register.
• Units are abbreviated as follows:
– MHz = Megahertz.
– kBaud, kBit = 1000 characters/bits per second.
– MBaud, MBit = 1,000,000 characters per second.
– KByte = 1024 bytes.
– MByte = 1048576 bytes of memory.
– GByte = 1,024 megabytes.
• Data format quantities referenced are as follows:
– Byte = 8-bit quantity.
– Half-word = 16-bit quantity.
– Word = 32-bit quantity.
– Double-word = 64-bit quantity.
• Pins using negative logic are indicated by an overbar: BRKOUT.
In tables where register bit fields are defined, the conventions shown in the following table are used in this
document.
Table 0-1 Bit Type Abbreviations
Abbreviation Description
r Read-only. The bit or bit field can only be read.
w Write-Only. The bit or bit field can only be written.
rw The bit or bit field can be read and written.
h The bit or bit field can be modified by hardware (such as a status bit). ‘h’ can be combined
with ‘rw’ or ‘r’ bits, to form ‘rwh’ or ‘rh’ bits.
- Reserved. Read value is undefined, but must be written with 0.

TriCore®TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set Information
V1.0 2013-07
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1 Instruction Set Information
This chapter contains descriptions of all TriCore™ instructions. The instruction mnemonics are grouped into
families of similar or related instructions, then listed in alphabetical order within those groups.
Notes
1. All instructions and operators are signed unless stated ‘unsigned’.
2. Information specific to 16-bit instructions is shown in a box with a grey background.
1.1 Instruction Syntax
The syntax definition specifies the operation to be performed and the operands used. Instruction operands are
separated by commas.
1.1.1 Operand Definitions
The Operand definitions are detailed in the following table.
1.1.2 Instruction Mnemonic
An instruction mnemonic is composed of up to three basic parts.
• A base operation
– Specifies the instructions basic operation. For example: ADD for addition, J for jump and LD for memory
load. Some instructions such as OR.EQ, have more than one base operation, separated by a period (.).
• An operation modifier
– Specifies the operation more precisely. For example: ADDI for addition using an immediate value, or JL for
a jump that includes a link. More than one operation modifier may be used for some instructions (ADDIH for
example).
• An operand (data type) modifier.
– Gives the data type of the source operands. For example: ADD.B for byte addition, JZ.A for a jump using an
address register and LD.H for a half-word load. The data type modifier is separated by a period (.).
Using the ADDS.U instruction as an example:
• ‘ADD’ is the base operation.
• ‘S’ is an operation modifier specifying that the result is saturated.
• ‘U’ is a data type modifier specifying that the operands are unsigned.
Table 1-1 Operand Definitions
Operand Definition
D[n] Data register n
A[n] Address register n
E[n] Extended data register n containing a 64-bit value made from an even/odd pair of registers
(D[n], D[n+1]). The format is little endian.
E[n][63:32] = D[n+1][31:0]; E[n][31:0] = D[n][31:0]
dispn Displacement value of ‘n’ bits, used to form the effective address in branch instructions
constn Constant value of ‘n’ bits, used as instruction operand
offn Offset value of ‘n’ bits, used to form the effective address in Load and Store instructions
pos1, pos2 Used to specify the position in a bit field instruction
pos Pos (position) is used with width to define a field
width Specifies the width of the bit field in bit field instructions

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32-bit Unified Processor Core
Instruction Set Information
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Some instructions, typically 16-bit instructions, use a General Purpose Register (GPR) as an implicit source or
destination.
Note:In the syntax section of the instruction descriptions, the implicit registers are included as explicit operands.
However they are not explicitly encoded in the instructions.
1.1.3 Operation Modifiers
The operation modifiers are shown in the following table. The order of the modifiers in this table is the same as the
order in which they appear as modifiers in an instruction mnemonic.
Table 1-2 Implicit Operand Definitions
Operand Definition
D[15] Implicit Data register for many 16-bit instructions
A[10] Stack Pointer (SP)
A[11] Return Address (RA) register for CALL, JL, JLA and JLI instructions, and Return PC value
on interrupts
A[15] Implicit Address Register for many 16-bit Load/Store instructions
Table 1-3 Operation Modifiers
Operation
Modifier Name Description Example
C Carry Use and update PSW carry bit ADDC
I Immediate Large immediate ADDI
H High Word Immediate value put in most-significant bits ADDIH
S Saturation Saturate result ADDS
X Carry out Update PSW carry bit ADDX
EQ Equal Comparison equal JEQ
GE Greater than Comparison greater than or equal JGE
L Link Record link (jump subroutine) JL
A Absolute Absolute (jump) JLA
I Indirect Register indirect (jump) JLI
LT Less than Comparison less than JLT
NE Not equal Comparison not equal JNE
D Decrement Decrement counter JNED
I Increment Increment counter JNEI
Z Zero Use zero immediate JNZ
M Multi-precision Multi-precision result (>32-bit) in Q format MULM
R Round Round result MULR
N Not Logical NOT SELN

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32-bit Unified Processor Core
Instruction Set Information
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1.1.4 Data Type Modifiers
The data type modifiers used in the instruction mnemonics are listed here. When multiple suffixes occur in an
instruction, the order of occurrence in the mnemonic is the same as the order in this table:
Note:Q format can be used as signed half-word multipliers.
1.2 Opcode Formats
1.2.1 16-bit Opcode Formats
Note:Bit[0] of the op1 field is always 0 for 16-bit instructions.
Table 1-4 Data Type Modifiers
Data Type
Modifier Name Description Example
D Data 32-bit data MOV.D
D Double-word 64-bit data/address LD.D
W Word 32-bit (word) data EQ.W
A Address 32-bit address ADD.A
Q Q Format 16-bit signed fraction (Q format) MADD.Q
H Half-word 16-bit data or two packed half-words ADD.H
B Byte 8-bit data or four packed bytes ADD.B
T Bit 1-bit data AND.T
U Unsigned Unsigned data type ADDS.U
Table 1-5 16-bit Opcode Formats
15-14 13-12 11-10 09-08 07-06 05-04 03-02 01-00
SB disp8 op1
SBC const4 disp4 op1
SBR s2 disp4 op1
SBRN n disp4 op1
SC const8 op1
SLR s2 d op1
SLRO off4 d op1
SR op2 s1/d op1
SRC const4 s1/d op1
SRO s2 off4 op1
SRR s2 s1/d op1
SRRS s2 s1/d n op1
SSR s2 s1 op1
SSRO off4 s1 op1

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32-bit Unified Processor Core
Instruction Set Information
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1.2.2 32-bit Opcode Formats
Note:Bit[0] of the op1 field is always 1 for 32-bit instructions.
Table 1-6 32-bit Opcode Formats
31:30 29:28 27:26 25:24 23:22 21:20 21:20 19:18 17:16 15:14 13:12 11:10 9-8
7-6
5-0
ABS off18
[9:6]
op2 off18
[13:10] off18[5:0]
off18
[17:14]
s1/d
op1
ABSB off18
[9:6]
op2 off18
[13:10] off18[5:0]
off18
[17:14]
b bpos3
op1
B disp24[15:0] disp24[23:16]
op1
BIT d pos2 op2 pos1 s2 s1 op1
BO off10[9:6] op2 off10[5:0] s2 s1/d
op1
BOL off16[9:6] off16[15:10] off16[5:0] s2 s1/d
op1
BRC o
p
2
disp15 const4 s1
op1
BRN o
p
2
disp15 n[3:0] s1
n[4]
op1
BRR o
p
2
disp15 s2 s1 op1
RC d op2 const9 s1 op1
RCPW d pos op2 width const4 s1 op1
RCR d s3 op2 const9 s1 op1
RCRR d s3 op2 - const4 s1 op1
RCRW d s3 op2 width const4 s1 op1
RLC d const16 s1 op1
RR d op2 - n s2 s1 op1
RR1 d op2 n s2 s1 op1
RR2 d op2 s2 s1 op1
RRPW d pos op2 width s2 s1 op1
RRR d s3 op2 - n s2 s1 op1
RRR1 d s3 op2 n s2 s1 op1
RRR2 d s3 op2 s2 s1 op1
RRRR d s3 op2 - s2 s1 op1
RRRW d s3 op2 width s2 s1 op1
SYS - op2 - s1/d op1

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32-bit Unified Processor Core
Instruction Set Information
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1.2.3 Opcode Field Definitions
Table 1-7 Opcode Field Definitions
Name Width Definition
s1 4 Source register(s) one
s2 4 Source register(s) number two
s3 4 Source register(s) number three
d 4 Destination register
For a register pair (E), the coding follows the register number:
E[0] = 0000B, E[2] = 0010B, E[4] = 0100B, and so on.
b1Bitvalue
bpos3 3 Bit position in a byte
pos 5 Bit position in a register
pos1 5 Bit position in a register
pos2 5 Bit position in a register
width 5 Bit position in a register
n2
• Multiplication result shift value (only 00Band 01Bare valid).
• Address shift value in add scale.
• Default to zero in all other operations using the RR format.
• Coprocessor number for coprocessor instructions.
const4 4 4-bit constant
const9 9 9-bit constant
const16 16 16-bit constant
disp4 4 4-bit displacement
disp8 8 8-bit displacement
disp15 15 15-bit displacement
disp24 24 24-bit displacement
off4 4 4-bit offset
off10 10 10-bit offset
off16 16 16-bit offset
- - Reserved field.
Read value is undefined; should be written with zero (0).
Must be set to zero (0) to allow for future compatibility.
op1 Primary Opcode
op2 Secondary Opcode

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32-bit Unified Processor Core
Instruction Set Information
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1.3 Instruction Operation Syntax
The operation of each instruction is described using a ‘C-like’ Register Transfer Level (RTL) notation.
Notes
1. The numbering of bits begins with bit zero, which is the least-significant bit of the word.
2. All intermediate 'result' values are assumed to have infinite precision unless otherwise indicated.
Table 1-8 RTL Syntax
Syntax Definition
bpos3 Bit position
const’n’ Constant value of ‘n’bits, used as instruction operand
disp’n’ Displacement value of ‘n’ bits, used to form the effective address in branch instructions
(expression)[p] A single bit, wiht ordinal index ‘p’ in the bit field ‘expression’
n’bx Constant bit string, where ‘n’ is the number of bits in the constant and ‘x’ is the constant
in binary. For example; 2’b11
n’hx Constant bit string, where ‘n’ is the number of bits in the constant and ‘x’ is the constant
in hexadecimal. For example, 16’hFFFF
off’n’ Offset value of ‘n’ bits, used to form the effective address in Load and Store instructions
pos Single bit position
signed A value that can be positive, negative or zero
ssov Saturation on signed overflow
suov Saturation on unsigned overflow
unsigned A value that can be positive or zero
{x,y} A bit string where ‘x’ and ‘y’ are expressions representing a bit or bit field. Any number
of expressions can be concatenated. For example, {x,y,z}
A[n] Address register ‘n’
CR Core Register
D[n] Data register ‘n’
EA Effective Address
E[n] Data register containing a 64-bit value, constructed by pairing two data registers. The
least-significant bit is in the even register D[n], and the most significant bit is in the odd
register D[n+1]
M(EA, data_size) Memory locations beginning at the specified byte location EA, and extending to EA +
data_size - 1.
data_size = byte, half-word, word, , 16-word
<mode> And addressing mode
P[n] Address register containing a 64-bit value, constructed by pairing two address registers.
The least-significant bit is in the even register A[n], and the most significant bit is in the
odd register A[n+1]
PC The address of the instruction in memory
[x:y] Bits y, y+1, ..., x where x>y;
For example D[a][x:y], if x=y then this is a single bit range which is also denoted by [x],
as in D[a][x]. For cases where x<y, this denotes an empty range.

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32-bit Unified Processor Core
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TRUE Boolean true. Equivalent to integer 1
FALSE Boolean false. Equivalent to integer 0
AND Logical AND. Returns a boolean result
OR Logical OR. Returns a boolean result
XOR Logical XOR. Returns a boolean result
! Logical NOT. Returns a boolean result
^ Bitwise XOR
& Bitwise AND
| Bitwise OR
~ Bitwise NOT
< Less than. Returns a boolean result
> Greater than. Returns a boolean result
<= Less than or equal to. Returns a boolean result
>= Greater than or equal to. Returns a boolean result
>> Right shift. High order bits shifted in are 0’s
<< Left shift. Low order bits shifted in are 0’s
+Add
- Subtract
* Multiply
/ Divide
% Modulo
= Equal to (assignment)
== Is equal to (comparison). Returns a boolean result
!= Not equal to. Returns a boolean result
≈Approximately equal to
|| Parallel operation
? : Conditional expression (Ternary operator)
∞Infinity
// Comment
Table 1-8 RTL Syntax
Syntax Definition

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Instruction Set Information
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1.3.1 RTL Functions
Register Transfer Level functions are defined in the table which follows.
Table 1-9 RTL Functions
Function Definition
abs(x) abs(x) returns ((x <0) ? (0 - x) : x);
cache_address_ivld(EA) Defined in ‘Cache RTL Functions’, which follows
cache_address_wb(EA) Defined in ‘Cache RTL Functions’, which follows
cache_address_wi(EA) Defined in ‘Cache RTL Functions’, which follows
cache_index_ivld Defined in ‘Cache RTL Functions’, which follows
cache_index_wb Defined in ‘Cache RTL Functions’, which follows
cache_index_wi Defined in ‘Cache RTL Functions’, which follows
cache_index_wb(EA) Defined in the ‘Cache RTL Functions’ section, which follows. ( TriCore1.6.1
TriCoreS)
cache_index_wi(EA) Defined in the ‘Cache RTL Functions’ section, which follows. ( TriCore1.6.1
TriCoreS)
carry(a,b,c) carry(a,b,c) {
result = a + b + c; // unsigned additions
return result[32];
cdc_decrement() If PSW.CDC == 7’b1111111 returns FALSE, otherwise decrements
PSW.CDC.COUNT and returns TRUE if PSW.CDC.COUNT underflows,
otherwise returns FALSE
cdc_increment() If PSW.CDC == 7'b1111111 returns FALSE, otherwise increments
PSW.CDC.COUNT and returns TRUE if PSW.CDC.COUNT overflows,
otherwise returns FALSE
cdc_zero() Returns TRUE if PCW.CDC.COUNT == 0 or if PSW.CDC == 7'b1111111,
otherwise returns FALSE
leading_ones(x) Returns the number of leading ones of ‘x’
leading_signs(x) Returns the number of leading sign bits of ‘x’
leading_zeros(x) Returns the number of leading zeros of ‘x’
reverse16(n) {n[0], n[1], n[2], n[3], n[4], n[5], n[6], n[7], n[8], n[9], n[10], n[11], n[12], n[13],
n[14], n[15]}
round16(n) = {(x + 32'h00008000)[31:16],16'h0000};
ssov(x,y) max_pos = (1 << (y - 1)) - 1;
max_neg = -(1 << (y - 1));
return ((x > max_pos) ? max_pos : ((x < max_neg) ?
max_neg : x ));
suov(x,y) max_pos = (1 << y) - 1;
return ((x > max_pos) ? max_pos : ((x < 0) ? 0 : x));
sign_ext(x) Sign extension; high-order bit of x is left extended
trap(x) Instruction will take trap ‘x’
zero_ext(x) Zero extensions; high-order bits are set to 0

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1.3.2 Cache RTL Functions
CACHE[ ] is a syntactic structure which hides the implementation characteristics of the cache implemented.
CACHE can be associatively accessed either by:
• A single argument which is an address.
• Two arguments consisting of implementation defined ranges for set_index and set_element.
In either case the CACHE[ ] access returns a structure with:
• Boolean validity information (CACHE[ ].valid).
• Boolean data modification information (CACHE[ ].modified).
• Physical address of the copied location (CACHE[ ].physical_address).
• Stored data associated with the address (CACHE[ ].data).
The cache function descriptions are given in the following table.
Notes
1. ‘cacheline’, which appears in the cache function descriptions, is the size of the cache line in bytes and is
implementation dependent.
2. ‘index’ and ‘elem’, which appear in the cache function descriptions, are the set_index and set_element values.
These values are implementation dependent.
Table 1-10 Cache Functions
Function Definition
cache_address_ivld(EA) if (CACHE[EA].valid==1) then CACHE [EA].valid=0;
cache_address_wb(EA) if ((CACHE[EA].valid==1) AND (CACHE[EA].modified==1)) then {
pa = CACHE[EA].physical_address;
M[pa,cacheline] = CACHE[EA].data;
CACHE[EA].modified = 0;
}
cache_address_wi(EA) if (CACHE[EA].valid==1) then {
if (CACHE[EA].modified==1) then {
pa = CACHE[EA].physical_address;
M[pa,cacheline] = CACHE[EA].data;
}
CACHE[EA].modified = 0;
CACHE[EA].valid = 0;
}
cache_index_ivld if (CACHE[index,elem].valid = = 1) then CACHE[index,elem].valid = 0;
cache_index_wb if ((CACHE[index,elem].valid==1) AND (CACHE[index,elem].modified==1))
then {
pa = CACHE[index,elem].physical_address;
M[pa,cacheline] = CACHE[index,elem].data;
CACHE[index,elem].modified = 0;
}

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cache_index_wi if (CACHE[index,elem].valid==1) then {
if (CACHE[index,elem].modified==1) then {
pa = CACHE[index,elem].physical_address;
M[pa,cacheline] = CACHE[index,elem].data;
}
CACHE[index,elem].modified = 0;
CACHE[index,elem].valid = 0;
}
cache_Index_wb(location) if ((CACHE[index,elem].valid==1) AND (CACHE[index,elem].modified==1))
then {
pa = CACHE[index,elem].physical_address;
M[pa,cacheline] = CACHE[index,elem].data;
CACHE[index,elem].modified = 0;
}
cache_index_wi(location) if (CACHE[index,elem].valid==1) then {
if (CACHE[index,elem].modified==1) then {
pa = CACHE[index,elem].physical_address;
M[pa,cacheline] = CACHE[index,elem].data;
}
CACHE[index,elem].modified = 0;
CACHE[index,elem].valid = 0;
}
Table 1-10 Cache Functions
Function Definition

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1.3.3 Floating Point Operation Syntax
The following table defines the floating point operation syntax.
Table 1-11 Floating Point Operation Syntax
Syntax Definition
ADD_NAN 7FC00001H
MUL_NAN 7FC00002H
SQRT_NAN 7FC00004H
DIV_NAN 7FC00008H
POS_INFINITY 7F800000H
NEG_INFINITY FF800000H
is_s_nan(x) Takes the IEEE-754-1985 32-bit single precision floating point format value ‘x’
and returns the boolean result of the expression:
(x[30:23] == 8'b11111111) AND (x[22] == 1’b0) AND (x[21:0] != 0);
is_q_nan(x) Takes the IEEE-754-1985 32-bit single precision floating point format value ‘x’
and returns the boolean result of the expression:
(x[30:23] == 8’b11111111) AND (x[22] == 1’b1);
is_nan(x) Takes the IEEE-754-1985 32-bit single precision floating point format value ‘x’
and returns the boolean result of the expression: (is_s_nan(x) OR
is_q_nan(x));
is_pos_inf(x) Takes the IEEE-754-1985 32-bit single precision floating point format value ‘x’
and returns the boolean result of the expression:
(x[31:0] == POS_INFINITY);
is_neg_inf(x) Takes the IEEE-754-1985 32-bit single precision floating point format value ‘x’
and returns the boolean result of the expression:
(x[31:0] == NEG_INFINITY);
is_inf(x) Takes the IEEE-754-1985 32-bit single precision floating point format value ‘x’
and returns the boolean result of the expression: (is_neg_inf(x) OR
is_pos_inf(x));
is_zero(x) Takes the IEEE-754-1985 32-bit single precision floating point format value ‘x’
and returns the boolean result of the expression: (x[30:0] == 0);
is_denorm(x) Takes the IEEE-754-1985 32-bit single precision floating point format value ‘x’
and returns the boolean result of the expression: (x[30:23] == 0) AND (x[22:0]
!= 0);
denorm_to_zero(x) If the IEEE-754-1985 32-bit single precision floating point format value ‘x’ is a
denormal value return the appropriately signed infinitely accurate real value 0.
Otherwise return ‘x’ as an infinitely accurate real value; i.e.
if((x < 0) AND (x > -2-126)) then return -0.0;
else if((x > 0) AND (x < 2126)) then return +0.0;
else return f_real(x);
round_to_integer(x,y) Returns a signed integer result of infinite width by rounding the IEEE-754-1985
32-bit single precision floating point format value ‘x’ to an integer value using
the IEEE-754-1985 mode specified by ‘y’.
round_to_unsigned(x,y) Returns an unsigned integer result of infinite width by rounding the IEEEV 32-
bit single precision floating point format value ‘x’ to an integer value using the
IEEE-754-1985 mode specified by ‘y’.

TriCore®TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set Information
V1.0 2013-07
User Manual (Volume 2) 1-12
round_to_q31(x,y) Returns a Q format result of infinite width by rounding the real value ‘x’ to a Q
format value using the IEEE-754-1985 mode specified by ‘y’.
i_real(x) Returns a infinitely accurate real number of equal value to the 32-bit signed
integer value ‘x’.
u_real(x) Returns a infinitely accurate real number of equal value to the 32-bit unsigned
integer value ‘x’.
f_real(x) Returns the IEEE-754-1985 32-bit single precision floating point format value
‘x’ as an infinitely accurate real value.
q_real(x) Returns the Q31 format value ‘x’ as an infinitely accurate real value.
add(x,y) Adds the real value ‘x’ to the real value ‘y’ and returns an infinitely accurate real
result.
mul(x,y) Multiply the real value ‘x’ by the real value ‘y’ and return an infinitely accurate
real result.
divide(x,y) Divides the real value ‘x’ by the real value ‘y’ and returns an infinitely accurate
real result.
ieee754_round(x,y) Rounds the real value ‘x’ using the type of rounding specified by ‘y’ compliant
with IEEE-754-1985.
ieee754_32bit_format(x) Returns the real value ‘x’ in the standard 32-bit single precision IEEE-754-
1985 floating point format. ‘x’ is converted to the correct IEEE-754-1985 result
on overflow or underflow.
ieee754_lt(x,y) Returns TRUE if ‘x’ is less than ‘y’ according to the IEEE-754-1985 rules for
32-bit single precision floating point numbers otherwise returns FALSE.
ieee754_gt(x,y) Returns TRUE if ‘x’ is greater than ‘y’ according to the IEEE-754-1985 rules for
32-bit single precision floating point numbers otherwise returns FALSE.
ieee754_eq(x,y) Returns TRUE if ‘x’ is equal to ‘y’ according to the IEEE-754-1985 rules for 32-
bit single precision floating point numbers otherwise returns FALSE.
fp_abs(x) Returns the infinitely accurate absolute value of the real value ‘x’; i.e. (x < 0.0)
? (0.0 - x) : x;
approx_inv_sqrt(x) Takes the real argument x and returns the approximate inverse square root (x-
0.5) to at least 6.75 bits of precision.
Table 1-11 Floating Point Operation Syntax
Syntax Definition

TriCore®TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set Information
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1.4 Coprocessor Instructions
The TriCore®instruction set architecture may be extended with implementation defined, application specific
coprocessor instructions. These instructions are executed on dedicated coprocessor hardware attached to the
coprocessor interface.
The coprocessors operate in a similar manner to the integer instructions, receiving operands from the general
purpose data registers, returning a result to the same registers.
The architecture supports the operation of up to four concurrent coprocessors (n = 0, 1, 2, 3).
Two of these (n = 0, 1) are reserved for use by the TriCore CPU, allowing two (n = 2, 3) for use by the application
hardware.
Figure 1-1 Coprocessor Instructions
Table 1-12 Coprocessor Status Flags
C Not set by this instruction
V Not set by this instruction
SV Not set by this instruction
AV Not set by this instruction
SAV Not set by this instruction