Infineon XMC7000 Series Guide

Application Note Please read the Important Notice and Warnings at the end of this document 002-33887 Rev. *A
www.infineon.com page 1 of 33 2022-05-25
AN233887
Using the Watchdog Timer in XMC7000 family
MCUs
About this document
Scope and purpose
This application note describes how to handle the watchdog timer in XMC7000 family MCUs. It introduces the
functions of the basic watchdog timer and multi-counter watchdog timer and the necessary configurations to
generate faults, interrupts, and reset.
Intended audience
This document is intentded for anyone using XMC7000 family MCUs.
Table of contents
About this document....................................................................................................................... 1
Table of contents............................................................................................................................ 1
1Introduction .......................................................................................................................... 3
2Basic WDT.............................................................................................................................. 4
2.1 Source clock ............................................................................................................................................5
2.2 WDT timer counter ..................................................................................................................................5
2.3 Register protection..................................................................................................................................5
2.4 Warning interrupt....................................................................................................................................5
2.5 Timeout mode.........................................................................................................................................6
2.6 Window mode..........................................................................................................................................7
2.7 Basic WDT settings ..................................................................................................................................7
2.7.1 Use case..............................................................................................................................................8
2.7.2 Configuring the Basic WDT ................................................................................................................9
2.8 Clearing the basic WDT .........................................................................................................................11
2.8.1 Use case............................................................................................................................................12
2.8.2 Example flow to clear the basic WDT ..............................................................................................12
2.9 Reset cause indication for the basic WDT ............................................................................................12
2.10 Basic WDT registers...............................................................................................................................13
3Multi-counter WDT ................................................................................................................14
3.1 Source clock ..........................................................................................................................................14
3.2 Register protection in MCWDT..............................................................................................................14
3.3 MCWDT interrupts .................................................................................................................................15
3.3.1 Pre-warning interrupt ......................................................................................................................15
3.3.2 MCWDT Subcounter 2 interrupt.......................................................................................................15
3.4 Timeout mode.......................................................................................................................................15
3.5 Window mode........................................................................................................................................16
3.6 Selecting the CPU..................................................................................................................................17
3.7 MCWDT settings.....................................................................................................................................17
3.7.1 Use case............................................................................................................................................18
3.7.2 Configuring the MCWDT...................................................................................................................19

Application Note 2 of 33 002-33887 Rev. *A
2022-05-25
Using the Watchdog Timer in XMC7000 family MCUs
Table of contents
3.8 Clearing the MCWDT..............................................................................................................................22
3.8.1 Use case............................................................................................................................................22
3.8.2 Example flow to clear the MCWDT...................................................................................................22
3.8.3 Example program to clear the MCWDT ...........................................................................................24
3.9 MCWDT fault handling...........................................................................................................................24
3.9.1 Use case............................................................................................................................................24
3.9.2 Example flow of MCWDT fault handler............................................................................................25
3.10 Reset cause indication for MCWDT.......................................................................................................26
3.11 MCWDT registers ...................................................................................................................................27
4Debug support ......................................................................................................................28
5Definitions, acronyms, and abbreviations................................................................................29
6Related documents ...............................................................................................................30
7Other references ...................................................................................................................31
Revision history.............................................................................................................................32

Application Note 3 of 33 002-33887 Rev. *A
2022-05-25
Using the Watchdog Timer in XMC7000 family MCUs
Introduction
1Introduction
This application note describes the watchdog timer (WDT) for the XMC7000 family MCU. A WDT detects an
unexpected firmware execution path by generating warning interrupts, faults, or resets. It allows the system to
recover from an unsafe execution of an application program.
The WDT includes different counters that are used to observe a predetermined period and monitors the normal
operation of the application software by periodically clearing the timer. When the WDT reaches the
predetermined period, it detects the condition as an abnormality and generates a reset or an interrupt, or a
fault event.
XMC7000 supports two types of WDTs:
•A Basic WDT
•A Multi-counter WDT (MCWDT).
Both WDTs support window mode which allows defining an upper and lower time limit within which the
watchdog timer must be served. The Basic WDT is activated by hardware after reset release. Its operation mode
is set by the application software during the initial setting. It counts in Active, Sleep, DeepSleep, and Hibernate
power modes. The MCWDT is activated and configured by the application software. It counts in Active, Sleep,
and DeepSleep power modes.
This document is applicable for XMC7100 series, XMC7200 series devices. Figure 1 shows the block diagram of
the WDT. It includes both sub-structures, the Basic WDT, and the MCWDT. See the “Watchdog Timer”chapter of
the Architecture Technical Reference Manual (TRM) for more details.
Basic Watchdog Timer
Multi Counter
Watchdog Timers
Device registers AHB interface
LFCLK
(Low-frequency clock) Clock
CFG/STATUS
Reset
Interrupt
Clock
CFG/STATUS
Reset
Interrupt WIC
(Wakeup Interrupt
Controller)
Device Reset
ILO0
(32-kHz low-speed
oscillator)
FAULT FAULT Structure
Interrupt Controller
Figure 1 WDT block diagram

Application Note 4 of 33 002-33887 Rev. *A
2022-05-25
Using the Watchdog Timer in XMC7000 family MCUs
Basic WDT
2Basic WDT
Figure 2 shows the block diagram of the Basic WDT. It supports one 32-bit free-running counter that counts up
with the ILO0 clock if the ENABLE [31] bit is set to ‘1’ in the WDT_CTL register.
Operation during Hibernate mode is possible because the WDT logic and ILO0 are supplied by the external high-
voltage supply (VDDD). A WDT reset restores the chip to Active mode. By default, the Basic WDT is enabled,
UPPER_ACTION is configured as reset, UPPER_LIMIT is set with the value 0x8000, and all protectable registers
are locked. UPPER_ACTION and UPPER_LIMIT are configuration registers that are used to define the behavior of
the Basic WDT in case it is not serviced in time and if a reset should be executed.
WDT configuration registers are in a protection region separate from the register that is used to service it.
Protection regions are handled by the Peripheral Protection Unit (PPU). See the CPU Subsystem (CPUSS)
chapter in the Architecture TRMfor more information.
WDT (32-bit Up-Counter)
WDT_CNT
ILO0
INTERRUPT
CTL_ENABLE EN
SERVICE
(Write from
Firmware)
Count = 0
RESET
Count < LOWER_LIMIT
Count == 3Count >= UPPER_LIMIT
Count == WARN_LIMIT
Count
32
Debug_active Debug
WDT_CONFIG
WARN
ACTION
UPPER
ACTION
LOWER
ACTION
Figure 2 Basic WDT block diagram
Depending on the configuration in the WDT_CONFIG register, an interrupt or a reset event can be generated
when the counter reaches related counter limits. Three threshold limits can be used for the following actions:
•LOWER-LIMIT: If the LOWER_ACTION[0] bit is set to ‘1’ in the WDT_CONFIG register, a reset is issued when
the watchdog routine is serviced before the WDT reaches the LOWER_LIMIT value.
•UPPER-LIMIT: If the UPPER_ACTION[4] bit is set to ‘1’ in the WDT_CONFIG register, a reset is issued when the
WDT reaches the UPPER_LIMIT value before the WDT is serviced.
•WARN-LIMIT: If the WARN_ACTION[8] bit is set to ‘1’ in the WDT_CONFIG register, an interrupt is issued when
the WDT reaches the WARN_LIMIT value.
UPPER-LIMIT and LOWER-LIMIT in combination are used to build the window mode for the Basic WDT.
Depending on the Basic WDT mode defined by the ACTION bits in the WDT_CONFIG register, servicing of the
watchdog counter must be handled differently. In window mode, the firmware must ensure adequate

Application Note 5 of 33 002-33887 Rev. *A
2022-05-25
Using the Watchdog Timer in XMC7000 family MCUs
Basic WDT
watchdog servicing timing to fulfill the window timing conditions. If the LOWER_ACTION bit is not set, the Basic
WDT can be serviced anytime before the UPPER_LIMIT value is reached.
2.1 Source clock
The source clock that can be selected for the Basic WDT is fixed to the ILO0 clock: 32.768 kHz.
2.2 WDT timer counter
The Basic WDT count width is 32 bits. Therefore, the timer period that can be set is between 30.518 µs and
131,072 s. These values are calculated with the typical ILO0 timing. Tolerances must also be considered. See
the device datasheet for details.
2.3 Register protection
Changing the register values that are used to configure the Basic WDT requires an UNLOCK sequence of the
WDT_LOCK[1:0] bits located in the LOCK register. The following write access sequence to the WDT_LOCK bit
field must be performed for unlocking CNT, CTL, LOWER_LIMIT, UPPER_LIMIT, WARN_LIMIT, CONFIG, and
SERVICE registers:
•WDT_LOCK = 1
•WDT_LOCK = 2
To regain the lock for the Basic WDT registers, one single access to the LOCK register is required:
•WDT_LOCK = 3
Check the lock status by reading the WDT_LOCK register. If the read value is not equal to ‘0’, it indicates that
Basic WDT registers are locked.
After a transition from DeepSleep or Hibernate mode to Active mode, all basic WDT registers are locked.
2.4 Warning interrupt
The basic WDT supports a WARN limit that can be used to define a dedicated timing to generate an interrupt. It
can be used for different purposes such as follows:
•Pre-warning event: The WARN_LIMIT value is defined as lower than the UPPER_LIMIT value. It is enabled if
the WARN_ACTION[8] bit in the CONFIG register is set to ‘1’. Note that you should use adequate limits to
execute the WARN interrupt in time.
•Wakeup event: The basic WDT can be used as a simple wakeup timer by setting the warning interrupt for
the desired wakeup time period. The watchdog counter can send interrupt requests to the wakeup interrupt
controller (WIC) in Sleep and DeepSleep power modes. In addition, the basic WDT is capable of waking up
the device from Hibernate power mode. This can be used with or without the normal watchdog reset
behavior.
The configuration of wakeup from Hibernate mode is done in the PWR_HIBERNATE register. See the “System
Resources Registers”chapter in the Technical Reference Manual (TRM) for more details.
The basic WDT can be serviced automatically by setting the AUTO_SERVICE[12] bit to ‘1’ in the CONFIG
register. Setting up automatic servicing of the basic WDT creates a periodic interrupt if the basic WDT
counter is not used as a watchdog timer with the timeout reset function. This means that the
LOWER_ACTION[0] and UPPER_ACTION[1] bits are set to ‘0’ in the CONFIG register. Servicing the basic WDT
counter in the corresponding interrupt service routine (ISR) is not required. The basic WDT counter is
serviced by the hardware.

Application Note 6 of 33 002-33887 Rev. *A
2022-05-25
Using the Watchdog Timer in XMC7000 family MCUs
Basic WDT
Figure 3 illustrates an example for a 500-milliseconds periodic wakeup timing with auto servicing activated.
The calculation is done using the following equation:
          
500ms
Time
WARN_LIMIT = 0x4000
Counts value
0xFFFFFFFF
AUTO_SERVICE
Wake-up event
Low Power Mode
RUN Mode
AUTO_SERVICE
Wake-up event AUTO_SERVICE
Wake-up event
AUTO_SERVICE
Wake-up event
Figure 3 Periodic wakeup with basic WDT
2.5 Timeout mode
The legacy mode of the basic WDT is the standard watchdog behavior with a timeout condition for resetting the
MCU. It uses the UPPER_LIMIT register for generating a reset if the basic WDT is not serviced in time. Set the
UPPER_ACTION[4] bit in the CONFIG register to ‘1’ to trigger a reset when the watchdog counter matches with
the UPPER_LIMIT value.
The WARN_LIMIT register can be used as a pre-warning event to indicate an incorrect watchdog counter service
timing. Set the WARN_ACTION[8] bit in the CONFIG register to ‘1’ to enable the warn interrupt.
Figure 4 shows an example for the basic WDT which demonstrates how to define the upper limit timeout
period of 1 second and 875-milliseconds pre-warning interrupt timing. Corresponding register values are
calculated as follows:
          
          
875ms
Time
WARN_LIMIT = 0x7000
Counts value
0xFFFFFFFF
SERVICE
WARN
Interrupt
RESET
UPPER_LIMIT = 0x8000
SERVICE
1sec
Figure 4 Basic WDT with timeout and pre-warning

Application Note 7 of 33 002-33887 Rev. *A
2022-05-25
Using the Watchdog Timer in XMC7000 family MCUs
Basic WDT
The example shows the following three scenarios:
•Service the basic WDT counter before it reaches the WARN_LIMIT.
•Service the basic WDT counter within the pre-warning ISR.
•If the basic WDT counter is not serviced in time, a RESET is issued after 1 second.
2.6 Window mode
XMC7000 MCUs support the option to define a lower counter threshold that allows a WDT window mode. WDT
window mode supports the observation of two counter limits: a lower limit and an upper limit. If the watchdog
is serviced before the counter has reached the configured lower limit value in the LOWER_LIMIT register, a reset
is issued. If the watchdog is not serviced before the upper limit of the basic WDT counter is reached, a reset is
issued. The two limits define the window timing within which the basic watchdog timer must be serviced. To
enable this function, the LOWER_ACTION[0] bit in the CONFIG register must be set to ‘1’, and an adequate lower
limit period must be defined in the LOWER_LIMIT register.
The following example calculates the LOWER_LIMIT of 150 ms:
          
2.7 Basic WDT settings
This section describes how to configure the WDT based on a use case using the ModusToolbox™ CAT1
Peripheral Driver Library provided by Infineon. The code snippets in this application note are part of the
ModusToolbox™ CAT1 Peripheral Driver Library. See Other references.
ModusToolbox™ CAT1 Peripheral Driver Library has a configuration part and a driver part. The configuration
part configures the parameter values for the desired operation.

Application Note 8 of 33 002-33887 Rev. *A
2022-05-25
Using the Watchdog Timer in XMC7000 family MCUs
Basic WDT
Figure 5 shows an example flow to configure the basic WDT.
Basic Watchdog Timer Setting
Set UPPER_LIMIT
Disable Basic Watchdog Timer
Set LOWER_LIMIT
Unlock Basic Watchdog Timer
Registers
Set WARN_LIMIT
Set WARN_ACTION
Set UPPER_ACTION
Set LOWER_ACTION
Enable WDT Interrupt
Enable Basic Watchdog Timer
Lock Basic Watchdog Timer Registers
Configure Auto Service
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(11)
(12)
(13)
Configure Counter Pause in Debug
Mode
(10)
Clear Pending Interrupt
End
Enable Interrupt
System Interrupt Control
Enable NVIC Interrupt Controller
Setup Interrupt (WDT Warn Interrupt)
Clear NVIC Pending Register
(14)
(15)
(16)
Configure Interrupt
Figure 5 Example flow to configure basic WDT
2.7.1 Use case
This section explains an example of the basic WDT using the following use case. The basic WDT is cleared in the
warn interrupt handler. A reset is triggered if the basic WDT is not cleared between LOWER_LIMIT and
UPPER_LIMIT.
Use case:
•LOWER_LIMIT: 125 ms
•UPPER_LIMIT: 1 second
•WARN_LIMIT: 875 ms

Application Note 9 of 33 002-33887 Rev. *A
2022-05-25
Using the Watchdog Timer in XMC7000 family MCUs
Basic WDT
•Window mode: Used
•Warn interrupt: Used (IRQ number: 2)
•Auto service: Unused
•Debugger configuration: Enables the trigger input for WDT to pause the counter during debug mode
2.7.2 Configuring the Basic WDT
Table 1 lists the parameters of the configuration part in ModusToolbox™ CAT1 Peripheral Driver Library for
basic WDT.
Table 1 List of basic WDT parameters
Code Listing 1 shows an example program of the basic WDT configuration part. For details of the interrupt
initial setting procedure, see the “Interrupt Structure” section in AN234226 listed in Related documents.
Function
Description
Value
Cy_WDT_SetLowerLimit()
Sets the lower limit
(unsigned integer 32-bit)
4096ul
Cy_WDT_SetUpperLimit()
Sets the upper limit
(unsigned integer 32-bit)
32768ul
Cy_WDT_SetWarnLimit()
Sets the warn limit
(unsigned integer 32-bit)
28672ul
Cy_WDT_SetLowerAction()
Sets the lower action to “no action”or
“reset”:
CY_WDT_LOW_UPP_ACTION_NONE = 0ul
CY_WDT_LOW_UPP_ACTION_RESET = 1ul
CY_WDT_LOW_UPP_ACTION_RE
SET
Cy_WDT_SetUpperAction()
Sets the upper action to “no action”or
“reset”:
CY_WDT_LOW_UPP_ACTION_NONE = 0ul
CY_WDT_LOW_UPP_ACTION_RESET = 1ul
CY_WDT_LOW_UPP_ACTION_RE
SET
Cy_WDT_SetWarnAction()
Sets the warn action to “no action”or
“interrupt”:
CY_WDT_WARN_ACTION_NONE = 0ul
CY_WDT_WARN_ACTION_INT = 1ul
CY_WDT_WARN_ACTION_INT
Cy_WDT_SetAutoService()
Configures to automatically clear the
basic WDT when the count value reaches
WARN_LIMIT:
CY_WDT_DISABLE = 0ul
CY_WDT_ENABLE = 1ul
CY_WDT_DISABLE
Cy_WDT_SetDebugRun()
Sets the debugger configuration (required
when using debugger)
CY_WDT_DISABLE = 0ul
CY_WDT_ENABLE = 1ul
CY_WDT_ENABLE

Application Note 10 of 33 002-33887 Rev. *A
2022-05-25
Using the Watchdog Timer in XMC7000 family MCUs
Basic WDT
Code Listing 1 Example of basic WDT configuration using Hardware Abstraction Layer (HAL)
void initialize_wdt()
{
cy_rslt_t result;
/* Initialize the WDT */
result = cyhal_wdt_init(&wdt_obj, WDT_TIME_OUT_MS);
/* WDT initialization failed. Stop program execution */
if (result != CY_RSLT_SUCCESS)
{
CY_ASSERT(0);
}
}
int main(void)
{
cy_rslt_t result;
/* Initialize the device and board peripherals */
result = cybsp_init();
/* Board init failed. Stop program execution */
if (result != CY_RSLT_SUCCESS)
{
CY_ASSERT(0);
}
/* Initialize the User LED */
cyhal_gpio_init(CYBSP_USER_LED, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_STRONG,
CYBSP_LED_STATE_OFF);
/* Check the reason for device restart */
if (CYHAL_SYSTEM_RESET_WDT == cyhal_system_get_reset_reason())
{
/* It's WDT reset event - blink LED twice */
cyhal_gpio_write(CYBSP_USER_LED, CYBSP_LED_STATE_ON);
cyhal_system_delay_ms(100);
cyhal_gpio_write(CYBSP_USER_LED, CYBSP_LED_STATE_OFF);
cyhal_system_delay_ms(200);
cyhal_gpio_write(CYBSP_USER_LED, CYBSP_LED_STATE_ON);
cyhal_system_delay_ms(100);
cyhal_gpio_write(CYBSP_USER_LED, CYBSP_LED_STATE_OFF);
}
else
{
/* It's Power-On reset or XRES event - blink LED once */
cyhal_gpio_write(CYBSP_USER_LED, CYBSP_LED_STATE_ON);
cyhal_system_delay_ms(100);
cyhal_gpio_write(CYBSP_USER_LED, CYBSP_LED_STATE_OFF);;
cyhal_system_delay_ms(100);
}
/* Initialize WDT */
initialize_wdt();
/* Enable global interrupt */
__enable_irq();
for (;;)
{
#if (ENABLE_BLOCKING_FUNCTION)
while(1);
#else
/* Reset WDT */
cyhal_wdt_kick(&wdt_obj);
/* Constant delay of 1000ms */
cyhal_system_delay_ms(1000);
/* Invert the state of LED */
cyhal_gpio_toggle(CYBSP_USER_LED);
#endif
}
}
Initialize Basic WDT

Application Note 11 of 33 002-33887 Rev. *A
2022-05-25
Using the Watchdog Timer in XMC7000 family MCUs
Basic WDT
2.8 Clearing the basic WDT
Clearing the basic WDT is performed by setting the SERVICE[0] bit to ‘1’ in the SERVICE register. The firmware
must consider reading this bit until it is ‘0’ before writing ‘1’to this bit.
Servicing of the basic WDT counter must be done regularly to ensure a stable software flow. Independent of the
software concept used, the runtime calculation of software components is crucial to define the limits of the
counter to be cleared. The window mode makes it even more complex because a minimum time period needs
to be determined before which the software is not expected to service the basic WDT. This minimum time
period can be, for example, the minimum execution time of a low-priority main function.
Figure 6 shows an example of when the watchdog counter can be cleared within a system with different tasks.
The calculation of each service moment must consider the following conditions:
1. In the window mode, do not service the watchdog before the counter reaches the LOWER_LIMIT.
2. Must service the watchdog counter before reaching the UPPER_LIMIT to avoid a reset event.
The following conditions are defined:
•UPPER_LIMIT = 0x8000: Upper reset threshold is 1 second
•LOWER_LIMIT = 0x1000: Minimum reset threshold is 125 ms
•Task 1 duration: 100 ms
•Task 2 duration: 300 ms
•Task 3 duration: 200 ms
•Task 4 duration: 150 ms
•Task 5 duration: 200 ms
There are different sequences assumed with different timings:
•Sequence 1: tTask1 + tTask2 + tTask3 + tTask4 = 100 ms + 300 ms + 200 ms + 150 ms = 750 ms
•Sequence 2: tTask1 + tTask4 = 100 ms + 150 ms = 250 ms
•Sequence 3: tTask1 + tTask4 + tTask5 = 100 ms + 150 ms + 200 ms = 450 ms
In all cases, the following condition is met:
tLOWER_LIMIT < tSEQUENCE < tUPPER_LIMIT

Application Note 12 of 33 002-33887 Rev. *A
2022-05-25
Using the Watchdog Timer in XMC7000 family MCUs
Basic WDT
Sequence 2:
250ms
...
125ms
Time
LOWER_LIMIT = 0x1000
Counts value
0xFFFFFFFF
UPPER_LIMIT = 0x8000
Sequence 1:
750ms
Task 1
Task 2
Task 3
Task 4
Task 1
Task 4
Task 1
Task 4
Task 5
Task 1
Task 2
100ms 300ms 200ms 150ms 100ms 150ms 100ms 150ms 200ms 100ms 300ms
SERVICE
SERVICE SERVICE
Sequence 3:
450ms
Figure 6 Example of servicing the basic WDT in window mode
2.8.1 Use case
This section describes an example of clearing the basic WDT using the use case discussed in 2.7.1 Use case.
2.8.2 Example flow to clear the basic WDT
Figure 7 shows an example flow to clear the basic WDT.
Start
Clear Basic WDT Counter
Clear Basic WDT Interrupt
End
Set Service bit to clear WDT Counter
Unlock Basic WDT Registers
Lock Basic WDT Registers
(1)
(2)
(3)
(4)
(5)
Figure 7 Example flow to clear the basic WDT
2.9 Reset cause indication for the basic WDT
If the basic WDT is not serviced or serviced too early, a system-wide reset is issued. The reset event is stored in
the RESET_WDT[0] bit in the RES_CAUSE register.
Note: The hardware clears this bit during power-on reset (POR). It cannot be distinguished whether a
reset was caused by a LOWER_LIMIT or UPPER_LIMIT violation.

Application Note 13 of 33 002-33887 Rev. *A
2022-05-25
Using the Watchdog Timer in XMC7000 family MCUs
Basic WDT
2.10 Basic WDT registers
Table 2 Basic WDT registers
Name
Description
WDT_CTL
Watchdog Counter Control Register
WDT_LOWER_LIMIT
WDT Lower Limit Register
WDT_UPPER_LIMIT
WDT Upper Limit Register
WDT_WARN_LIMIT
WDT Warn Limit Register
WDT_CONFIG
WDT Configuration Register
WDT_CNT
WDT Count Register
WDT_LOCK
WDT Lock Register
WDT_SERVICE
WDT Service Register
WDT_INTR
WDT Interrupt Register
WDT_INTR_SET
WDT Interrupt Set Register
WDT_INTR_MASK
WDT Interrupt Mask Register
WDT_INTR_MASKED
WDT Interrupt Masked Register
CLK_ILO0_CONFIG
ILO0 configuration
RES_CAUSE
Reset cause observation register

Application Note 14 of 33 002-33887 Rev. *A
2022-05-25
Using the Watchdog Timer in XMC7000 family MCUs
Multi-counter WDT
3Multi-counter WDT
The MCWDT includes three subcounters: Subcounters 0, 1, and 2.
Subcounter 0 and Subcounter 1 are 16-bit counters, which behave like the basic WDT. Window mode and pre-
warning interrupts are supported. If any window timing violation occurs, a FAULT or a reset after a FAULT can
be generated if not handled within a timeout timing.
Subcounter 2 is a 32-bit counter, which can be configured to generate an interrupt when one of the pre-defined
counter bits toggles. Both types of counters operate during Active, Sleep, and DeepSleep modes. They are not
available during Hibernate mode.
Figure 8 illustrates the block diagram of the MCWDT with all three subcounters.
LFCLK
FAULT
Count <
MCWDTx_CTR1_LOWER_LIMIT
Count == 3 Count >=
MCWDTx_CTR1_UPPER_LIMIT
Count ==
MCWDTx_CTR1_WARN_LIMIT
16
MCWDTx_CNT0 (16-bit Counter)
Subcounter 0
Count <
MCWDTx_CTR0_LOWER_LIMIT
Count == 3 Count >=
MCWDTx_CTR0_UPPER_LIMIT
Count ==
MCWDTx_CTR0_WARN_LIMIT
Count
16
INTERRUPT
Timeout RESET
32
5
MCWDTx_CTR2_CONFIG.
BITS
MCWDT
Mode
Configuration
MCWDTx_INTR.CTR2_INT
MCWDTx_CTR2_CONFIG.ACT
ION
MCWDTx_CNT1 (16-bit Counter)
Subcounter 1
Count
MCWDTx_CNT2 (32-bit Counter)
Subcounter 2
Count
Figure 8 MCWDT block diagram
3.1 Source clock
The source clock that can be selected for MCWDT is LFCLK, which can be one of the following clock sources:
•ILO0/1: Internal low-speed oscillator (32.768 kHz nom.) with relatively poor accuracy
•WCO: Low-frequency watch crystal oscillator (32.768 kHz nom.)
•ECO: High-frequency crystal oscillator (4–33.33 MHz nom.)
3.2 Register protection in MCWDT
Changing the registers related to MCWDT requires an UNLOCK sequence of the MCWDT_LOCK[1:0] bits located
in the LOCK register. The following access sequence must be performed for unlocking the following:
Subcounter 2: CTR2_CTL, CTR2_CONFIG, and CTR2_CNT registers

Application Note 15 of 33 002-33887 Rev. *A
2022-05-25
Using the Watchdog Timer in XMC7000 family MCUs
Multi-counter WDT
Subcounter 0 and Subcounter 1: CTL, LOWER_LIMIT, UPPER_LIMIT, WARN_LIMIT, CONFIG, SERVICE, and CNT
registers
•MCWDT_LOCK = 1
•MCWDT_LOCK = 2
To protect the MCWDT registers, one single write access to the LOCK register is required:
•MCWDT_LOCK = 3
3.3 MCWDT interrupts
MCWDT supports different types of interrupts.
3.3.1 Pre-warning interrupt
Subcounter 0 and Subcounter 1 behave very similarly to the pre-warning interrupt of the Basic WDT. See 2.4
Warning interrupt. The only difference is that the WARN_LIMIT is a 16-bit value that can generate an interrupt
timing per the following equation:
   


The interrupt can be used as a pre-warning event that indicates that the MCWDT counter must be serviced
before a FAULT event is issued.
The interrupt is triggered to the related CPU when the WARN_ACTION[8] bit is set to ‘1’ in the CONFIG register.
The MCWDT can be serviced automatically by the AUTO_SERVICE[12] bit in the CONFIG register. This allows the
creation of a periodic interrupt if this counter is not needed as a watchdog.
3.3.2 MCWDT Subcounter 2 interrupt
Subcounter 2 interrupt behaves in a different way. A coarse-grained timing should be generated when a
dedicated pre-defined counter bit is toggled. The interrupt timing is calculated with the following equation:
   


Example:
LFCLK = ILO0 = 32.768 kHz
Toggle-Bit = Bit 12
    
 
The toggle-bit is configured by BITS[20:16] in the CTR2_CONFIG register. The interrupt is triggered to the
related CPU when the ACTION[0] bit is set to ‘1’ in the CTR2_CONFIG register.
3.4 Timeout mode
This mode is related to Subcounter 0 and Subcounter 1 only, and is similar to that of the basic WDT. See
2.5 Timeout mode. The difference is that the UPPER_LIMIT is a 16-bit value; when the subcounter matches with
the UPPER_LIMIT value, a FAULT is generated to be handled in the FAULT structures.

Application Note 16 of 33 002-33887 Rev. *A
2022-05-25
Using the Watchdog Timer in XMC7000 family MCUs
Multi-counter WDT
The UPPER_ACTION[1:0] bit field in the CONFIG register specifies how a FAULT is handled:
•No action is taken
•Generate only a FAULT to be handled by the FAULT structures
•Generate a FAULT and trigger a RESET if this FAULT is not handled in < 3 clock cycles
3.5 Window mode
This mode is related to Subcounter 0 and Subcounter 1 only, and is similar to that of the basic WDT. See
2.6 Window mode. The difference is that the LOWER_LIMIT is a 16-bit value, and if the subcounter is serviced
before the counter reaches the LOWER_LIMIT value, a FAULT is generated to be handled in the FAULT
structures.
The UPPER_ACTION[5:4] and LOWER_ACTION[1:0] bit fields in the CONFIG register specify how a FAULT is
handled as follows:
•No action is taken
•Generate only a FAULT to be handled by the FAULT structures
•Generate a FAULT and trigger a RESET if this FAULT is not handled in < 3 clk cycles
In Figure 9, the window mode is shown when FAULT_THEN_RESET is selected as LOWER_ACTION and
UPPER_ACTION. Four scenarios are possible while LOWER_ACTION, WARN_ACTION, and UPPER_ACTION are
activated accordingly:
•Counter is serviced between LOWER_LIMIT and WARN_LIMIT: This is the regular behavior of the MCWDT. No
WARN interrupt is issued and no RESET is done.
•Counter is serviced between WARN_LIMIT and UPPER_LIMIT: The service is done late; a WARN interrupt is
issued but no RESET is done.
•Counter is not serviced at all: A WARN interrupt is issued but even then, the CTR0/1_SERVICE bit is not set.
When the counter reaches the UPPER_LIMIT, a FAULT is issued. If the firmware does not handle this FAULT
to bring the system back into a safe state, a RESET is issued after a fixed number of LFCLK cycles.
•Counter is serviced before the LOWER_LIMIT is reached: The counter is serviced too early; a FAULT is issued
followed by a RESET in case the FAULT is not handled in time by the firmware.
Time
WARN_LIMIT
Counts value
LOWER_LIMIT
0xFFFF
CTR0/1_SERVICE
UPPER_LIMIT
CTR0/1_INT
interrupt 1
CTR0/1_SERVICE FAULT
CTR0/1_SERVICE
RESET
CTR0/1_INT
Interrupt 2
Figure 9 Subcounter 0/1 operation in window mode with FAULT and RESET action

Application Note 17 of 33 002-33887 Rev. *A
2022-05-25
Using the Watchdog Timer in XMC7000 family MCUs
Multi-counter WDT
3.6 Selecting the CPU
In a multi-CPU system, you should assign one MCWDT to a dedicated CPU to select the SLEEPDEEP for
controlling the counter behavior in the respective CPU low-power mode. The counter pauses while the
respective CPU is in a low-power mode if the SLEEPDEEP_PAUSE[30] bit is set to ‘1’ in the CTR2_CONFIG
register.
A single MCWDT is not intended to be used simultaneously by multiple CPUs because of the complexity
involved in coordination.
CPU_SEL[1:0] bits in the CPU_SELECT register are defined in Table 3.
Table 3 MCWDT assignment to cores
CPU_SEL[1:0]
CPU
0
CM0+
1
CM7_0
2
CM7_1
3.7 MCWDT settings
Figure 10 illustrates an example flow to configure the MCWDT.

Application Note 18 of 33 002-33887 Rev. *A
2022-05-25
Using the Watchdog Timer in XMC7000 family MCUs
Multi-counter WDT
De-initialize MCWDT Return register value to their default state
Initialize MCWDT Configure register value to user setting
Unlock MCWDT Registers
End
Lock MCWDT Registers
Enable MCWDT Interrupt
Enable MCWDT Counter
Configure Interrupt Priority
Enable Interrupt
System Interrupt Control
Enable NVIC Interrupt Controller
Setup Interrupt
Configure NVIC Priority Register
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
Configure MCWDT Parameters
Clear Fault Status
(1)
(2)
MCWDT Setting
Enable Fault MCWDT
Enable Fault Interrupt
(3)
(4)
Configure Interrupt
Configure Fault
Figure 10 Multi-counter WDT setting procedure
3.7.1 Use case
This section explains an example of the MCWDT using the following use case. The MCWDT is cleared in the main
task loop. The fault interrupt is triggered if the MCWDT is not cleared within the UPPER_LIMIT.
Use case:
•MCWDT number: 0
•CPU: CM7_0
•Subcounter 0
−LOWER_LIMIT: 0
−UPPER_LIMIT: 0xFFFF
−WARN_LIMIT: 1 second (32000, when clk_lf = 32 KHz)
−LOWER Action: None
−UPPER Action: None
−WARN Action: Interrupt
−Auto service: Enable

Application Note 19 of 33 002-33887 Rev. *A
2022-05-25
Using the Watchdog Timer in XMC7000 family MCUs
Multi-counter WDT
−Deep Sleep Pause: Enable
−Debug mode: Enable
•Subcounter 1: Same as Subcounter 0
•Subcounter 2:
−Action: Interrupt
−Auto service: Enable
−Deep Sleep Pause: Enable
−Debug mode: Enable
3.7.2 Configuring the MCWDT
You can configure the parameters in Peripherals tab of the Device Configurator as shown below; then
ModusToolbox™generates the corresponding code automatically.
Double-click design.modus to open the Device Configurator.

Application Note 20 of 33 002-33887 Rev. *A
2022-05-25
Using the Watchdog Timer in XMC7000 family MCUs
Multi-counter WDT
Code preview:
This code is auto-generated after the configuration in the Device Configurator.
Code Listing 2 shows an example program of the MCWDT configuration part. For details of the interrupt and
initial fault setting procedure, see the “Interrupt and Fault Report Structure” section in AN234226 listed in
Related documents.
Code Listing 2 Example program to configure MCWDT
cy_stc_sysint_t mcwdt_irq_cfg =
{
.intrSrc = ((NvicMux3_IRQn << 16) | srss_interrupt_mcwdt_0_IRQn),
.intrPriority = 2UL
};
int main(void)
{
cy_rslt_t result;
cy_en_mcwdt_status_t mcwdt_init_status = CY_MCWDT_SUCCESS;
/* Initialize the device and board peripherals */
result = cybsp_init() ;
/* BSP initialization failed. Stop program execution */
if (result != CY_RSLT_SUCCESS)
{
CY_ASSERT(0);
}