Texas Instruments Silicon Errata TMS320F28379S User manual

TMS320F28379S, TMS320F28377S,
TMS320F28376S, TMS320F28375S,
TMS320F28374S Delfino Microcontrollers
Silicon Errata
Literature Number: SPRZ422D
August 2014–Revised July 2016

2SPRZ422D–August 2014–Revised July 2016
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Table of Contents
Contents
1 Introduction......................................................................................................................... 4
2 Device and Development Support Tool Nomenclature.............................................................. 4
3 Device Markings .................................................................................................................. 5
4 Usage Notes and Known Design Exceptions to Functional Specifications.................................. 6
4.1 Usage Notes.............................................................................................................. 6
4.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask
Clear............................................................................................................ 6
4.2 Known Design Exceptions to Functional Specifications ............................................................ 7
5 Documentation Support ...................................................................................................... 23
Revision History.......................................................................................................................... 24

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List of Figures
List of Figures
1 Example of Device Markings............................................................................................... 5
2 Example of Device Nomenclature......................................................................................... 5
3 Single-Ended Input Model................................................................................................. 11
List of Tables
1 Determining Silicon Revision From Lot Trace Code ................................................................... 5
2 List of Usage Notes.......................................................................................................... 6
3 Table of Contents for Advisories........................................................................................... 7
4 List of Advisories............................................................................................................. 8
5 Memories Impacted by Advisory ......................................................................................... 20

4SPRZ422D–August 2014–Revised July 2016
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TMS320F2837xS Delfino™ Microcontrollers
Silicon Errata
SPRZ422D–August 2014–Revised July 2016
TMS320F2837xS Delfino™ Microcontrollers
Delfino, PowerPAD, TMS320, controlSUITE are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
1 Introduction
This document describes the silicon updates to the functional specifications for the TMS320F2837xS
microcontrollers (MCUs).
The updates are applicable to the following:
• 337-ball New Fine Pitch Ball Grid Array, ZWT Suffix
• 176-pin PowerPAD™ Thermally Enhanced Low-Profile Quad Flatpack, PTP Suffix
• 100-Pin PowerPAD Thermally Enhanced Thin Quad Flatpack, PZP Suffix
2 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
[TMS320] DSP devices and support tools. Each TMS320™ DSP commercial family member has one of
three prefixes: TMX, TMP, or TMS (for example, TMS320F28379S). Texas Instruments recommends two
of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent
evolutionary stages of product development from engineering prototypes (with TMX for devices and TMDX
for tools) through fully qualified production devices and tools (with TMS for devices and TMDS for tools).
TMX Experimental device that is not necessarily representative of the final device's electrical
specifications
TMP Final silicon die that conforms to the device's electrical specifications but has not
completed quality and reliability verification
TMS Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal
qualification testing
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PTP) and temperature range (for example, T).

PREFIX
TMS
TMX = experimental device
TMP = prototype device
TMS = qualified device
320
DEVICE FAMILY
320 = TMS320 MCU Family
F
TECHNOLOGY
F = Flash
28379S
DEVICE
28379S
28377S
28376S
28375S
28374S
PTP
PACKAGE TYPE
176
337-Ball ZWT New Fine Pitch Ball Grid Array (nFBGA)
-Pin PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack (HLQFP)
100-Pin PZP PowerPAD Thermally Enhanced Thin Quad Flatpack (HTQFP)
TEMPERATURE RANGE
T
−40°C to 105°C (T )
−40°C to 125°C (T )
−40°C to 125°C (T )
(Q refers to Q100 qualification for automotive applications.)
J
J
A
T
S
Q
=
=
=
YMLLLLS
YM
LLLL
S
$$
#
G4
Lot Trace Code
2-Digit Year/Month Code
Assembly Lot
Assembly Site Code
Wafer Fab Code as applicable
Silicon Revision Code
Green (Low Halogen and RoHS-compliant)
=
=
=
=
=
=
=
$$#-YMLLLLS
G4
F28379SPTPT
TMS320
Package
Pin 1
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3 Device Markings
Figure 1 provides an example of the 2837xS device markings and defines each of the markings. The
device revision can be determined by the symbols marked on the top of the package as shown in
Figure 1. Some prototype devices may have markings different from those illustrated. Figure 2 shows an
example of the device nomenclature.
Figure 1. Example of Device Markings
(1) Silicon Revision ID
Table 1. Determining Silicon Revision From Lot Trace Code
SILICON REVISION CODE SILICON REVISION REVID(1)
Address: 0x5D00C COMMENTS
B B 0x0002 This silicon revision is available as TMX.
C C 0x0003 This silicon revision is available as TMS.
Figure 2. Example of Device Nomenclature

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4 Usage Notes and Known Design Exceptions to Functional Specifications
4.1 Usage Notes
Usage notes highlight and describe particular situations where the device's behavior may not match
presumed or documented behavior. This may include behaviors that affect device performance or
functional correctness. These usage notes will be incorporated into future documentation updates for the
device (such as the device-specific data sheet), and the behaviors they describe will not be altered in
future silicon revisions.
Table 2 shows which silicon revision(s) are affected by each usage note.
Table 2. List of Usage Notes
TITLE SILICON REVISION(S)
AFFECTED
B C
PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear Yes Yes
4.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt
Mask Clear
Revision(s) Affected: B, C
Certain code sequences used for nested interrupts allow the CPU and PIE to enter an inconsistent state
that can trigger an unwanted interrupt. The conditions required to enter this state are:
1. A PIEACK clear is followed immediately by a global interrupt enable (EINT or asm(" CLRC INTM")).
2. A nested interrupt clears one or more PIEIER bits for its group.
Whether the unwanted interrupt is triggered depends on the configuration and timing of the other
interrupts in the system. This is expected to be a rare or nonexistent event in most applications. If it
happens, the unwanted interrupt will be the first one in the nested interrupt's PIE group, and will be
triggered after the nested interrupt re-enables CPU interrupts (EINT or asm(" CLRC INTM")).
Workaround: Add a NOP between the PIEACK write and the CPU interrupt enable. Example code is
shown below.
//Bad interrupt nesting code
PieCtrlRegs.PIEACK.all = 0xFFFF; //Enable nesting in the PIE
EINT; //Enable nesting in the CPU
//Good interrupt nesting code
PieCtrlRegs.PIEACK.all = 0xFFFF; //Enable nesting in the PIE
asm(" NOP"); //Wait for PIEACK to exit the pipeline
EINT; //Enable nesting in the CPU

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4.2 Known Design Exceptions to Functional Specifications
Table 3. Table of Contents for Advisories
Title ...................................................................................................................................... Page
Advisory —Analog Trim of Some TMX Devices ..................................................................................... 9
Advisory —ADC: ADC Post-Processing Block Limit Compare................................................................... 10
Advisory —ADC: ADC Offset Trim in Different Modes ............................................................................ 10
Advisory —ADC: Random Conversion Errors...................................................................................... 10
Advisory —ADC: ADC PPB Event Trigger (ADCxEVT) to ePWM Digital Compare Submodule ............................ 11
Advisory —ADC: 12-Bit Switch Resistance ........................................................................................ 11
Advisory —ADC: 12-Bit Input Capacitance When Switching Channel Groups ................................................ 11
Advisory —XRS may Toggle During Power Up .................................................................................... 12
Advisory —USB: USB DMA Event Triggers are not Supported.................................................................. 12
Advisory —VREG: VREG Will be Enabled During Power Up Irrespective of VREGENZ .................................... 12
Advisory —Flash: A Single-Bit ECC Error May Cause Endless Calls to Single-Bit-Error ISR ............................... 12
Advisory —ePIE: Spurious VCU Interrupt (ePIE 12.6) Can Occur When First Enabled...................................... 13
Advisory —eQEP: Position Counter Incorrectly Reset on Direction Change During Index .................................. 13
Advisory —PLL: May Not Lock on the First Lock Attempt........................................................................ 14
Advisory —SDFM: Data Filter Output Does Not Saturate at Maximum Value With Sinc3 and OSR = 256................ 15
Advisory —SDFM: Spurious Data Acknowledge Event When Data Filter is Configured and Enabled for the First Time 15
Advisory —SDFM: Spurious Data Acknowledge Event When Data Filter is Synchronized Using PWM FILRES Signal 15
Advisory —SDFM: Comparator Filter Module may Generate Spurious Over-Value and Under-Value Conditions ....... 16
Advisory —SDFM: Dynamically Changing Threshold Settings (LLT, HLT), Filter Type, or COSR Settings Will Trigger
Spurious Comparator Events................................................................................................. 16
Advisory —SDFM: Dynamically Changing Data Filter Settings (Such as Filter Type or DOSR) Will Trigger Spurious
Data Acknowledge Events.................................................................................................... 16
Advisory —FPU: FPU-to-CPU Register Move Operation Preceded by Any FPU 2p Operation............................. 17
Advisory —FPU: LUF, LVF Flags are Invalid for the EINVF32 and EISQRTF32 Instructions ............................... 18
Advisory —Memory: Prefetching Beyond Valid Memory ......................................................................... 20
Advisory —CMPSS: COMPxLATCH May Not Clear Properly Under Certain Conditions .................................... 21
Advisory —CMPSS: Ramp Generator May Not Start Under Certain Conditions .............................................. 21
Advisory —Boot ROM: Device Will Hang During Boot if X1 Clock Source is not Present ................................... 22

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Table 4 shows which silicon revision(s) are affected by each advisory.
Table 4. List of Advisories
TITLE SILICON REVISION(S)
AFFECTED
B C
Analog Trim of Some TMX Devices Yes
ADC: ADC Post-Processing Block Limit Compare Yes Yes
ADC: ADC Offset Trim in Different Modes Yes Yes
ADC: Random Conversion Errors Yes
ADC: ADC PPB Event Trigger (ADCxEVT) to ePWM Digital Compare Submodule Yes
ADC: 12-Bit Switch Resistance Yes
ADC: 12-Bit Input Capacitance When Switching Channel Groups Yes
XRS may Toggle During Power Up Yes
USB: USB DMA Event Triggers are not Supported Yes Yes
VREG: VREG Will be Enabled During Power Up Irrespective of VREGENZ Yes
Flash: A Single-Bit ECC Error May Cause Endless Calls to Single-Bit-Error ISR Yes Yes
ePIE: Spurious VCU Interrupt (ePIE 12.6) Can Occur When First Enabled Yes
eQEP: Position Counter Incorrectly Reset on Direction Change During Index Yes Yes
PLL: May Not Lock On the First Lock Attempt Yes Yes
SDFM: Data Filter Output Does Not Saturate at Maximum Value With Sinc3 and OSR = 256 Yes Yes
SDFM: Spurious Data Acknowledge Event When Data Filter is Configured and Enabled for the First
Time Yes Yes
SDFM: Spurious Data Acknowledge Event When Data Filter is Synchronized Using PWM FILRES
Signal Yes Yes
SDFM: Comparator Filter Module may Generate Spurious Over-Value and Under-Value Conditions Yes Yes
SDFM: Dynamically Changing Threshold Settings (LLT, HLT), Filter Type, or COSR Settings Will
Trigger Spurious Comparator Events Yes Yes
SDFM: Dynamically Changing Data Filter Settings (Such as Filter Type or DOSR) Will Trigger
Spurious Data Acknowledge Events Yes Yes
FPU: FPU-to-CPU Register Move Operation Preceded by Any FPU 2p Operation Yes Yes
FPU: LUF, LVF Flags are Invalid for the EINVF32 and EISQRTF32 Instructions Yes Yes
Memory: Prefetching Beyond Valid Memory Yes Yes
CMPSS: COMPxLATCH May Not Clear Properly Under Certain Conditions Yes Yes
CMPSS: Ramp Generator May Not Start Under Certain Conditions Yes Yes
Boot ROM: Device Will Hang During Boot if X1 Clock Source is not Present Yes

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Advisory Analog Trim of Some TMX Devices
Revision(s) Affected B
Details Some TMX samples may not have analog trims programmed. This could degrade the
performance of the ADC, buffered DAC, and internal oscillators. A value of all zeros in
these trim registers will have the following impact.
TRIM REGISTER IMPACT OF TRIM VALUE EQUAL TO ZERO
ADC reference AnalogSubsysRegs.ANAREFTRIMA Degraded performance of the ADC for all
specifications.
AnalogSubsysRegs.ANAREFTRIMB
AnalogSubsysRegs.ANAREFTRIMC
AnalogSubsysRegs.ANAREFTRIMD
ADC linearity AdcaRegs.ADCINLTRIM1-6 Degraded INL and DNL specifications of the ADC
in 16-bit mode. No workaround available.
AdcbRegs.ADCINLTRIM1-6
AdccRegs.ADCINLTRIM1-6
AdcdRegs.ADCINLTRIM1-6
ADC offset AdcaRegs.ADCOFFTRIM Degraded performance of the ADC offset error
specification.
AdcbRegs.ADCOFFTRIM
AdccRegs.ADCOFFTRIM
AdcdRegs.ADCOFFTRIM
Internal oscillator AnalogSubsysRegs.INTOSC1TRIM Degraded frequency accuracy and temperature
drift of the internal oscillators.
AnalogSubsysRegs.INTOSC2TRIM
Buffered DAC offset DacaRegs.DACTRIM Degraded offset error specification of the buffered
DAC. No workaround available.
DacbRegs.DACTRIM
DaccRegs.DACTRIM
Workaround(s) The following workarounds can be used for improved performance, though it still may not
meet data sheet specifications.
If the ADC reference trim registers contain all zeros, write the static reference trim value
of 0x7BDD to the reference trim register for all ADCs.
Missing ADC offset trim can be generated by following the instructions in the “ADC
Zero Offset Calibration” section of the TMS320F2837xS Delfino Microcontrollers
Technical Reference Manual.
If the internal oscillator trim contains all zeros, the user can adjust the lowest 10 bits of
the oscillator trim register between 1 (minimum) and 1023 (maximum) while observing
the system clock on the XCLOCKOUT pin.

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Advisory ADC: ADC Post-Processing Block Limit Compare
Revision(s) Affected B, C
Details When using a non-zero offset reference in the ADC post-processing block (PPB), the
resultant ADCPPBxRESULT can be signed. TRIPHI or TRIPLO limit compares do not
function correctly with this result if it is signed.
Workaround(s) When using the TRIPHI or TRIPLO limit compares, leave the offset reference as zero.
The offset reference (and zero compare) can be used as long as the limit compares are
disabled.
If the limit compares, the offset reference, and the zero-crossing compare are to be used
at the same time, then two PPBs can be used. Both PPBs should be configured to use
the same SOC. One PPB can implement the TRIPHI and/or TRIPLO limit compares
while the other can implement offset reference subtraction and zero-crossing detection.
Advisory ADC: ADC Offset Trim in Different Modes
Revision(s) Affected B, C
Details A different offset trim is required when switching between 12-bit and 16-bit resolution
and when switching between single-ended and differential signaling mode.
Workaround(s) Whenever setting the resolution or signal mode of the ADC, use the “AdcSetMode”
function in controlSUITE™. This will ensure the correct trims are loaded into the offset
trim register. Note that on start-up, trims will be loaded for 12-bit, single-ended operation.
Advisory ADC: Random Conversion Errors
Revision(s) Affected B
Details The ADC may have errors at a rate as high as 1 in 106.5 ADC conversions in 12-bit mode
and as high as 1 in 108.75 conversions in 16-bit mode. When a conversion error occurs, it
will be a significant random jump in the digital output of the ADC without a corresponding
change in the ADC input voltage, otherwise known as a “sparkle code”. The magnitude
of this jump will typically be in the range of 20 LSBs to 200 LSBs; however, larger or
smaller jumps may occur.
Workaround(s) For the revisions affected, the error rate will be lower than 1 error in 1014.5 ADC
conversions for both 12-bit mode and 16-bit mode when all of the following
configurations are used:
• The S+H duration is at least 320 ns
• ADCCLK is 40 MHz or less
• ADCCLK prescale is a whole number: /1.0, /2.0, /3.0, /4.0, /5.0, /6.0, /7.0, or /8.0
• The value of 0x7000 is written to memory locations 0x0000 743F, 0x0000 74BF,
0x0000 753F, and 0x0000 75BF (writing this value is only valid when the ADCCLK
prescale is a whole number).