Epson S1C17W18 User manual

Rev. 1.2
CMOS 16-BIT SINGLE CHIP MICROCONTROLLER
S1C17W18
Technical Manual

©
SEIKO EPSON CORPORATION 2021, All rights reserved.
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PREFACE
S1C17W18 TECHNICAL MANUAL Seiko Epson Corporation i
(Rev. 1.2)
Preface
This is a technical manual for designers and programmers who develop a product using the S1C17W18. This
document describes the functions of the IC, embedded peripheral circuit operations, and their control methods.
For the CPU functions and instructions, refer to the “S1C17 Family S1C17 Core Manual.” For the functions
and operations of the debugging tools, refer to the respective tool manuals. (Our “Products: Document Down-
loads” website provides the downloadable manuals.)
Notational conventions and symbols in this manual
Register address
Peripheral circuit chapters do not provide control register addresses. Refer to “Peripheral Circuit Area” in
the “Memory and Bus” chapter or “List of Peripheral Circuit Control Registers” in the Appendix.
Register and control bit names
In this manual, the register and control bit names are described as shown below to distinguish from signal
and pin names.
XXX register: Represents a register including its all bits.
XXX.YYY bit: Represents the one control bit YYY in the XXX register.
XXX.ZZZ[1:0] bits: Represents the two control bits ZZZ1 and ZZZ0 in the XXX register.
Register table contents and symbols
Initial: Value set at initialization
Reset: Initialization condition. The initialization condition depends on the reset group (H0, H1, or S0).
For more information on the reset groups, refer to “Initialization Conditions (Reset Groups)” in the
“Power Supply, Reset, and Clocks” chapter.
R/W: R = Read only bit
W = Write only bit
WP = Write only bit with a write protection using the MSCPROT.PROT[15:0] bits
R/W = Read/write bit
R/WP = Read/write bit with a write protection using the MSCPROT.PROT[15:0] bits
Control bit read/write values
This manual describes control bit values in a hexadecimal notation except for one-bit values (and except
when decimal or binary notation is required in terms of explanation). The values are described as shown
below according to the control bit width.
1 bit: 0 or 1
2 to 4 bits: 0x0 to 0xf
5 to 8 bits: 0x00 to 0xff
9 to 12 bits: 0x000 to 0xfff
13 to 16 bits: 0x0000 to 0xffff
Decimal: 0 to 9999...
Binary: 0b0000... to 0b1111...
Channel number
Multiple channels may be implemented in some peripheral circuits (e.g., 16-bit timer, etc.). The peripheral
circuit chapters use ‘n’ as the value that represents the channel number in the register and pin names regard-
less of the number of channel actually implemented. Normally, the descriptions are applied to all channels.
If there is a channel that has different functions from others, the channel number is specified clearly.
Example) T16_nCTL register of the 16-bit timer
If one channel is implemented (Ch.0 only): T16_nCTL = T16_0CTL only
If two channels are implemented (Ch.0 and Ch.1): T16_nCTL = T16_0CTL and T16_1CTL
For the number of channels implemented in the peripheral circuits of this IC, refer to “Features” in the
“Overview” chapter.

CONTENTS
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– Contents –
Preface......................................................................................................................................i
Notational conventions and symbols in this manual ................................................................i
1 Overview........................................................................................................................1-1
1.1 Features .......................................................................................................................... 1-1
1.2 Block Diagram................................................................................................................. 1-3
1.3 Pins ................................................................................................................................. 1-4
1.3.1 Pin Configuration Diagram (Package)............................................................... 1-4
1.3.2 Pad Configuration Diagram (Chip).................................................................... 1-7
1.3.3 Pin Descriptions................................................................................................ 1-8
2 Power Supply, Reset, and Clocks ...............................................................................2-1
2.1 Power Generator (PWG2)................................................................................................ 2-1
2.1.1 Overview ........................................................................................................... 2-1
2.1.2 Pins................................................................................................................... 2-1
2.1.3 Operations ........................................................................................................ 2-2
2.2 System Reset Controller (SRC)....................................................................................... 2-4
2.2.1 Overview ........................................................................................................... 2-4
2.2.2 Input Pin............................................................................................................ 2-4
2.2.3 Reset Sources .................................................................................................. 2-4
2.2.4 Initialization Conditions (Reset Groups)............................................................ 2-5
2.3 Clock Generator (CLG).................................................................................................... 2-6
2.3.1 Overview ........................................................................................................... 2-6
2.3.2 Input/Output Pins ............................................................................................. 2-7
2.3.3 Clock Sources .................................................................................................. 2-7
2.3.4 Operations ........................................................................................................ 2-9
2.4 Operating Mode ............................................................................................................. 2-14
2.4.1 Initial Boot Sequence....................................................................................... 2-14
2.4.2 Transition between Operating Modes.............................................................. 2-14
2.5 Interrupts........................................................................................................................ 2-16
2.6 Control Registers ........................................................................................................... 2-16
PWG2 Control Register............................................................................................................ 2-16
PWG2 Timing Control Register ................................................................................................ 2-17
PWG2 Interrupt Flag Register .................................................................................................. 2-17
PWG2 Interrupt Enable Register .............................................................................................. 2-17
CLG System Clock Control Register........................................................................................ 2-18
CLG Oscillation Control Register ............................................................................................. 2-19
CLG IOSC Control Register ..................................................................................................... 2-20
CLG OSC1 Control Register .................................................................................................... 2-20
CLG OSC3 Control Register .................................................................................................... 2-22
CLG Interrupt Flag Register ..................................................................................................... 2-23
CLG Interrupt Enable Register ................................................................................................. 2-23
CLG FOUT Control Register..................................................................................................... 2-24
CLG Oscillation Frequency Trimming Register ........................................................................ 2-25
3 CPU and Debugger ......................................................................................................3-1
3.1 Overview ......................................................................................................................... 3-1
3.2 CPU Core........................................................................................................................ 3-2
3.2.1 CPU Registers .................................................................................................. 3-2
3.2.2 Instruction Set .................................................................................................. 3-2
3.2.3 Reading PSR .................................................................................................... 3-2
3.2.4 I/O Area Reserved for the S1C17 Core ............................................................ 3-2
3.3 Debugger ........................................................................................................................ 3-2

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3.3.1 Debugging Functions........................................................................................ 3-2
3.3.2 Resource Requirements and Debugging Tools ................................................ 3-3
3.3.3 List of debugger input/output pins ................................................................... 3-3
3.3.4 External Connection ......................................................................................... 3-3
3.3.5 Flash Security Function .................................................................................... 3-4
3.4 Control Register .............................................................................................................. 3-4
MISC PSR Register ................................................................................................................... 3-4
Debug RAM Base Register ....................................................................................................... 3-5
4 Memory and Bus ..........................................................................................................4-1
4.1 Overview ......................................................................................................................... 4-1
4.2 Bus Access Cycle ........................................................................................................... 4-1
4.3 Flash Memory ................................................................................................................. 4-2
4.3.1 Flash Memory Pin ............................................................................................. 4-2
4.3.2 Flash Bus Access Cycle Setting....................................................................... 4-2
4.3.3 Flash Programming........................................................................................... 4-3
4.4 RAM ................................................................................................................................ 4-3
4.5 Display Data RAM ........................................................................................................... 4-3
4.6 Peripheral Circuit Control Registers................................................................................ 4-4
4.6.1 System-Protect Function.................................................................................. 4-9
4.7 Control Registers ............................................................................................................ 4-9
MISC System Protect Register ................................................................................................. 4-9
MISC IRAM Size Register.......................................................................................................... 4-9
FLASHC Flash Read Cycle Register ......................................................................................... 4-9
5 Interrupt Controller (ITC) .............................................................................................5-1
5.1 Overview ......................................................................................................................... 5-1
5.2 Vector Table .................................................................................................................... 5-1
5.2.1 Vector Table Base Address (TTBR)................................................................... 5-3
5.3 Initialization ..................................................................................................................... 5-3
5.4 Maskable Interrupt Control and Operations ................................................................... 5-3
5.4.1 Peripheral Circuit Interrupt Control................................................................... 5-3
5.4.2 ITC Interrupt Request Processing .................................................................... 5-4
5.4.3 Conditions to Accept Interrupt Requests by the CPU...................................... 5-4
5.5 NMI.................................................................................................................................. 5-4
5.6 Software Interrupts ......................................................................................................... 5-4
5.7 Interrupt Processing by the CPU .................................................................................... 5-5
5.8 Control Registers ............................................................................................................ 5-5
MISC Vector Table Address Low Register ................................................................................ 5-5
MISC Vector Table Address High Register................................................................................ 5-5
ITC Interrupt Level Setup Register x......................................................................................... 5-5
6 I/O Ports (PPORT).........................................................................................................6-1
6.1 Overview ......................................................................................................................... 6-1
6.2 I/O Cell Structure and Functions..................................................................................... 6-2
6.2.1 Schmitt Input .................................................................................................... 6-2
6.2.2 Over Voltage Tolerant Fail-Safe Type I/O Cell................................................... 6-2
6.2.3 Pull-Up/Pull-Down ............................................................................................ 6-2
6.2.4 CMOS Output and High Impedance State ....................................................... 6-3
6.3 Clock Settings................................................................................................................. 6-3
6.3.1 PPORT Operating Clock................................................................................... 6-3
6.3.2 Clock Supply in SLEEP Mode .......................................................................... 6-3
6.3.3 Clock Supply in DEBUG Mode......................................................................... 6-3
6.4 Operations ...................................................................................................................... 6-3

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6.4.1 Initialization ....................................................................................................... 6-3
6.4.2 Port Input/Output Control................................................................................. 6-5
6.5 Interrupts......................................................................................................................... 6-6
6.6 Control Registers ............................................................................................................ 6-6
PxPort Data Register................................................................................................................ 6-6
PxPort Enable Register ............................................................................................................ 6-7
PxPort Pull-up/down Control Register..................................................................................... 6-7
PxPort Interrupt Flag Register.................................................................................................. 6-8
PxPort Interrupt Control Register............................................................................................. 6-8
PxPort Chattering Filter Enable Register.................................................................................. 6-8
PxPort Mode Select Register ................................................................................................... 6-8
PxPort Function Select Register .............................................................................................. 6-9
P Port Clock Control Register ................................................................................................... 6-9
P Port Interrupt Flag Group Register........................................................................................ 6-10
6.7 Control Register and Port Function Configuration of this IC ......................................... 6-11
6.7.1 P0 Port Group.................................................................................................. 6-11
6.7.2 P1 Port Group.................................................................................................. 6-12
6.7.3 P2 Port Group.................................................................................................. 6-13
6.7.4 P3 Port Group.................................................................................................. 6-14
6.7.5 P4 Port Group.................................................................................................. 6-15
6.7.6 P5 Port Group.................................................................................................. 6-16
6.7.7 P6 Port Group.................................................................................................. 6-17
6.7.8 P7 Port Group.................................................................................................. 6-18
6.7.9 P8 Port Group.................................................................................................. 6-19
6.7.10 Pd Port Group................................................................................................ 6-20
6.7.11 Common Registers between Port Groups..................................................... 6-21
7 Universal Port Multiplexer (UPMUX)...........................................................................7-1
7.1 Overview ......................................................................................................................... 7-1
7.2 Peripheral Circuit I/O Function Assignment.................................................................... 7-1
7.3 Control Registers ............................................................................................................ 7-2
Pxy–xz Universal Port Multiplexer Setting Register................................................................... 7-2
8 Watchdog Timer (WDT)................................................................................................8-1
8.1 Overview ......................................................................................................................... 8-1
8.2 Clock Settings................................................................................................................. 8-1
8.2.1 WDT Operating Clock....................................................................................... 8-1
8.2.2 Clock Supply in DEBUG Mode......................................................................... 8-2
8.3 Operations ...................................................................................................................... 8-2
8.3.1 WDT Control ..................................................................................................... 8-2
8.3.2 Operations in HALT and SLEEP Modes............................................................ 8-2
8.4 Control Registers ............................................................................................................ 8-3
WDT Clock Control Register ..................................................................................................... 8-3
WDT Control Register ............................................................................................................... 8-3
9 Real-Time Clock (RTCA) ..............................................................................................9-1
9.1 Overview ......................................................................................................................... 9-1
9.2 Output Pin and External Connection .............................................................................. 9-1
9.2.1 Output Pin......................................................................................................... 9-1
9.3 Clock Settings................................................................................................................. 9-2
9.3.1 RTCA Operating Clock ..................................................................................... 9-2
9.3.2 Theoretical Regulation Function....................................................................... 9-2
9.4 Operations ...................................................................................................................... 9-3
9.4.1 RTCA Control ................................................................................................... 9-3
9.4.2 Real-Time Clock Counter Operations............................................................... 9-4

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9.4.3 Stopwatch Control............................................................................................ 9-4
9.4.4 Stopwatch Count-up Pattern ........................................................................... 9-4
9.5 Interrupts......................................................................................................................... 9-5
9.6 Control Registers ............................................................................................................ 9-6
RTC Control Register ................................................................................................................ 9-6
RTC Second Alarm Register ..................................................................................................... 9-7
RTC Hour/Minute Alarm Register.............................................................................................. 9-8
RTC Stopwatch Control Register .............................................................................................. 9-8
RTC Second/1Hz Register ........................................................................................................ 9-9
RTC Hour/Minute Register ....................................................................................................... 9-10
RTC Month/Day Register ......................................................................................................... 9-11
RTC Year/Week Register .......................................................................................................... 9-11
RTC Interrupt Flag Register...................................................................................................... 9-12
RTC Interrupt Enable Register ................................................................................................. 9-13
10 Supply Voltage Detector (SVD).................................................................................10-1
10.1 Overview ...................................................................................................................... 10-1
10.2 Input Pin and External Connection .............................................................................. 10-2
10.2.1 Input Pin......................................................................................................... 10-2
10.2.2 External Connection ...................................................................................... 10-2
10.3 Clock Settings.............................................................................................................. 10-2
10.3.1 SVD Operating Clock..................................................................................... 10-2
10.3.2 Clock Supply in SLEEP Mode ....................................................................... 10-2
10.3.3 Clock Supply in DEBUG Mode...................................................................... 10-3
10.4 Operations ................................................................................................................... 10-3
10.4.1 SVD Control ................................................................................................... 10-3
10.4.2 SVD Operations ............................................................................................. 10-4
10.5 SVD Interrupt and Reset .............................................................................................. 10-4
10.5.1 SVD Interrupt ................................................................................................. 10-4
10.5.2 SVD Reset...................................................................................................... 10-5
10.6 Control Registers ......................................................................................................... 10-5
SVD Clock Control Register ..................................................................................................... 10-5
SVD Control Register ............................................................................................................... 10-6
SVD Status and Interrupt Flag Register ................................................................................... 10-7
SVD Interrupt Enable Register ................................................................................................. 10-8
11 16-bit Timers (T16).....................................................................................................11-1
11.1 Overview ...................................................................................................................... 11-1
11.2 Input Pin....................................................................................................................... 11-1
11.3 Clock Settings.............................................................................................................. 11-2
11.3.1 T16 Operating Clock...................................................................................... 11-2
11.3.2 Clock Supply in SLEEP Mode ....................................................................... 11-2
11.3.3 Clock Supply in DEBUG Mode...................................................................... 11-2
11.3.4 Event Counter Clock...................................................................................... 11-2
11.4 Operations ................................................................................................................... 11-2
11.4.1 Initialization .................................................................................................... 11-2
11.4.2 Counter Underflow ........................................................................................ 11-3
11.4.3 Operations in Repeat Mode........................................................................... 11-3
11.4.4 Operations in One-shot Mode ....................................................................... 11-3
11.4.5 Counter Value Read....................................................................................... 11-4
11.5 Interrupt........................................................................................................................ 11-4
11.6 Control Registers ......................................................................................................... 11-4
T16 Ch.nClock Control Register ............................................................................................. 11-4
T16 Ch.nMode Register .......................................................................................................... 11-5
T16 Ch.nControl Register........................................................................................................ 11-5

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T16 Ch.nReload Data Register................................................................................................ 11-6
T16 Ch.nCounter Data Register .............................................................................................. 11-6
T16 Ch.nInterrupt Flag Register .............................................................................................. 11-6
T16 Ch.nInterrupt Enable Register.......................................................................................... 11-7
12 UART (UART)..............................................................................................................12-1
12.1 Overview ...................................................................................................................... 12-1
12.2 Input/Output Pins and External Connections .............................................................. 12-2
12.2.1 List of Input/Output Pins................................................................................ 12-2
12.2.2 External Connections .................................................................................... 12-2
12.2.3 Input Pin Pull-Up Function............................................................................. 12-2
12.2.4 Output Pin Open-Drain Output Function ...................................................... 12-2
12.3 Clock Settings.............................................................................................................. 12-2
12.3.1 UART Operating Clock .................................................................................. 12-2
12.3.2 Clock Supply in SLEEP Mode ....................................................................... 12-2
12.3.3 Clock Supply in DEBUG Mode...................................................................... 12-3
12.3.4 Baud Rate Generator..................................................................................... 12-3
12.4 Data Format ................................................................................................................. 12-3
12.5 Operations ................................................................................................................... 12-4
12.5.1 Initialization .................................................................................................... 12-4
12.5.2 Data Transmission ......................................................................................... 12-4
12.5.3 Data Reception .............................................................................................. 12-5
12.5.4 IrDA Interface................................................................................................. 12-6
12.6 Receive Errors.............................................................................................................. 12-7
12.6.1 Framing Error ................................................................................................. 12-7
12.6.2 Parity Error..................................................................................................... 12-8
12.6.3 Overrun Error ................................................................................................. 12-8
12.7 Interrupts...................................................................................................................... 12-8
12.8 Control Registers ......................................................................................................... 12-8
UART Ch.nClock Control Register .......................................................................................... 12-8
UART Ch.nMode Register....................................................................................................... 12-9
UART Ch.nBaud–Rate Register ............................................................................................. 12-10
UART Ch.nControl Register ................................................................................................... 12-10
UART Ch.nTransmit Data Register ......................................................................................... 12-11
UART Ch.nReceive Data Register.......................................................................................... 12-11
UART Ch.nStatus and Interrupt Flag Register ....................................................................... 12-11
UART Ch.nInterrupt Enable Register...................................................................................... 12-12
13 Synchronous Serial Interface (SPIA)........................................................................13-1
13.1 Overview ...................................................................................................................... 13-1
13.2 Input/Output Pins and External Connections .............................................................. 13-2
13.2.1 List of Input/Output Pins................................................................................ 13-2
13.2.2 External Connections .................................................................................... 13-2
13.2.3 Pin Functions in Master Mode and Slave Mode............................................ 13-3
13.2.4 Input Pin Pull-Up/Pull-Down Function .......................................................... 13-3
13.3 Clock Settings.............................................................................................................. 13-3
13.3.1 SPIA Operating Clock.................................................................................... 13-3
13.3.2 Clock Supply in DEBUG Mode...................................................................... 13-4
13.3.3 SPI Clock (SPICLKn) Phase and Polarity ...................................................... 13-4
13.4 Data Format ................................................................................................................. 13-5
13.5 Operations ................................................................................................................... 13-5
13.5.1 Initialization .................................................................................................... 13-5
13.5.2 Data Transmission in Master Mode ............................................................... 13-5
13.5.3 Data Reception in Master Mode.................................................................... 13-7

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13.5.4 Terminating Data Transfer in Master Mode.................................................... 13-8
13.5.5 Data Transfer in Slave Mode.......................................................................... 13-8
13.5.6 Terminating Data Transfer in Slave Mode ..................................................... 13-10
13.6 Interrupts..................................................................................................................... 13-10
13.7 Control Registers ........................................................................................................ 13-11
SPIA Ch.nMode Register ....................................................................................................... 13-11
SPIA Ch.nControl Register..................................................................................................... 13-12
SPIA Ch.nTransmit Data Register .......................................................................................... 13-13
SPIA Ch.nReceive Data Register ........................................................................................... 13-13
SPIA Ch.nInterrupt Flag Register ........................................................................................... 13-13
SPIA Ch.nInterrupt Enable Register ....................................................................................... 13-14
14 I2C (I2C).......................................................................................................................14-1
14.1 Overview ...................................................................................................................... 14-1
14.2 Input/Output Pins and External Connections .............................................................. 14-2
14.2.1 List of Input/Output Pins................................................................................ 14-2
14.2.2 External Connections .................................................................................... 14-2
14.3 Clock Settings.............................................................................................................. 14-3
14.3.1 I2C Operating Clock ...................................................................................... 14-3
14.3.2 Clock Supply in DEBUG Mode...................................................................... 14-3
14.3.3 Baud Rate Generator..................................................................................... 14-3
14.4 Operations ................................................................................................................... 14-4
14.4.1 Initialization .................................................................................................... 14-4
14.4.2 Data Transmission in Master Mode ............................................................... 14-5
14.4.3 Data Reception in Master Mode.................................................................... 14-7
14.4.4 10-bit Addressing in Master Mode ................................................................ 14-9
14.4.5 Data Transmission in Slave Mode................................................................. 14-10
14.4.6 Data Reception in Slave Mode ..................................................................... 14-12
14.4.7 Slave Operations in 10-bit Address Mode.................................................... 14-14
14.4.8 Automatic Bus Clearing Operation ............................................................... 14-14
14.4.9 Error Detection.............................................................................................. 14-15
14.5 Interrupts..................................................................................................................... 14-16
14.6 Control Registers ........................................................................................................ 14-17
I2C Ch.nClock Control Register............................................................................................. 14-17
I2C Ch.nMode Register.......................................................................................................... 14-18
I2C Ch.nBaud-Rate Register.................................................................................................. 14-18
I2C Ch.nOwn Address Register ............................................................................................. 14-18
I2C Ch.nControl Register ....................................................................................................... 14-19
I2C Ch.nTransmit Data Register............................................................................................. 14-20
I2C Ch.nReceive Data Register.............................................................................................. 14-20
I2C Ch.nStatus and Interrupt Flag Register ........................................................................... 14-20
I2C Ch.nInterrupt Enable Register ......................................................................................... 14-21
15 16-bit PWM Timers (T16B) ........................................................................................15-1
15.1 Overview ...................................................................................................................... 15-1
15.2 Input/Output Pins......................................................................................................... 15-2
15.3 Clock Settings.............................................................................................................. 15-3
15.3.1 T16B Operating Clock ................................................................................... 15-3
15.3.2 Clock Supply in SLEEP Mode ....................................................................... 15-3
15.3.3 Clock Supply in DEBUG Mode...................................................................... 15-3
15.3.4 Event Counter Clock...................................................................................... 15-3
15.4 Operations ................................................................................................................... 15-4
15.4.1 Initialization .................................................................................................... 15-4
15.4.2 Counter Block Operations ............................................................................. 15-5
15.4.3 Comparator/Capture Block Operations......................................................... 15-8

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15.4.4 TOUT Output Control ................................................................................... 15-16
15.5 Interrupt....................................................................................................................... 15-22
15.6 Control Registers ........................................................................................................ 15-22
T16B Ch.nClock Control Register.......................................................................................... 15-22
T16B Ch.nCounter Control Register ...................................................................................... 15-23
T16B Ch.nMax Counter Data Register................................................................................... 15-24
T16B Ch.nTimer Counter Data Register................................................................................. 15-24
T16B Ch.nCounter Status Register........................................................................................ 15-25
T16B Ch.nInterrupt Flag Register........................................................................................... 15-26
T16B Ch.nInterrupt Enable Register ...................................................................................... 15-27
T16B Ch.nComparator/Capture mControl Register.............................................................. 15-28
T16B Ch.nCompare/Capture mData Register....................................................................... 15-30
16 Sound Generator (SNDA) ..........................................................................................16-1
16.1 Overview ...................................................................................................................... 16-1
16.2 Output Pins and External Connections........................................................................ 16-2
16.2.1 List of Output Pins ......................................................................................... 16-2
16.2.2 Output Pin Drive Mode .................................................................................. 16-2
16.2.3 External Connections .................................................................................... 16-2
16.3 Clock Settings.............................................................................................................. 16-3
16.3.1 SNDA Operating Clock.................................................................................. 16-3
16.3.2 Clock Supply in SLEEP Mode ....................................................................... 16-3
16.3.3 Clock Supply in DEBUG Mode...................................................................... 16-3
16.4 Operations ................................................................................................................... 16-3
16.4.1 Initialization .................................................................................................... 16-3
16.4.2 Buzzer Output in Normal Buzzer Mode......................................................... 16-3
16.4.3 Buzzer Output in One-shot Buzzer Mode...................................................... 16-6
16.4.4 Output in Melody Mode................................................................................. 16-7
16.5 Interrupts...................................................................................................................... 16-9
16.6 Control Registers ......................................................................................................... 16-9
SNDA Clock Control Register .................................................................................................. 16-9
SNDA Select Register ............................................................................................................. 16-10
SNDA Control Register............................................................................................................ 16-11
SNDA Data Register................................................................................................................ 16-11
SNDA Interrupt Flag Register.................................................................................................. 16-12
SNDA Interrupt Enable Register.............................................................................................. 16-13
17 IR Remote Controller (REMC2) ................................................................................17-1
17.1 Overview ...................................................................................................................... 17-1
17.2 Input/Output Pins and External Connections .............................................................. 17-1
17.2.1 Output Pin...................................................................................................... 17-1
17.2.2 External Connections .................................................................................... 17-2
17.3 Clock Settings.............................................................................................................. 17-2
17.3.1 REMC2 Operating Clock ............................................................................... 17-2
17.3.2 Clock Supply in SLEEP Mode ....................................................................... 17-2
17.3.3 Clock Supply in DEBUG Mode...................................................................... 17-2
17.4 Operations ................................................................................................................... 17-2
17.4.1 Initialization .................................................................................................... 17-2
17.4.2 Data Transmission Procedures...................................................................... 17-3
17.4.3 REMO Output Waveform ............................................................................... 17-3
17.4.4 Continuous Data Transmission and Compare Buffers................................... 17-5
17.5 Interrupts...................................................................................................................... 17-6
17.6 Application Example: Driving EL Lamp........................................................................ 17-7
17.7 Control Registers ......................................................................................................... 17-7

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REMC2 Clock Control Register................................................................................................ 17-7
REMC2 Data Bit Counter Control Register .............................................................................. 17-8
REMC2 Data Bit Counter Register........................................................................................... 17-9
REMC2 Data Bit Active Pulse Length Register....................................................................... 17-10
REMC2 Data Bit Length Register............................................................................................ 17-10
REMC2 Status and Interrupt Flag Register............................................................................. 17-10
REMC2 Interrupt Enable Register ........................................................................................... 17-11
REMC2 Carrier Waveform Register......................................................................................... 17-11
REMC2 Carrier Modulation Control Register .......................................................................... 17-12
18 LCD Driver (LCD8B)...................................................................................................18-1
18.1 Overview ...................................................................................................................... 18-1
18.2 Output Pins and External Connections........................................................................ 18-2
18.2.1 List of Output Pins ......................................................................................... 18-2
18.2.2 External Connections .................................................................................... 18-2
18.3 Clock Settings.............................................................................................................. 18-3
18.3.1 LCD8B Operating Clock ................................................................................ 18-3
18.3.2 Clock Supply in SLEEP Mode ....................................................................... 18-3
18.3.3 Clock Supply in DEBUG Mode...................................................................... 18-3
18.3.4 Frame Frequency........................................................................................... 18-3
18.4 LCD Power Supply....................................................................................................... 18-4
18.4.1 Internal Generation Mode .............................................................................. 18-4
18.4.2 External Voltage Application Mode 1............................................................. 18-4
18.4.3 External Voltage Application Mode 2............................................................. 18-5
18.4.4 LCD Voltage Regulator Settings .................................................................... 18-5
18.4.5 LCD Voltage Booster Setting......................................................................... 18-5
18.4.6 LCD Contrast Adjustment.............................................................................. 18-5
18.5 Operations ................................................................................................................... 18-6
18.5.1 Initialization .................................................................................................... 18-6
18.5.2 Display On/Off ............................................................................................... 18-6
18.5.3 Inverted Display ............................................................................................. 18-7
18.5.4 Drive Duty Switching ..................................................................................... 18-7
18.5.5 Drive Waveforms............................................................................................ 18-7
18.5.6 Partial Common Output Drive....................................................................... 18-11
18.5.7 n-Segment-Line Inverse AC Drive ................................................................ 18-11
18.6 Display Data RAM ....................................................................................................... 18-11
18.6.1 Display Area Selection.................................................................................. 18-11
18.6.2 Segment Pin Assignment ............................................................................. 18-12
18.6.3 Common Pin Assignment ............................................................................. 18-12
18.7 Interrupt....................................................................................................................... 18-22
18.8 Control Registers ........................................................................................................ 18-22
LCD8B Clock Control Register................................................................................................ 18-22
LCD8B Control Register.......................................................................................................... 18-23
LCD8B Timing Control Register 1........................................................................................... 18-23
LCD8B Timing Control Register 2........................................................................................... 18-24
LCD8B Power Control Register............................................................................................... 18-24
LCD8B Display Control Register............................................................................................. 18-25
LCD8B COM Pin Control Register 0 ....................................................................................... 18-26
LCD8B Interrupt Flag Register ................................................................................................ 18-26
LCD8B Interrupt Enable Register............................................................................................ 18-26
19 R/F Converter (RFC) ..................................................................................................19-1
19.1 Overview ...................................................................................................................... 19-1
19.2 Input/Output Pins and External Connections .............................................................. 19-2
19.2.1 List of Input/Output Pins................................................................................ 19-2

CONTENTS
xSeiko Epson Corporation S1C17W18 TECHNICAL MANUAL
(Rev. 1.2)
19.2.2 External Connections .................................................................................... 19-2
19.3 Clock Settings.............................................................................................................. 19-3
19.3.1 RFC Operating Clock..................................................................................... 19-3
19.3.2 Clock Supply in SLEEP Mode ....................................................................... 19-3
19.3.3 Clock Supply in DEBUG Mode...................................................................... 19-3
19.4 Operations ................................................................................................................... 19-3
19.4.1 Initialization .................................................................................................... 19-3
19.4.2 Operating Modes........................................................................................... 19-4
19.4.3 RFC Counters ................................................................................................ 19-4
19.4.4 Converting Operations and Control Procedure ............................................. 19-5
19.4.5 CR Oscillation Frequency Monitoring Function............................................. 19-7
19.5 Interrupts...................................................................................................................... 19-7
19.6 Control Registers ......................................................................................................... 19-8
RFC Ch.nClock Control Register ............................................................................................ 19-8
RFC Ch.nControl Register....................................................................................................... 19-8
RFC Ch.nOscillation Trigger Register...................................................................................... 19-9
RFC Ch.nMeasurement Counter Low and High Registers .................................................... 19-10
RFC Ch.nTime Base Counter Low and High Registers ......................................................... 19-10
RFC Ch.nInterrupt Flag Register............................................................................................ 19-11
RFC Ch.nInterrupt Enable Register........................................................................................ 19-11
20 12-bit A/D Converter (ADC12A)................................................................................20-1
20.1 Overview ...................................................................................................................... 20-1
20.2 Input Pins and External Connections........................................................................... 20-2
20.2.1 List of Input Pins............................................................................................ 20-2
20.2.2 External Connections .................................................................................... 20-2
20.3 Clock Settings.............................................................................................................. 20-2
20.3.1 ADC12A Operating Clock.............................................................................. 20-2
20.3.2 Sampling Time............................................................................................... 20-2
20.4 Operations ................................................................................................................... 20-3
20.4.1 Initialization .................................................................................................... 20-3
20.4.2 Conversion Start Trigger Source.................................................................... 20-3
20.4.3 Conversion Mode and Analog Input Pin Settings.......................................... 20-4
20.4.4 A/D Conversion Operations and Control Procedures.................................... 20-4
20.5 Interrupts...................................................................................................................... 20-6
20.6 Control Registers ......................................................................................................... 20-6
ADC12A Ch.nControl Register ................................................................................................ 20-6
ADC12A Ch.nTrigger/Analog Input Select Register ................................................................ 20-7
ADC12A Ch.nConfiguration Register ...................................................................................... 20-8
ADC12A Ch.nInterrupt Flag Register ...................................................................................... 20-9
ADC12A Ch.nInterrupt Enable Register ................................................................................. 20-10
ADC12A Ch.nResult Register m............................................................................................. 20-10
21 Temperature Sensor/Reference Voltage Generator (TSRVR)................................21-1
21.1 Overview ...................................................................................................................... 21-1
21.2 Output Pin and External Connections ......................................................................... 21-1
21.2.1 Output Pin...................................................................................................... 21-1
21.2.2 External Connections .................................................................................... 21-2
21.3 Operations ................................................................................................................... 21-2
21.3.1 Reference Voltage Setting ............................................................................. 21-2
21.3.2 Temperature Sensor Setting .......................................................................... 21-2
21.4 Control Registers ......................................................................................................... 21-3
TSRVR Ch.nTemperature Sensor Control Register................................................................. 21-3
TSRVR Ch.nReference Voltage Generator Control Register................................................... 21-3

CONTENTS
S1C17W18 TECHNICAL MANUAL Seiko Epson Corporation xi
(Rev. 1.2)
22 Multiplier/Divider (COPRO2).....................................................................................22-1
22.1 Overview ...................................................................................................................... 22-1
22.2 Operation Mode and Output Mode.............................................................................. 22-1
22.3 Multiplication................................................................................................................ 22-2
22.4 Division......................................................................................................................... 22-3
22.5 MAC ............................................................................................................................. 22-5
22.6 Reading Operation Results .......................................................................................... 22-7
23 Electrical Characteristics .........................................................................................23-1
23.1 Absolute Maximum Ratings ......................................................................................... 23-1
23.2 Recommended Operating Conditions ......................................................................... 23-1
23.3 Current Consumption................................................................................................... 23-2
23.4 System Reset Controller (SRC) Characteristics........................................................... 23-4
23.5 Clock Generator (CLG) Characteristics........................................................................ 23-4
23.6 Flash Memory Characteristics ..................................................................................... 23-7
23.7 Input/Output Port (PPORT) Characteristics ................................................................. 23-7
23.8 Supply Voltage Detector (SVD) Characteristics ........................................................... 23-8
23.9 UART (UART) Characteristics ...................................................................................... 23-9
23.10 Synchronous Serial Interface (SPIA) Characteristics ................................................ 23-10
23.11 I2C (I2C) Characteristics............................................................................................ 23-11
23.12 LCD Driver (LCD8B) Characteristics ......................................................................... 23-11
23.13 R/F Converter (RFC) Characteristics......................................................................... 23-16
23.14 12-bit A/D Converter (ADC12A) Characteristics ....................................................... 23-17
23.15 Temperature Sensor/Reference Voltage Generator (TSRVR) Characteristics........... 23-18
24 Basic External Connection Diagram .......................................................................24-1
25 Package......................................................................................................................25-1
Appendix A List of Peripheral Circuit Control Registers ......................................... AP-A-1
0x4000–0x4008 Misc Registers (MISC)................................................................. AP-A-1
0x4020–0x4026 Power Generator (PWG2)............................................................ AP-A-1
0x4040–0x4052 Clock Generator (CLG) ................................................................ AP-A-1
0x4080–0x4096 Interrupt Controller (ITC).............................................................. AP-A-3
0x40a0–0x40a2 Watchdog Timer (WDT) ............................................................... AP-A-4
0x40c0–0x40d2 Real-time Clock (RTCA)............................................................... AP-A-4
0x4100–0x4106 Supply Voltage Detector (SVD).................................................... AP-A-6
0x4160–0x416c 16-bit Timer (T16) Ch.0................................................................ AP-A-6
0x41b0 Flash Controller (FLASHC) .......................................................... AP-A-7
0x4200–0x42e2 I/O Ports (PPORT) ....................................................................... AP-A-7
0x4300–0x431e Universal Port Multiplexer (UPMUX)........................................... AP-A-12
0x4380–0x438e UART (UART) Ch.0 ..................................................................... AP-A-14
0x43a0–0x43ac 16-bit Timer (T16) Ch.1............................................................... AP-A-15
0x43b0–0x43ba Synchronous Serial Interface (SPIA) Ch.0.................................. AP-A-16
0x43c0–0x43d2 I2C (I2C) ...................................................................................... AP-A-16
0x5000–0x501a 16-bit PWM Timer (T16B) Ch.0 .................................................. AP-A-18
0x5040–0x505a 16-bit PWM Timer (T16B) Ch.1 .................................................. AP-A-19
0x5080–0x509a 16-bit PWM Timer (T16B) Ch.2 .................................................. AP-A-20
0x5200–0x520e UART (UART) Ch.1 ..................................................................... AP-A-22
0x5260–0x526c 16-bit Timer (T16) Ch.2............................................................... AP-A-23
0x5270–0x527a Synchronous Serial Interface (SPIA) Ch.1 .................................. AP-A-23
0x5300–0x530a Sound Generator (SNDA) ........................................................... AP-A-24
0x5320–0x5332 IR Remote Controller (REMC2)................................................... AP-A-24

CONTENTS
xii Seiko Epson Corporation S1C17W18 TECHNICAL MANUAL
(Rev. 1.2)
0x5400–0x5412 LCD Driver (LCD8B).................................................................... AP-A-25
0x5440–0x5450 R/F Converter (RFC) Ch.0 .......................................................... AP-A-26
0x5460–0x5470 R/F Converter (RFC) Ch.1 .......................................................... AP-A-27
0x5480–0x548c 16-bit Timer (T16) Ch.3............................................................... AP-A-28
0x54a2–0x54ba 12-bit A/D Converter (ADC12A).................................................. AP-A-29
0x54c0–0x54c2 Temperature Sensor/Reference Voltage Generator (TSRVR) ..... AP-A-30
0xffff90 Debugger (DBG) ......................................................................... AP-A-30
Appendix B Power Saving .......................................................................................... AP-B-1
B.1 Operating Status Configuration Examples for Power Saving...................................... AP-B-1
B.2 Other Power Saving Methods ..................................................................................... AP-B-2
Appendix C Mounting Precautions ............................................................................ AP-C-1
Appendix D Measures Against Noise ........................................................................ AP-D-1
Appendix E Initialization Routine ............................................................................... AP-E-1
Revision History

1 OVERVIEW
S1C17W18 TECHNICAL MANUAL Seiko Epson Corporation 1-1
(Rev. 1.2)
1 Overview
The S1C17W18 is a 16-bit MCU that features low-voltage operation from 1.2 V even though Flash memory is in-
cluded. The embedded high-efficiency DC-DC converter generates the constant-voltage to drive the IC with lower
power consumption than 4-bit MCUs. This IC includes a real-time clock, a stopwatch, an LCD driver, a tempera-
ture sensor, an A/D converter, and a PWM timer capable of being used to generate drive waveforms for a motor
driver as well as a high-performance 16-bit CPU. It is suitable for battery-driven applications that require an LCD
display and a temperature measurement function.
1.1 Features
Table 1.1.1 Features
Model S1C17W18
CPU
CPU core Seiko Epson original 16-bit RISC CPU core S1C17
Other On-chip debugger
Embedded Flash memory
Capacity 128K bytes (for both instructions and data)
Erase/program count 1,000 times (min.) *Programming by the debugging tool ICDmini
Other Security function to protect from reading/programming by ICDmini
On-board programming function using ICDmini
Flash programming voltage can be generated internally.
Embedded RAM
Capacity 8K bytes
Embedded display RAM
Capacity 96 bytes
Clock generator (CLG)
System clock source 4 sources (IOSC/OSC1/OSC3/EXOSC)
System clock frequency (operating frequency) 1.1 MHz (max.) VDD = 1.2 to 1.6 V
4.2 MHz (max.) VDD = 1.6 to 3.6 V
IOSC oscillator circuit (boot clock source) 700 kHz (typ.) embedded oscillator
23 µs (max.) starting time (time from cancelation of SLEEP state to vector table read
by the CPU)
OSC1 oscillator circuit 32.768 kHz (typ.) crystal oscillator
Oscillation stop detection circuit included
OSC3 oscillator circuit 4.2 MHz (max.) crystal/ceramic oscillator
250, 384, 500 kHz, 1, 2, and 4 MHz-switchable embedded oscillator
2.1 MHz (max.) CR oscillator (an external R is required)
EXOSC clock input 4.2 MHz (max.) square or sine wave input
Other Configurable system clock division ratio
Configurable system clock used at wake up from SLEEP state
Operating clock frequency for the CPU and all peripheral circuits is selectable.
I/O port (PPORT)
Number of general-purpose I/O ports Input/output port: 67 bits (max., 128-pin package or chip)
56 bits (max., 80-pin package)
48 bits (max., 64-pin package)
Output port: 1 bit (max.)
Pins are shared with the peripheral I/O.
Number of input interrupt ports 63 bits (max., 128-pin package or chip)
52 bits (max., 80-pin package)
44 bits (max., 64-pin package)
Number of ports that support universal port
multiplexer (UPMUX)
32 bits (max., 128-pin package or chip)
29 bits (max., 80-pin package)
24 bits (max., 64-pin package)
A peripheral circuit I/O function selected via software can be assigned to each port.
Timers
Watchdog timer (WDT) Generates NMI or watchdog timer reset.
Real-time clock (RTCA) 128–1 Hz counter, second/minute/hour/day/day of the week/month/year counters
Theoretical regulation function for 1-second correction
Alarm and stopwatch functions
16-bit timer (T16) 4 channels
Generates the SPIA master clocks and the ADC12A operating clock/trigger signal.
16-bit PWM timer (T16B) 3 channels
Event counter/capture function
PWM waveform generation function
Number of PWM output or capture input ports: 2 ports/channel

1 OVERVIEW
1-2 Seiko Epson Corporation S1C17W18 TECHNICAL MANUAL
(Rev. 1.2)
Model S1C17W18
Supply voltage detector (SVD)
Detection level 30 levels (1.2 to 3.6 V)
Other Intermittent operation mode
Generates an interrupt or reset according to the detection level evaluation.
Serial interfaces
UART (UART) 2 channels
Baud-rate generator included, IrDA1.0 supported
Synchronous serial interface (SPIA) 2 channels
2 to 16-bit variable data length
The 16-bit timer (T16) can be used for the baud-rate generator in master mode.
I2C (I2C) 1 channel
Baud-rate generator included
Sound generator (SNDA)
Buzzer output function 512 Hz to 16 kHz output frequencies
One-shot output function
Melody generation function Pitch: 128 Hz to 16 kHz ≈C3 to C6
Duration: 7 notes/rests (Half note/rest to thirty-second note/rest)
Tempo: 16 tempos (30 to 480)
Tie/slur may be specified.
IR remote controller (REMC2)
Number of transmitter channels 1 channel
Other EL lamp drive waveform can be generated for an application example.
LCD driver (LCD8B)
LCD output 44 SEG ×5–8 COM (max.), 48 SEG ×1–4 COM (max.) (128-pin package or chip)
28 SEG ×5–8 COM (max.), 32 SEG ×1–4 COM (max.) (80-pin package)
20 SEG ×5–8 COM (max.), 24 SEG ×1–4 COM (max.) (64-pin package)
LCD contrast 32 levels
Other 1/4 or 1/3 bias power supply included, external voltage can be applied.
R/F converter (RFC)
Conversion method CR oscillation type with 24-bit counters
Number of conversion channels 2 channels (Up to two sensors can be connected to each channel.)
Supported sensors DC-bias resistive sensors, AC-bias resistive sensors (Ch.0 only)
12-bit A/D converter (ADC12A)
Conversion method Successive approximation type
Resolution 12 bits
Number of conversion channels 1 channel
Number of analog signal inputs 8 ports/channel (The temperature sensor output is connected to a port.)
Temperature sensor/reference voltage generator (TSRVR)
Temperature sensor circuit Sensor output can be measured using ADC12A.
Reference voltage generator Reference voltage for ADC12A is selectable from 2.0 V, 2.5 V, VDD, and external input.
Multiplier/divider (COPRO2)
Arithmetic functions 16-bit ×16-bit multiplier
16-bit ×16-bit + 32-bit multiply and accumulation unit
32-bit ÷32-bit divider
Reset
#RESET pin Reset when the reset pin is set to low.
Power-on reset Reset at power on.
Key entry reset Reset when the P00 to P01/P02/P03 keys are pressed simultaneously (can be en-
abled/disabled using a register).
Watchdog timer reset Reset when the watchdog timer overflows (can be enabled/disabled using a register).
Supply voltage detector reset Reset when the supply voltage detector detects the set voltage level (can be enabled/
disabled using a register).
Interrupt
Non-maskable interrupt 4 systems (Reset, address misaligned interrupt, debug, NMI)
Programmable interrupt External interrupt: 1 system (8 levels)
Internal interrupt: 22 systems (8 levels)
Power supply voltage
VDD operating voltage 1.2 to 3.6 V
VDD operating voltage for Flash programming 2.4 to 3.6 V (VPP = 7.5 V external power supply is required.)
2.4 to 3.6 V (When VPP is generated internally)
VDD operating voltage for super economy mode 2.5 to 3.6 V (128-pin package or chip)
Operating temperature
Operating temperature range -40 to 85 °C
Current consumption (Typ. value)
SLEEP mode 0.15 µA
IOSC = OFF, OSC1 = OFF, OSC3 = OFF
HALT mode 0.5 µA
OSC1 = 32 kHz, RTC = ON
0.3 µA (128-pin package or chip)
OSC1 = 32 kHz, RTC = ON, super economy mode

1 OVERVIEW
S1C17W18 TECHNICAL MANUAL Seiko Epson Corporation 1-3
(Rev. 1.2)
Model S1C17W18
Current consumption (Typ. value)
RUN mode 4 µA
OSC1 = 32 kHz, RTC = ON, CPU = OSC1
2 µA (128-pin package or chip)
OSC1 = 32 kHz, RTC = ON, CPU = OSC1, super economy mode
140 µA
OSC3 = 1 MHz (ceramic oscillator), OSC1 = 32 kHz, RTC = ON, CPU = OSC3
Shipping form
1 *1SQFN9-64PIN (P-VQFN064-0909-0.50, 9 ×9 mm, t = 1 mm, 0.5 mm pitch)
2 *1TQFP14-80PIN (P-TQFP080-1212-0.50, 12 ×12 mm, t = 1.2 mm, 0.5 mm pitch)
3 *1TQFP15-128PIN (P-TQFP128-1414-0.40, 14 ×14 mm, t = 1.2 mm, 0.4 mm pitch)
4 Die form (Pad pitch: 80 µm (min.))
*1 Shown in parentheses are JEITA package names.
1.2 Block Diagram
CPU core & debugger
(S1C17)
Internal RAM
8K bytes
System clock Interrupt request
Interrupt signal
DCLK
DSIO
DST2
32-bit RAM bus
Multiplier/divider
(COPRO2)
Coprocessor bus
Instruction bus
16-bit internal bus
IOSC
oscillator
OSC1
oscillator
EXOSC
input circuit
Clock generator
(CLG)
Power-on reset
(POR)
Power generator
(PWG2)
System reset controller
(SRC)
VDD
VSS
VD1
(
∗1, ∗2) VD2
(
∗1, ∗2) CV1
(
∗1, ∗2) CV2
RTC1S
SDA0
SCL0
EXSVD
P00–07
P10–17
P20–27
P30–32 (∗1)
P33–34 (∗1, ∗2)
P35 (∗1)
P36 (∗1, ∗2)
P37 (∗1)
P40–42 (∗1)
P43–47 (∗1, ∗2)
P50–52 (∗1, ∗2)
P60–67
P70–73
P80–87
PD0–D1
PD3–D4
PD2
FOUT
OSC1
OSC2
OSC3
OSC4
EXOSC
BZOUT
#BZOUT
#RESET
OSC3
oscillator
Interrupt
controller
(ITC)
I/O port
(PPORT)
Watchdog timer
(WDT)
Real-time clock
(RTCA)
I2C
(I2C)
1 Ch.
Supply voltage
detector
(SVD)
16-bit timer
(T16)
4 Ch.
TOUT00–01
TOUT10–11
TOUT20–21
CAP00–01
CAP10–11
CAP20–21
EXCL00–01
EXCL10–11
EXCL20–21
16-bit PWM timer
(T16B)
3 Ch.
SDI0–1
SDO0–1
SPICLK0–1
#SPISS0–1
Sound generator
(SNDA)
Synchronous
serial interface
(SPIA)
2 Ch.
USIN0–1
USOUT0–1
UART
(UART)
2 Ch.
Flash memory
128K bytes VPP
Flash
programming
voltage booster
REMO
CLPLS
IR remote
controller
(REMC2)
1 Ch.
#ADTRG0
ADIN00–06
(ADIN07)
VREFA0
12-bit A/D
converter
(ADC12A)
1 Ch.
Temperature
sensor
&
Reference voltage
generator
(TSRVR)
R/F converter
(RFC)
2 Ch.
RFIN0–1
REF0–1
SENA0–1
SENB0–1
VC1–4
CP1–4
COM0–3
COM4–7/SEG0–3
SEG4–23
SEG24–27 (∗1)
SEG28–34 (∗1, ∗2)
SEG35–38 (∗1)
SEG39–47 (∗1, ∗2)
LFRO
LCD driver
(LCD8B)
Display RAM
96 bytes
*1 These pins do not exist in the 64-pin package. *2 These pins do not exist in the 80-pin package.
Figure 1.2.1 S1C17W18 Block Diagram

1 OVERVIEW
1-4 Seiko Epson Corporation S1C17W18 TECHNICAL MANUAL
(Rev. 1.2)
1.3 Pins
1.3.1 Pin Configuration Diagram (Package)
SQFN9-64PIN
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P70 P71 P72 P73 P80 P81 P82 P83 P84 P85 P86 P87
CP1
CP2 CP3 CP4
P70/SEG7 P71/SEG6 P72/SEG5 P73/SEG4
P80/COM7/SEG3 P81/COM6/SEG2 P82/COM5/SEG1 P83/COM4/SEG0
P84/COM3 P85/COM2 P86/COM1 P87/COM0
CP1
CP2 CP3 CP4
VPP PD2 PD1 PD0 P17 P16 P15 P14 P13 P12 P11 P10 P06 P05 P04 VD1
VPP DCLK/PD2 DSIO/PD1 DST2/PD0 P17/EXCL11/UPMUX/ADIN06 P16/FOUT/UPMUX/ADIN05 P15/BZOUT/UPMUX/ADIN04
P14/#BZOUT/UPMUX/ADIN03
P13/UPMUX/ADIN02 P12/UPMUX/ADIN01 P11/UPMUX/ADIN00 P10/UPMUX/VREFA0 P06/EXCL10/UPMUX P05/EXCL01/UPMUX P04/RTC1S/UPMUX VD1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
(Top View)
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
VDD
VSS
#RESET
OSC1
OSC2
P07
P03
P02
P01
P00
PD4
PD3
VC4
VC3
VC2
VC1
VDD
VSS
#RESET
OSC1
OSC2
P07/EXOSC/UPMUX/EXSVD
P03/RFIN0/UPMUX
P02/REF0/UPMUX
P01/SENA0/UPMUX
P00/SENB0/UPMUX
PD4/OSC4
PD3/OSC3
VC4
VC3
VC2
VC1
Pin
name
P20
P21
P22
P23
P24
P25
P26
P27
P60
P61
P62
P63
P64
P65
P66
P67
Port function
or signal
assignment
P20/SENB1/UPMUX/SEG23
P21/SENA1/UPMUX/SEG22
P22/REF1/UPMUX/SEG21
P23/RFIN1/UPMUX/SEG20
P24/EXCL20/UPMUX/SEG19
P25/EXCL21/UPMUX/SEG18
P26/CLPLS/UPMUX/SEG17
P27/EXCL00/UPMUX/SEG16
P60/RFCLKO0/SEG15
P61/RFCLKO1/SEG14
P62/REMO/SEG13
P63/LFRO/SEG12
P64/#ADTRG/SEG11
P65/SEG10
P66/SEG9
P67/SEG8
Figure 1.3.1.1 S1C17W18 Pin Configuration Diagram (SQFN9-64PIN)
Note: The model in this package cannot be placed into super economy mode, as it does not have the
VD2, CV1, and CV2 pins.

1 OVERVIEW
S1C17W18 TECHNICAL MANUAL Seiko Epson Corporation 1-5
(Rev. 1.2)
TQFP14-80PIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P70 P71 P72 P73 P80 P81 P82 P83 P84 P85 P86 P87
SEG27 SEG26 SEG25 SEG24
CP1
CP2 CP3 CP4
P70/SEG7 P71/SEG6 P72/SEG5 P73/SEG4
P80/COM7/SEG3 P81/COM6/SEG2 P82/COM5/SEG1 P83/COM4/SEG0
P84/COM3 P85/COM2 P86/COM1 P87/COM0
SEG27 SEG26 SEG25 SEG24
CP1
CP2 CP3 CP4
VPP PD2 PD1 PD0 P42 P41 P40 P37 P17 P16 P15 P14 P13 P12 P11 P10 P06 P05 P04 VD1
VDD
VSS
#RESET
OSC1
OSC2
P07
P35
P32
P31
P30
P03
P02
P01
P00
PD4
PD3
VC4
VC3
VC2
VC1
Pin name
P20
P21
P22
P23
P24
P25
P26
P27
SEG38
SEG37
SEG36
SEG35
P60
P61
P62
P63
P64
P65
P66
P67
VPP DCLK/PD2 DSIO/PD1 DST2/PD0 P42 P41 P40 P37/UPMUX P17/EXCL11/UPMUX/ADIN06 P16/FOUT/UPMUX/ADIN05 P15/BZOUT/UPMUX/ADIN04
P14/#BZOUT/UPMUX/ADIN03
P13/UPMUX/ADIN02 P12/UPMUX/ADIN01 P11/UPMUX/ADIN00 P10/UPMUX/VREFA0 P06/EXCL10/UPMUX P05/EXCL01/UPMUX P04/RTC1S/UPMUX VD1
VDD
VSS
#RESET
OSC1
OSC2
P07/EXOSC/UPMUX/EXSVD
P35/UPMUX
P32/UPMUX
P31/UPMUX
P30/UPMUX
P03/RFIN0/UPMUX
P02/REF0/UPMUX
P01/SENA0/UPMUX
P00/SENB0/UPMUX
PD4/OSC4
PD3/OSC3
VC4
VC3
VC2
VC1
Port function
or signal
assignment
P20/SENB1/UPMUX/SEG23
P21/SENA1/UPMUX/SEG22
P22/REF1/UPMUX/SEG21
P23/RFIN1/UPMUX/SEG20
P24/EXCL20/UPMUX/SEG19
P25/EXCL21/UPMUX/SEG18
P26/CLPLS/UPMUX/SEG17
P27/EXCL00/UPMUX/SEG16
SEG38
SEG37
SEG36
SEG35
P60/RFCLKO0/SEG15
P61/RFCLKO1/SEG14
P62/REMO/SEG13
P63/LFRO/SEG12
P64/#ADTRG/SEG11
P65/SEG10
P66/SEG9
P67/SEG8
Figure 1.3.1.2 S1C17W18 Pin Configuration Diagram (TQFP14-80PIN)
Note: The model in this package cannot be placed into super economy mode, as it does not have the
VD2, CV1, and CV2 pins.

1 OVERVIEW
1-6 Seiko Epson Corporation S1C17W18 TECHNICAL MANUAL
(Rev. 1.2)
TQFP15-128PIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
P70 P71 P72 P73
N.C.
P80 P81 P82 P83 P84 P85 P86 P87
N.C.
SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24
N.C.
VDD
CP1 CP2 CP3 CP4
N.C.
P70/SEG7 P71/SEG6 P72/SEG5 P73/SEG4
N.C.
P80/COM7/SEG3 P81/COM6/SEG2 P82/COM5/SEG1 P83/COM4/SEG0
P84/COM3 P85/COM2 P86/COM1 P87/COM0
N.C.
SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24
N.C.
VDD
CP1 CP2 CP3 CP4
N.C.
SEG47 N.C. VPP
PD2 PD1 PD0 P47 P46 P45 P44 P43 P42 P41 P40 P37 N.C. P17 P16 P15 P14 P13 P12 P11 P10 P06 P05 P04 N.C. VD1 CV2 CV1 N.C.
SEG47 N.C. VPP
DCLK/PD2 DSIO/PD1 DST2/PD0 P47 P46 P45 P44 P43 P42 P41 P40 P37/UPMUX N.C. P17/EXCL11/UPMUX/ADIN06 P16/FOUT/UPMUX/ADIN05 P15/BZOUT/UPMUX/ADIN04
P14/#BZOUT/UPMUX/ADIN03
P13/UPMUX/ADIN02 P12/UPMUX/ADIN01 P11/UPMUX/ADIN00 P10/UPMUX/VREFA0 P06/EXCL10/UPMUX P05/EXCL01/UPMUX P04/RTC1S/UPMUX N.C. VD1 CV2 CV1 N.C.
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
VD2
VDD
VSS
#RESET
OSC1
OSC2
N.C.
P52
P51
P50
P07
P36
P35
P34
P33
P32
P31
P30
N.C.
P03
P02
P01
P00
PD4
PD3
N.C.
VSS
VC4
VC3
VC2
VC1
N.C.
VD2
VDD
VSS
#RESET
OSC1
OSC2
N.C.
P52
P51
P50
P07/EXOSC/UPMUX/EXSVD
P36/UPMUX
P35/UPMUX
P34/UPMUX
P33/UPMUX
P32/UPMUX
P31/UPMUX
P30/UPMUX
N.C.
P03/RFIN0/UPMUX
P02/REF0/UPMUX
P01/SENA0/UPMUX
P00/SENB0/UPMUX
PD4/OSC4
PD3/OSC3
N.C.
VSS
VC4
VC3
VC2
VC1
N.C.
Pin name
N.C.
P20
P21
P22
P23
P24
P25
P26
P27
N.C.
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
N.C.
P60
P61
P62
P63
P64
P65
P66
P67
N.C
Port function
or signal
assignment
N.C.
P20/SENB1/UPMUX/SEG23
P21/SENA1/UPMUX/SEG22
P22/REF1/UPMUX/SEG21
P23/RFIN1/UPMUX/SEG20
P24/EXCL20/UPMUX/SEG19
P25/EXCL21/UPMUX/SEG18
P26/CLPLS/UPMUX/SEG17
P27/EXCL00/UPMUX/SEG16
N.C.
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
N.C.
P60/RFCLKO0/SEG15
P61/RFCLKO1/SEG14
P62/REMO/SEG13
P63/LFRO/SEG12
P64/#ADTRG/SEG11
P65/SEG10
P66/SEG9
P67/SEG8
N.C.
Figure 1.3.1.3 S1C17W18 Pin Configuration Diagram (TQFP15-128PIN)