Infineon PSoC 6 User manual

PSoC™6 MCU low-power modes and power
reduction techniques
About this document
Scope and purpose
AN219528 describes how to use PSoC™6 MCU power modes to optimize power consumption. Major topics
include low-power modes in PSoC™6 MCU devices, and power management techniques using PSoC™6 MCU
features. Associated code examples demonstrate dierent low-power techniques. See AN230938 – PSoC™6 MCU
low- power analog for additional information on the low-power analog peripherals of CY8C62x4 family devices.
More code examples? We heard you.
To access an ever-growing list of hundreds of PSoC™MCU code examples, please visit our code examples web
page. You can also explore the video training library here.
AN219528
Application note Please read the sections "Important notice" and "Warnings" at the end of this document 002-19528 Rev. *E
www.infineon.com 2022-07-21

Table of contents
About this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Power mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 CPU sleep and wakeup instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Low-power assistant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3.1 Low-power assistant features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.3.2 PSoC™6 MCU device LPA settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.3 Connectivity device LPA soware settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.4 Subsystem availability and power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.4.1 Subsystem availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4.2 Approximating power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4.3 Power estimator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5 Example case scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.6 System power management (SysPm) library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.6.2 Mode transition functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 PSoC™6 MCU power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.1 Core voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.1 Linear regulator and buck regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 ULP mode clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 Backup power domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.3.1 VBackup supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.3.2 Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3.3 External PMIC control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.3.4 Wakeup sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.3.5 Backup data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4 Other power saving techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1 Use PSoC™6 MCU to gate current paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.2 Disable unused blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.3 Use DMA to move data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.4 Periodic wakeup timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.5 Disabling CPUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.6 Splitting tasks between the CPUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.7 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.8 GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.9 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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4.10 TCPWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.11 SCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
4.12 Audio subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
4.13 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
4.14 Low-power comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
4.15 SAR ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.16 Voltage DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.17 Opamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
5 Power measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
5.1 Measuring the current with a DMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.2 Approximating the power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6 Power supply protection system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1 Hardware control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1.1 Brownout detect (BOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1.2 Low-voltage detect (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1.3 Overvoltage detect (OVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
A Power modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
A.1 Power modes and wakeup source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
B Subsystem availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
B.1 Resources available in dierent power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
C Callback function examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
C.1 Register callback functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
C.2 Implement custom callback functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
D Code examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
D.1 CE219881 - PSoC™6 MCU switching between power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
D.2 CE218129 - PSoC™6 MCU wakeup from hibernate using a low-power comparator . . . . . . . . . . . . . 46
D.3 CE218542 - PSoC™6 MCU custom tick timer using RTC alarm interrupt . . . . . . . . . . . . . . . . . . . . . . . 47
D.4 CE226306 - PSoC™6 MCU power measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
PSoC™6 MCU low-power modes and power reduction techniques
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Application note 3 002-19528 Rev. *E
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1 Introduction
PSoC™6 MCU gives the best power-saving benefit when low-power modes are implemented with other
power-saving features and techniques, without significantly sacrificing the performance. This application note
describes not only general power-saving methods but also the unique low-power modes in PSoC™6 MCU. It also
discusses other low-power considerations.
This application note requires a basic knowledge of the PSoC™MCU architecture, and the ability to develop
a PSoC™6 MCU application using PSoC™Creator IDE or ModusToolbox™soware. If you are new to PSoC™6
MCU, see AN221774 - Getting started with PSoC™6 MCU or AN210781 – Getting started with PSoC™6 MCU with
Bluetooth®Low Energy connectivity on PSoC™Creator IDE. If you are new to PSoC™Creator IDE, see PSoC™
Creator IDE.
If you are designing an Internet of Things (IoT) system, there are additional connectivity-related power
considerations that impact total system power. While these considerations are outside the scope of this
application note (AN), there are specific application notes focused on low-power IoT systems. AN227910 –
Low- power system design with AIROC™CYW43012 Wi-Fi & Bluetooth®combo chip and PSoC™6 MCU discusses
optimizations for low power in Wi-Fi, Bluetooth®, and PSoC™6 MCU systems.
PSoC™6 MCU low-power modes and power reduction techniques
1 Introduction
Application note 4 002-19528 Rev. *E
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2 Power modes
2.1 Power mode transitions
PSoC™6 MCU features seven power modes that are divided into system modes that aect the whole device,
and standard ARM®CPU modes that aect only one CPU. The system power modes are Low-Power (LP),
Ultra-Low-Power (ULP), deep sleep, and hibernate. The ARM®CPU power modes are active, sleep, and deep
sleep; these are available in system LP and ULP power modes. Table 1 lists the power modes in which the
devices operate.
Table 1 PSoC™6 MCU power modes
Power mode Description
System LP • All resources are available with maximum power and speed
• All CPU power modes supported
System ULP • All blocks are available, but the core voltage is lowered resulting in reduced high-
frequency clock frequencies
• All CPU power modes supported
CPU active • Normal CPU code execution
• Available in system LP and ULP power modes
CPU sleep • CPU halts code execution
• Available in system LP and ULP power modes
CPU deep sleep • CPU halts code execution
• Requests system deep sleep entry
• Available in system LP and ULP power modes
System deep sleep • Occurs when all CPUs are in CPU deep sleep
• CPUs, most peripherals, and high-frequency clocks are OFF
• Low-frequency clock is ON
• Low-power analog and some digital peripherals are available for operation and as
wakeup sources
• SRAM is retained
System hibernate • CPUs and clocks are OFF
• GPIO output states are frozen
• Low-power comparator, RTC alarm, and dedicated WAKEUP pins are available to
wake up the system
• Backup domain is available
• SRAM is not retained
Figure 1 shows how power mode transitions are based on dierent events and actions, including interrupts,
firmware actions, and reset events. In some cases, mode transitions are done through multiple modes.
For more detailed information, see PSoC™6 MCU architecture technical reference manual and Appendix A.
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System ULP
(0.9 V Core)
System LP
(1.1 V Core)
CPU active CPU active
CPU sleep/
deep sleep
CPU sleep/
deep sleep
System
hibernate
XRES
External reset event
Firmware action
Hibernate wakeup events
Power Mode Action
LEGEND:
XRES/
POR/BOD
Assert
Firmware
Action
Peripheral
Interrupt
Firmware
Action
Wakeup
Assert
XRES/POR/BOD
Deassert
Peripheral interrupts/
Hardware events
System
deep sleep
Off
Both
CPUs in
deep sleep Deep sleep
Interrupt for
this CPU
Firmware
Action
Peripheral
Interrupt
Deep sleep
Interrupt for
other CPU
Deep sleep
Interrupt for
other CPU
Deep sleep
Interrupt for
this CPU
Firmware
Action
Figure 1 PSoC™6 MCU device power mode transition
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2.2 CPU sleep and wakeup instructions
ARM®Cortex®CPUs transition between sleep and wakeup independently. Figure 2 shows several scenarios of
wakeup from sleep.
Wait-for-Interrupt (__WFI) is the core sleep instruction. Aer a CPU executes __WFI, the CPU goes to sleep and
stays in sleep until any interrupt is asserted. Wait-for-Event (__WFE) is similar to __WFI, but it wakes up when the
wakeup event is received instead of an interrupt. Set Event (__SEV) is used for waking up other CPUs in sleep
mode because of a __WFE. CPU deep sleep uses the same instructions for sleep and wakeup, but the SLEEPDEEP
bit[2] of the Arm®System Control Register (SCR) is set before a sleep instruction. For more information on SCR,
see ARM®system control register user guide. This process is implemented in SysPm PDL library APIs.
Figure 2 Multi-CPU sleep and wakeup cases
CPU power modes are dierent from system power modes. Figure 2 shows that each CPU supports its own
sleep modes, independent of the state of the other CPU. The device is in system deep sleep mode when both
CPUs are in deep sleep. For more detailed information, see AN215656 – PSoC™6 MCU dual-CPU system design.
2.3 Low-power assistant
2.3.1 Low-power assistant features
The low-power assistant (LPA) provides an easy-to-use GUI for setup of both device and system power options.
The LPA’s goal is to aid in quickly attaining datasheet power numbers in real-world user applications. For each
power option supported in the device, the ModusToolbox™device configurator has corresponding sections to
configure power resources in the same method as configuring any other peripheral.
To launch the assistant, for PSoC™6 MCU devices, from under the PSoC™6 MCU part number tab and System
sub-tab, select Power resource, as shown in Figure 3. For connectivity devices, from under the Wi-Fi or
Bluetooth®device part number tab, select the BT or Wi-Fi Resource in the Power section, as shown in Figure 4.
See the LPA documentation in the Documentation section located at the top of the Power Configurator.
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2 Power modes
Application note 7 002-19528 Rev. *E
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Figure 3 LPA soware selection for PSoC™MCU
Figure 4 Connectivity device LPA selection
2.3.2 PSoC™6 MCU device LPA settings
Use the PSoC™6 MCU device section of the LPA to configure the initial power configuration of the device as
shown in Figure 5. Use the General section of the LPA to configure the highest power settings required in the
design for system power mode, core regulators, and Vbackup domain features. Aer the highest power mode
is configured, use the RTOS section to configure the lowest power mode the system automatically transitions
into. In many designs, this is all the power mode configuration required, because the RTOS typically handles
all the dynamic mode transitions. For more advanced use cases, the HAL or SysPm PDL library power functions
can be called at any time to dynamically modify any of the power settings or initiate a power mode transition.
CPU and system wakeup from sleep and deep sleep power modes occur when any configured peripheral
interrupt is triggered. You can configure the sleep and deep sleep wakeup interrupts by enabling the desired
wakeup peripheral’s interrupt in that peripheral’s configurator within ModusToolbox™device configurator.
If your system enters hibernate mode at runtime using HAL or SysPm calls, the LPA Wakeup pins section
simplifies the selection of hibernate wakeup sources.
Figure 5 Power parameters: LPA soware for PSoC™MCU
2.3.3 Connectivity device LPA soware settings
Use the “Connectivity device” section of the LPA soware to configure Wi-Fi and Bluetooth®power options.
AIROC™Bluetooth®connectivity devices are designed to automatically operate in their lowest power modes.
The primary power option is to enable the Bluetooth®device host wakeup trigger as shown in Figure 6.
PSoC™6 MCU low-power modes and power reduction techniques
2 Power modes
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Bluetooth®host wakeup allows the PSoC™6 MCU host device to enter a system deep sleep or hibernate mode
and wait for the Bluetooth®connectivity device to wake up the MCU by generating a GPIO pin interrupt when it
is required to process Bluetooth®operations.
Figure 6 LPA soware: Bluetooth®power parameters
Infineon AIROC™Wi-Fi & Bluetooth®connectivity devices support a wide range of power optimization techniques
that you can configure based on the needs of the application and network features supported, as shown in
Figure 7. The three primary low-power features for Wi-Fi are host wakeup, oloads, and filters.
•Host wakeup allows the PSoC™6 MCU host to enter system deep sleep or hibernate mode until the Wi-Fi
device requires MCU processing. When the host MCU must wake up, the Wi-Fi device triggers a GPIO pin
interrupt. A host wakeup is required to use most of the other low-power Wi-Fi features
•Oloads allow the MCU’s device stack processing to be moved (oloaded) to the Wi-Fi device internal
processor. This increases the time the MCU host can devote to other tasks or spend in a low-power mode
•Filters run on the Wi-Fi device and avoid waking the host MCU until the filter conditions are met. An
example is an IoT device that needs to respond only to MQTT packets. The device can enable MQTT filters
to ignore all other network traic allowing the host MCU device to stay longer in a low-power mode
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Figure 7 LPA soware: Wi-Fi power parameters
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2.4 Subsystem availability and power consumption
2.4.1 Subsystem availability
Each subsystem resource works dierently in various system power modes. For example, the CPU can be in ON,
OFF, and Retention modes. It is important to select proper peripherals for the power mode to work correctly.
Table 2 lists the resources available in dierent power modes.
2.4.2 Approximating power consumption
See the device datasheet for power consumption data for given conditions. Because there are dierent
combinations to achieve the best power consumption, the actual power consumption of the application can be
dierent from the datasheet.
2.4.3 Power estimator
Eclipse IDE for ModusToolbox™soware version 2.1 provides the Power Estimator (CyPE) tool, which estimates
the power consumed by a target device or platform dynamically at runtime. This tool helps you determine the
power in dierent operating modes and how power changes under actual system conditions.
Figure 8 CyPE tool
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2.5 Example case scenarios
Proper power mode selection reduces power consumption without performance degradation. Table 2 lists
sample scenarios of power modes. In some examples, only a few power modes are used eectively.
Table 2 Sample case scenarios of power modes
Power modes Wearable device Air conditioner Remote
controller
Thermometer
System LP
CPU active
GUI interaction by user Motor run – Communicates over
BLE
System ULP
CPU active
Processes heartbeat – Sends command Reads temperature
Updates result on
LCD
System LP
CPU sleep
– – – –
System ULP
CPU sleep
Analog block detects
heartbeat
– – –
System deep
sleep
Goes to deep sleep when
the device does not detect
heartbeat for 30 seconds
(device is not in use)
Waits for command
No motor run
Wakeup by infra-
red (IR) triggering
– Wakes up every
1 second using
watchdog timer
(WDT)
System hibernate Low battery – Does nothing
Resets device when
charger is plugged in
– Waits for button
press
–
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2.6 System power management (SysPm) library
2.6.1 Overview
The peripheral driver library (PDL) is a complete soware tool that includes APIs for configuring peripherals and
system registers to implement the desired functionality. PDL provides direct access to almost all hardware
resources of the target device. It reduces the need to understand and directly access registers and bit
structures.
Within the PDL, the system power management (SysPm) API provides functions to change power modes as
shown in Figure 1. The API can also register callback functions to execute a peripheral function before or aer
power mode transitions as shown in Figure 9. PDL is available from two sources depending on the development
platform you are using. The two versions of PDL share the same APIs but are not compatible with the other
versions tool base.
•ModusToolbox™peripheral driver library (psoc6pdl) from github.com. The ModusToolbox™soware
installation automatically installs PDL but requires a download during install directly from GitHub
•PSoC™Creator IDE peripheral driver library from the website. The PSoC™Creator IDE download and
installation includes PDL so no additional user actions are required
2.6.2 Mode transition functions
Figure 1 shows firmware transitions for power modes. SysPm provides the default five transition functions for
CPU sleep, CPU deep sleep, system hibernate, system LP, and system ULP.
The power mode changing functions provide four dierent callback operations to execute a necessary action
for each peripheral:
Callback function Description
CY_SYS_PM_CHECK_READY Checks the ready state to transition to other mode. Exits without
transition if it returns CY_SYSPM_FAIL.
CY_SYSPM_BEFORE_TRANSITION Callbacks execute and configure required actions before mode
transition.
CY_SYSPM_AFTER_TRANSITION Callbacks execute aer mode transition or configuration.
CY_SYS_CHECK_FAIL Callbacks execute only when CY_SYSPM_CHECK_READY fails. It executes
the rollback action.
The SysPm driver provides three functions for callback: registration, de-registration, and execution. These
functions not only help in power optimization, but also in preventing an abnormal peripheral state aer mode
transition. The PDL expects the user to register callbacks for each power mode, as shown in Figure 9. Most
peripheral drivers have predefined callbacks associated with each power mode. You can choose to register
the defined peripheral callback or can make a custom callback. The SysPm transition function executes the
registered callbacks sequentially. The first registered function is executed first.
For more information on callback registration and implementation, see Appendix C, and Appendix D.1 of the
code example CE219881 - PSoC™6 MCU switching between power modes, which is the mode transition example
for CPU active, CPU sleep, system LP, system ULP, and system deep sleep.
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Figure 9 Power mode callback registration and deregistration
By calling the mode transition function, the device starts to transition with four callback operations. The CPU
sleep and CPU deep sleep modes use Arm®sleep instructions. Code execution stops and waits for an interrupt
during the CPU sleep power mode. Figure 9 shows the CPU waiting for a wakeup source aer calling the sleep
instruction: __WFI() or __WFE(). Aer wakeup, the device automatically transitions to CPU active.
Figure 10 Sleep/deep sleep/hibernate mode transition
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In the system LP and system ULP modes, all system resources keep running. Entering system LP and ULP
modes is done by configuring the power mode control register; the transition occurs without delay. SysPm PDL
provides the associated driver functions, as shown in Figure 11. For the best power eiciency, it is necessary
to configure the core voltage regulator and the system clock. For more detailed information, see Core voltage
selection, ULP mode clock and peripheral driver library documentation (PSoC™Creator > Help > Documentation
> Peripheral Driver Library).
Figure 11 Low-power mode transition
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3 PSoC™6 MCU power management
3.1 Core voltage selection
3.1.1 Linear regulator and buck regulator
PSoC™6 MCU supports multiple on-chip regulators including low drop out (LDO) and single input multiple
output (SIMO), or single input single output (SISO) buck to generate VCC for core power, as listed in Table 3.
The LDO can provide up to 300 mA in high-current mode (normal) and 25 mA in low-current mode. The buck
regulator can provide up to 20 mA for one output and 30 mA combined for both outputs of the SIMO buck. The
SIMO buck regulator provides better eiciency under normal load conditions. Once switched to the SIMO buck
regulator, it is not possible to switch back to the LDO without resetting the device.
Table 3 Options of core voltage regulators for low-power profile
Output Max load Max clock frequency
LDO 0.9 V 25/300 mA (low-current mode/normal mode) 50 MHz for Arm®Cortex®-M4 (CM4)
25 MHz for Arm®Cortex®-M0+ (CM0+)
1.1 V 25/300 mA (low-current mode/normal mode) Allow maximum supportable clock frequency
Buck 0.9 V 20 mA 50 MHz for CM4
25 MHz for CM0+
1.1 V 20 mA Allow maximum supportable clock frequency
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3.2 ULP mode clock
Transition to ULP mode can be done by configuring the power mode control register. There is a maximum clock
speed limitation in ULP mode as described earlier, so the clock configuration should be adjusted based on
the regulator output when entering or exiting ULP mode. PDL provides associated functions to configure the
PWR_CTL register. For more information, see PSoC™6 MCU registers technical reference manual.
Figure 12 shows how to transition between LP and ULP modes using PDL functions with the registered callback
function. Because of the ULP mode clock limitation, either the frequency-locked loop (FLL) clock speed or
HFClk should be adjusted to a valid frequency before the mode transition. Changing the FLL frequency impacts
the blocks that use FLL-derived clocks; therefore, all active peripherals should register their own callbacks
to handle the changing frequency. CE219881 – PSoC™6 MCU switching between power modes provides an
example of clock adjustment using callbacks.
Figure 12 LP mode enter/exit transition
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3.3 Backup power domain
The backup domain is not a power mode but rather an always on group of resources that can be active during
any of the device power modes.
A separate power supply provides power to a limited number of functions shown in Figure 13 while the
main device power is removed. This results in the lowest power state possible while retaining a base level
of functionality. The backup domain contains the pmic_wakeup_in pin allowing system-generated signals to
trigger the repowering of the device and return to the CPU active power state.
A real time clock (RTC) allows periodic and accurate time-based wakeup triggers. By continuously powering the
RTC using the VBACKUP supply accurate time can be maintained independently of the full device power state.
Wakeup is accomplished by outputting a HIGH logic level on the pmic_wakeup_out pin most commonly used
to enable an external power management integrated circuit (PMIC) supplying power to the full PSoC™6 MCU
device.
64 bytes of SRAM storage are also maintained allowing key system state information to be retained when the
device is repowered. The backup domain is powered by the VBACKUP supply that can be powered by a separate
system supply, battery, or supercapacitor. In designs that do not require the backup domain to be powered
separately from the rest of the PSoC™6 MCU device, VBACKUP should be connected directly to the VDDD supply.
Figure 13 Backup domain block diagram
3.3.1 VBackup supply
By providing a separate VBACKUP supply to the backup domain, the majority of the device may be completely
powered down eliminating the leakage that would otherwise still occur in system hibernate power mode. If the
backup domain is not powered separately from the rest of the device, VBACKUP and VDDD must be tied together.
The internal backup power supply named VDDBAK is automatically switched between VDDD and VBACKUP using an
internal circuit. When VDDD is present and greater than 1.6 V, the VBACKUP supply is disabled in order to conserve
battery or supercapacitor capacity. As VDDD drops below 1.6 V, the greater of VBACKUP or VDDD supplies is selected
and the lower voltage supply connection is disabled. There are no sequencing restrictions between VBACKUP and
VDDD. There is no need for external power supply isolation and switching circuits in most designs.
There are four common VBACKUP supply connection options.
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1. VBACKUP directly connected to VDDD – When the backup domain is only used with the full PSoC™6 MCU
device, there is no reason for a separate supply. VBACKUP and VDDD supply pins must be directly connected
together as shown in Figure 14
Figure 14 Backup domain combined connection
2. VBACKUP powered by supercapacitor – When a supercapacitor is used as the VBACKUP supply as shown
in Figure 15, there are two options for recharging it. By calling the Cy_SysPm_BackupSuperCapCharge() PDL
function, the internal charge circuit is enabled any time the VDDD supply is selected as the active VDDBAK
supply
The key value of 0x3C must be passed in the function to avoid accidentally enabling the charge circuit.
This charge circuit is not precise; the current varies in the range of 20 µA based on the dierence
between VDDD and VBACKUP. Recharge time is on the order of hours
The second option is to use an external charge circuit which can be optimized for any unique design
challenges including a faster charge time. Both charge methods can be used in parallel. Any external
charge components should be chosen to limit leakage current. The supercapacitor will be charged up to
VDDD; therefore, ensure that it has an appropriate voltage rating
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Figure 15 Backup domain supercapacitor connection Backup domain battery
connection
3. VBACKUP powered by battery – Figure 16 demonstrates a battery-powered VBACKUP . When a battery
supplies VBACKUP, it is important to NOT use the supercapacitor charge circuit because it provides no
battery safety mechanisms. If the battery is rechargeable, an external board-level recharge circuit can be
provided for the battery-specific charge requirements
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