Intel 82496 CACHE CONTROLLER User manual

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intel®
Pentium™ Processor
User's Manual
Volume 2:
82496 Cache Controller and
82491 Cache SRAM Data Book
NOTE: The Pentium™ Processor User's Manual consists of three
books: Pentium™ Processor Data Book, Order Number 241428; the
82496 Cache Controller and 82491 Cache SRAM Data Book, Order
Number 241429; and the Architecture andProgramming Manual,
Order Number 241430.
Please refer to all three volumes when evaluating your design needs.
1993
I

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© INTEL CORPORATION 1993
CG·010493

82496 CACHE CONTROLLER AND
82491 CACHE SRAM
FOR USE WITH THE PENTIUMTM PROCESSOR
• High Performance Second Level Cache •
Zero Wait States at 66 MHz
Two-way Set Associative
Write-Back with MESI Protocol
Concurrent CPU bus and memory
bus operation
Boundary Scan
• Pentium Processor •
Chip Set Version of Pentium
Processor
Superscalar Architecture
Enhanced Floating Point
On-chip 8K Code and 8K Data
Caches
See Pentium™Processor Data Book
for more information
Highly Flexible
256K to 512K with parity
32, 64,
or 128 Bit Wide Memory Bus
Synchronous, Asynchronous, and
Strobed Memory Bus Operation
Selectable Bus Widths, Line Sizes,
Transfers, and Burst Orders
Full Multiprocessing Support
Concurrent CPU, Memory Bus, and
Snoop Operations
Complete MESI Protocol
Internal/External Parity
Generation/Checking
Supports Read-for Ownership,
Write-Allocation, and Cache-to-
Cache Transfers
The 82496 Cache Controller and multiple 82491 Cache SRAMs combine with the Pentium processor to
form a CPU Cache chip set designed for high performance servers and function-rich desktops. The high-
speed interconnect between the CPU and cache components has been optimized to provide zero-wait state
operation. This CPU Cache chip set is fully compatible with existing software, and has new data integrity
features for mission critical applications.
The 82496 cache controller
implements the MESI write-back
protocol for full multiprocessing
support. Dual ported buffers and
registers allow the 82496 to
concurrently handle CPU bus,
memory bus, and internal cache
operation for maximum
performance.
The 82491 is a customized high-
performance SRAM that
supports 32, 64, and 128-bit
wide memory bus widths, 16,
32, and 64 byte line sizes, and
optional sectoring. The data
path between the CPU bus and
memory bus is separated by the
82491, allowing the CPU bus to
handshake synchronously,
asynchronously, or with a
strobed protocol, and allowing
concurrent CPU bus and
memory bus operations.
I iii

TABLE OF CONTENTS
CHAPTER 1
PINOUTS Page
1.1. PINOUT DIAGRAMS .................................................................................................... 1-1
1.1.1. Pentium™ Processor Pinouts................................................................................... 1-1
1.1.2. 82496 Cache Controller Pinouts ...............................................................................1-3
1.1.3.
82491 Cache SRAM Memory Pinouts ......................................................................1-5
1.2.
PIN CROSS REFERENCE TABLES.............................................................................1-7
1.2.1. Pentium Processor....................................................................................................1-7
1.2.2. 82496 Cache Controller............................................................................................1-9
1.2.3.
82491 Cache SRAM ...............................................................................................1-12
1.3. BRIEF
PIN DESCRiPTIONS.......................................................................................1-12
CHAPTER 2
CACHE ARCHITECTURE OVERVIEW
2.1. MAIN FEATURES.........................................................................................................2-2
2.2. CPU/CACHE
CORE DESCRIPTION ............................................................................2-2
2.2.1. 82496 Cache Controller............................................................................................2-2
2.2.2.
82491 Cache SRAMs ...............................................................................................2-3
2.2.3. Memory Bus Controller .............................................................................................2-4
2.3. CONFIGURATION ........................................:...............................................................2-5
2.3.1. Physical Cache .........................................................................................................2-5
2.3.2. Snoop Modes............................................................................................................2-6
2.3.2.1. SYNCHRONOUS SNOOP
MODE ........................................................................2-6
2.3.2.2. CLOCKED (ASYNCHRONOUS) SNOOP
MODE .................................................2-6
2.3.2.3. STROBED SNOOP
MODE ...................................................................................2-6
2.3.3. Memory
Bus Modes ..................................................................................................2-6
2.3.3.1. CLOCKED MEMORY
BUS MODE ........................................................................2-7
2.3.3.2. STROBED MEMORY
BUS MODE ........................................................................2-7
2.4.
PENTIUM PROCESSOR BUS INTERFACE ................................................................2-7
2.5. 82496 CACHE CONTROLLER/82491 CACHE
SRAM OPTIMIZED INTERFACE........ 2-8
2.6. MEMORY
BUS INTERFACE ........................................................................................2-8
2.6.1. Snooping Logic .........................................................................................................2-8
2.6.2. Cycle Control Logic...................................................................................................2-9
2.7. TEST.............................................................................................................................2-9
CHAPTER 3
COMPONENT OPERATION
3.1. WRITE-THROUGH CACHE DESiGNS......................................................................... 3-1
3.2. WRITE-BACK CACHE DESIGNS................................................................................. 3-1
3.3. 82496 CACHE CONTROLLER CACHE CONSISTENCY PROTOCOL........................ 3-1
3.4. MESI CACHE CONSISTENCY PROTOCOL MODEL ..................................................3-2
3.5. BASIC
MESI STATE TRANSiTIONS............................................................................3-3
3.5.1.
MESI State Changes Resulting From CPU Bus Operations.....................................3-5
3.5.1.1.
READ HIT .............................................................................................................3-5
3.5.1.2.
READ MISS ..........................................................................................................3-5
3.5.1.3. WRITE HIT............................................................................................................3-6
3.5.1 .4. WRITE MiSS.........................................................................................................3-6
I v

CONTENTS
Page
3.5.1.5. WRITE MISS WITH ALLOCATION .............:......................................................... 3-6
3.5.2. MESI State Changes Resulting From Memory Bus Masters ....................................3-7
3.5.2.1. SNOOPING...........................................................................................................3-7
3.5.2.2. CACHE SyNCHRONiZATION ..............................................................................3-8
3.6. MESI STATE CHANGES FOLLOWING CYCLES WITH SPECIAL ATTRIBUTES.......3-8
3.6.1. Cacheability Attributes:
PCD, MKEN# ...................................................................... 3-8
3.6.2. Write Through Protocol: PWT, MWB/WT#................................................................3-8
3.6.3.
Read Only Accesses: MRO# ....................................................................................3-9
3.6.4. Locked Accesses: LOCK# ........................................................................................3-9
3.6.5. Direct-To-Modified Attribute: DRCTM# ...................................................................3-10
3.7. STATE TRANSITIONS ...............................................................................................3-10
3.7.1. CPU Bus Signals ....................................................................................................3-10
3.7.2. Memory Bus Signals ............................................................................................... 3-11
3.7.3. Tag State and Cycles.Resulting from State Transitions .........................................3-12
3.7.3.1.
TAG STATE ........................................................................................................3-12
3.7.3.2. CYCLES RESULTING
FROM STATE TRANSITIONS .......................................3-12
3.7.4.
MESI State Tables (82496 Cache Controller State Changes) ................................3-14
3.8. PRIMARY TO SECONDARY CACHE COHERENCy.................................................3-17
3.8.1. Inclusion..................................................................................................................3-17
3.8.2. Inquire
and Back-Invalidation Cycles......................................................................3-18
3.8.3. Write Once Policy ...................................................................................................3-19
3.8.4.
MESI State Tables (Pentium Processor CPU-Cache Chip Set State Changes)..... 3-19
CHAPTER 4
CACHE INITIALIZATION AND CONFIGURATION
4.1. CONFIGURATION SIGNAL SAMPLING DURING RESET ..........................................4-2
4.1.1. Initialization Required for Chip Set
Mode ..................................................................4-3
4.2. PHYSICAL CACHE.......................................................................................................4-4
4.2.1. Memory
Bus Width....................................................................................................4-4
4.2.2. Line Ratio..................................................................................................................4-5
4.2.3.
Tag RAM Size............................................................................................................4-5
4.2.4.
Tag RAM Structure ....................................................................................................4-5
4.2.5. Lines per Sector (LIS) ...............................................................................................4-6
4.2.6. Cache Size................................................................................................................4-7
4.2.7. Configurable Address Connections ...........................................................................4-7
4.2.8.
82491 Cache SRAM Bus Configuration....................................................................4-8
4.2.9.
82491 Cache SRAM Parity Configuration.................................................................4-9
4.2.10.
CPU to 82491 Cache SRAM Address Configurations ..............................................4-9
4.2.11.
Bus Driver Buffer Selection..................................................................................... 4-1 0
4.3. CACHE MODES .........................................................................................................4-10
4.3.1. Memory Bus Modes ................................................................................................ 4-1 0
4.3.1.1. CLOCKED MODE ............................................................................................... 4-11
4.3.1.2. STROBED MODE ............................................................................................... 4-11
4.3.1.3. CONFIGURATION OF MEMORY BUS MODE ................................................... 4-11
4.3.2. Snoop Modes.......................................................................................................... 4-11
4.3.2.1. CONFIGURATION OF SNOOP MODE ...............................................................4-12
4.3.3. Strong/Weak Write Ordering...................................................................................4-12
4.3.3.1. DESCRiPTION....................................................................................................4-12
4.3.3.2. CONFIGURATION ..............................................................................................4-13
vi
I

CONTENTS
CHAPTERS
HARDWARE INTERFACE Page
5.1. MEMORY BUS CONTROLLER CONSiDERATIONS ................................................... 5-1
5.1 .1. Cycle Control ............................................................................................................5-2
5.1.1.1. IDENTIFYING
AND EXECUTING CyCLES..........................................................5-4
5.1.1.1.1.
Read Hit............................................................................................................5-6
5.1.1.1.2. Cacheable
Read Miss.......................................................................................5-6
5.1.1.1.3. Non-Cacheable
Read Miss ...............................................................................5-7
5.1.1 .1 .4. Write Hit [EJ, [M] ................................................................................................5-7
5.1 .1 .1 .5. Write Hit lSI.......................................................................................................5-7
5.1.1.1.6. Write Miss:
No Allocation, Allocation ................................................................5-7
5.1.1.1.7. Replacement.....................................................................................................5-8
5.1.1 .1.8. Snoop Write Back .............................................................................................5-8
5.1.1.1.9. Locked ..............................................................................................................5-8
5.1.1.1.10. Cache-To-Cache Transfer ................................................................................5-9
5.1.1.1.11.
Read For Ownership.........................................................................................5-9
5.1 .1 .1.12. 1/0 Cycles .......................................................................................................5-10
5.1 .1 .1.13. Special Cycles ................................................................................................ 5-1 0
5.1.1.1.14. FLUSH and SYNC Cycles ..............................................................................5-10
5.1.2. Snooping................................................................................................................. 5-11
5.1.2.1. CHOOSING A SNOOPING MODE ..................................................................... 5-11
5.1.2.1.1. Synchronous Snooping Mode ......................................................................... 5-11
5.1.2.1.2. Asynchronous Snooping Mode .......................................................................5-12
5.1.2.1.3. Strobed Snooping
Mode .................................................................................5-13
5.1.2.2. SNOOP OPERATION .........................................................................................5-14
5.1.2.3. SNOOP BLOCKING............................................................................................5-17
5.1.2.4.
WHEN SNOOPING IS NOT ALLOWED .............................................................5-19
5.1.2.5. SNOOPING DURING
LOCKED CyCLES...........................................................5-20
5.1.2.5.1. Snooping During Split Locked Cycles............................................................. 5-21
5.1.2.6. SNOOP WRITE BACK CyCLES......................................................................... 5-21
5.1.3. Address Integrity.....................................................................................................5-22
5.1.3.1.
CPU BUS ADDRESS PARITY............................................................................5-22
5.1.3.2. MEMORY
BUS ADDRESS PARITY ...................................................................5-22
5.1.4. Data Control............................................................................................................5-23
5.1.4.1.
CPU DATA BUS TRANSFER CONTROL...........................................................5-24
5.1.5. Memory
Bus Mode Selection ..................................................................................5-24
5.1.6.
82491 Cache SRAM Intelligent Dual-Ported Cache Memory .................................5-25
5.1.6.1.
82491 CACHESRAMDATAPATH ....................................................................5-25
5.1.6.2. . MEMORY CYCLE BUFFERS .............................................................................5-26
5.1.6.3. WRITE-BACK
AND SNOOP BUFFERS .............................................................5-26
5.1.6.4. MEMORY
BUS CONTROL SiGNALS.................................................................5-27
5.1.6.5.
82491 CACHE SRAM PARITY DEViCES...........................................................5-28
5.1.7. Signal Synchronization ...........................................................................................5-29
5.1.8.
Warm Reset ............................................................................................................5-30
5.1.9. Handling of Large Caches I Larger Line Sizes .......................................................5-30
5.1.10. 82496 Cache Controller Guaranteed Signal Relationships ....................................
5-31
5.1.11. 82496 Cache Controller Cycle Progress Requirements .........................................5-32
5.1.12. 82496 Cache Controller Input Signal Recognition Requirements...........................5-32
5.1.13. 82496 Cache Controller
and 82491 Cache SRAM CRDY# Requirements.............5-32
5.1.14. 82496 Cache Controller Cycle Attribute Sampling Requirements ..........................5-33
5.1.15. Pentium Processor, 82496 Cache Controller,
and 82491 Cache
5.1.16.
5.1.17.
5.1.18.
I
SRAM BRDY# Requirements .................................................................................5-33
82496 Cache Controller Cycle Progress Signal Sampling Requirements ..............5-34
82491 Cache SRAM Data Control Signal Requirements........................................5-35
Semaphore (Strong Write Ordering) Consistency ..................................................5-35
vii

CONTENTS
Page
5.2. DETAILED PENTIUM PROCESSOR CPU-CACHE CHIP SET
PIN DESCRIPTIONS..................................................................................................5-36
5.2.1.
5.2.1.1.
5.2.1.2.
5.2.1.3.
5.2.1.4.
5.2.1.5.
5.2.1.6.
5.2.1.7.
5.2.1.8.
5.2.1.9.
5.2.1.10.
5.2.1.11.
5.2.2.
5.2.2.1.
5.2.2.2.
5.2.2.3.
5.2.2.4.
5.2.2.5.
5.2.2.6.
5.2.2.7.
5.2.2.8.
5.2.2.9.
5.2.2.10.
5.2.2.11.
5.2.2.12.
5.2.2.13.
5.2.2.14.
5.2.2.15.
5.2.2.16.
5.2.2.17.
5.2.2.18.
5.2.2.19.
5.2.2.20.
5.2.2.21.
5.2.2.22.
5.2.2.23.
5.2.2.24.
5.2.2.25.
5.2.2.26.
5.2.2.27.
5.2.2.28.
5.2.2.29.
5.2.2.30.
5.2.2.31.
5.2.2.32.
5.2.2.33.
5.2.2.34.
5.2.2.35.
5.2.2.36.
5.2.2.37.
viii
Signal/Category Cross-Reference ..........................................................................5-36
CONFIGURATION SiGNALS..............................................................................5-36
SNOOPING SiGNALS ........................................................................................5-36
CYCLE ATTRIBUTE / PROGRESS SiGNALS....................................................5-36
CYCLE CONTROL SIGNALS .............................................................................5-36
MEMORY ADDRESS BUS AND ADDRESS CONTROL SIGNALS....................5-37
MEMORY DATA BUS AND DATA CONTROL SIGNALS ...................................5-37
CACHE SYNCHRONIZATION SIGNALS............................................................5-37
CPU SiGNALS....................................................................................................5-37
TEST SIGNALS ..................................................................................................5-37
PENTIUM PROCESSOR BUS OPTIMIZED INTERFACE SiGNALS..................5-37
82496 CACHE CONTROLLER/82491 CACHE SRAM OPTIMIZED
INTERFACE SIGNALS .......................................................................................5-37
Pentium Processor CPU-Cache Chip Set Detailed Pin Descriptions......................5-38
A[31 :3]/A[15:0] ....................................................................................................5-38
A20M#.................................................................................................................5-39
ADS#...................................................................................................................5-40
ADSC#................................................................................................................5-41
AHOLD................................................................................................................5-42
AP .......................................................................................................................5-43
APCHK#..............................................................................................................5-44
APERR#..............................................................................................................5-45
APIC#..................................................................................................................5-46
BE#,BE[7:0]# ......................................................................................................5-47
BGT#...................................................................................................................5-48
BLAST#...............................................................................................................
5-50
BLE#................................................................................................................... 5-51
BLEC#.................................................................................................................5-52
BOFF# ................................................................................................................5-54
BP[3:2], PM/BP[1 :0] ............................................................................................5-55
BRDY#................................................................................................................5-56
BRDYC# .............................................................................................................5-58
BRDYC1# ...........................................................................................................5-59
BRDYC2# ...........................................................................................................
5-60
BREQ.................................................................................................................. 5-61
BT[3:0] ................................................................................................................5-62
BUS#...................................................................................................................5-63
BUSCHK#...........................................................................................................5-64
CACHE# .............................................................................................................5-65
CADS#.................................................................................................................5-66
CAHOLD .............................................................................................................5-68
CCACHE#...........................................................................................................5-69
CD/C# .................................................................................................................5-70
CDATA[7:0].........................................................................................................
5-71
CDTS# ................................................................................................................5-72
CFA[6:0],SET[10:0],TAG[11 :0]............................................................................5-74
CFG[2:0] .............................................................................................................5-75
CLDRV................................................................................................................5-76
CLK.....................................................................................................................5-77
CM/IO#................................................................................................................5-78
CNA# ..................................................................................................................5-79
I

5.2.2.38.
5.2.2.39.
5.2.2.40.
5.2.2.41.
5.2.2.42.
5.2.2.43.
5.2.2.44.
5.2.2.45.
5.2.2.46.
5.2.2.47.
5.2.2.48.
5.2.2.49.
5.2.2.50.
5.2.2.51.
5.2.2.52.
5.2.2.53.
5.2.2.54.
5.2.2.55.
5.2.2.56.
5.2.2.57.
5.2.2.58.
5.2.2.59.
5.2.2.60.
5.2.2.61.
5.2.2.62.
5.2.2.63.
5.2.2.64.
5.2.2.65.
5.2.2.66.
5.2.2.67.
5.2.2.68.
5.2.2.69.
5.2.2.70.
5.2.2.71.
5.2.2.72.
5.2.2.73.
5.2.2.74.
5.2.2.75.
5.2.2.76.
5.2.2.77.
5.2.2.78.
5.2.2.79.
5.2.2.80.
5.2.2.81.
5.2.2.82.
5.2.2.83.
5.2.2.84.
5.2.2.85.
5.2.2.86.
5.2.2.87.
5.2.2.88.
5.2.2.89.
5.2.2.90.
I
CONTENTS
Page
CPCD..................................................................................................................5-80
CPWT .................................................................................................................
5-81
CRDY#................................................................................................................5-82
CSCYC ...............................................................................................................5-84
CW/R# ................................................................................................................5-85
CWAY .................................................................................................................5-86
D/C#....................................................................................................................5-87
D[63:0] ................................................................................................................5-88
DP[7:0]................................................................................................................5-89
DRCTM#.............................................................................................................5-90
EADS#................................................................................................................5-92
EWBE# ...............................................................................................................5-93
FERR# ................................................................................................................5-94
FLUSH# ..............................................................................................................5-95
FRCMC#..................................... '" .....................................................................5-97
FSIOUT#.............................................................................................................5-98
HIGHZ#.............................................................................................................5-100
HIT#..................................................................................................................5-101
HITM#...............................................................................................................5-102
HLDA ................................................................................................................5-103
HOLD................................................................................................................5-104
IBT ...................................................................................................:................5-105
IERR# ...............................................................................................................5-106
IGNNE#.............................................................................................................5-107
INIT...................................................................................................................5-108
INTR..................................................................................................................5-109
INV....................................................................................................................5-110
IPERR#.............................................................................................................5-111
IU ......................................................................................................................5-112
IV.......................................................................................................................5-113
KEN#.................................................................................................................5-114
KLOCK#............................................................................................................5-116
KWEND#...........................................................................................................5-118
LOCK# ..............................................................................................................5-120
LR[1 :0] ..............................................................................................................5-121
M/IO#................................................................................................................5-122
MALDRV...........................................................................................................5-123
MALE ................................................................................................................5-124
MAOE# .............................................................................................................5-125
MAP ..................................................................................................................5-127
MAPERR#.........................................................................................................5-128
MAWEA# ..........................................................................................................5-129
MBALE..............................................................................................................5-130
MBAOE#...........................................................................................................5-131
MBE#................................................................................................................5-133
MBRDY#...........................................................................................................5-135
MBT[3:0] ...........................................................................................................5-137
MCACHE#.........................................................................................................5-139
MCFA[6:0]. MSET[10:0]. MTAG[11 :0]...............................................................5-141
MCLK................................................................................................................5-143
MCYC# .............................................................................................................5-144
MDATA[7:0] ......................................................................................................5-145
MDLDRV...........................................................................................................5-147
ix

CONTENTS
5.2.2.91.
5.2.2.92.
5.2.2.93.
5.2.2.94.
5.2.2.95.
5.2.2.96.
5.2.2.97.
5.2.2.98.
5.2.2.99.
5.2.2.100.
5.2.2.101.
5.2.2.102.
5.2.2.103.
5.2.2.104.
5.2.2.105.
5.2.2.106.
5.2.2.107.
5.2.2.108.
5.2.2.109.
5.2.2.110.
5.2.2.111.
5.2.2.112.
5.2.2.113.
5.2.2.114.
5.2.2.115.
5.2.2.116.
5.2.2.117.
5.2.2.118.
5.2.2.119.
5.2.2.120.
5.2.2.121.
5.2.2.122.
5.2.2.123.
5.2.2.124.
5.2.2.125.
5.2.2.126.
5.2.2.127.
5.2.2.128.
5.2.2.129.
5.2.2.130.
5.2.2.131.
5.2.2.132.
5.2.2.133.
5.2.2.134.
5.2.2.135.
5.2.2.136.
5.2.2.137.
5.2.2.138.
5.2.2.139.
5.2.2.140.
5.2.2.141.
5.2.2.142.
5.2.2.143.
x
Page
MOOE# .............................................................................................................5-148
MEOC# .............................................................................................................5-149
MFRZ#..............................................................................................................5-151
MHITM# .............;..............................................................................................5-153
MISTB ...............................................................................................................5-154
MKEN#..............................................................................................................5-155
MOCLK .............................................................................................................5-156
MOSTB .............................................................................................................5-158
MRO#................................................................................................................5-159
MSEL#..............................................................................................................5-161
MSTBM .............................................................................................................5-163
MTHIT#.............................................................................................................5-164
MTR4/8#...........................................................................................................5-165
MWB/WT#....................................................................:....................................5-166
MX4/8#..............................................................................................................5-167
MZBT#..............................................................................................................5-168
NA#...................................................................................................................5-170
NENE#..............................................................................................................5-172
NMI ...................................................................................................................5-173
PALLC#.............................................................................................................5-174
PAR#.................................................................................................................5-175
PCO ..................................................................................................................5-176
PCHK#..............................................................................................................5-177
PEN#.................................................................................................................5-178
PROY ................................................................................................................5-179
PWT..................................................................................................................5-180
RIS#..................................................................................................................5-181
ROYSRC...........................................................................................................5-182
RESET..............................................................................................................5-183
SCYC ................................................................................................................5-185
SEC2#...............................................................................................................5-186
SLFTST#...........................................................................................................5-187
SMI#..................................................................................................................5-188
SMIACT# ..........................................................................................................5-189
SMLN#..............................................................................................................5-190
SNPAOS# .........................................................................................................5-191
SNPBSY# .........................................................................................................5-193
SNPCLK............................................................................................................5-194
SNPCYC#.........................................................................................................5-195
SNPINV.............................................................................................................5-196
SNPMO .............................................................................................................5-197
SNPNCA ...........................................................................................................5-198
SNPSTB#..........................................................................................................5-200
SWENO#
...........................................................................................................5-202
SYNC#..............................................................................................................5-204
TCK...................................................................................................................5-206
TOI ....................................................................................................................5-207
TOO ..................................................................................................................5-208
TMS ..................................................................................................................5-209
TRST#
...............................................................................................................5-210
W/R# .................................................................................................................5-211
WAy ..................................................................................................................5-212
WB/WT#............................................................................................................5-213
I

CONTENTS
Page
5.2.2.144. WBA ..................................................................................................................5-214
5.2.2.145.
WBTYP .............................................................................................................5-215
5.2.2.146. WBWE# ............................................................................................................5-216
5.2.2.147. WRARR# ..........................................................................................................5-217
5.2.2.148. WWOR#............................................................................................................5-218
CHAPTER 6
MEMORY BUS FUNCTIONAL DESCRIPTION
6.1. READ CyCLES............................................................................................................. 6-1
6.1 .1. Read Hit Cycles ........................................................................................................ 6-1
6.1.2. Read Miss Cycles .....................................................................................................6-4
6.1.2.1.
WITH CLEAN REPLACEMENT............................................................................6-4
6.1.2.2.
WITH REPLACEMENT OF MODIFIED LINE ........................................................6-7
6.1 .3. Non Cacheable Read Miss Cycles ...........................................................................6-9
6.2. WRITE CyCLES.........................................................................................................6-10
6.2.1. Write Hit to
IE] or 1M] State Cycles .........................................................................6-10
6.2.2. Write Miss
with No Allocation or Write Hit to IS] State Cycles ................................6-12
6.2.3. Write
Miss with Allocation Cycles ...........................................................................6-14
6.3. LOCKED READ-MODIFY-WRITE CYCLES ...............................................................6-16
6.4.
SNOOP HIT TO 1M] STATE -SYNCHRONOUS SNOOP MODE ...............................6-18
6.5.
I/O CyCLES................................................................................................................ 6-21
CHAPTER 7
ELECTRICAL SPECIFICATIONS
7.1. POWER AND GROUND ............................................................................................... 7-1
7.2. DECOUPLING RECOMMENDATIONS ........................................................................ 7-1
7.3. CONNECTION SPECIFICATIONS ............................................................................... 7-1
7.4. MAXIMUM RATINGS .................................................................................................... 7-1
7.5. D.C. SPECiFiCATIONS................................................................................................ 7-2
7.6. A.C. SPECIFICATIONS ................................................................................................7-4
7.6.1. Optimized Interface...................................................................................................7-4
7.6.1.1. FLIGHT TIME SPECIFICATION ...........................................................................
7-5
7.6.1.1.1. 66-MHz 256-Kbyte Flight Times ....................................................................... 7-9
7.6.1.1.2. 60-MHz 256-Kbyte Flight Times .....................................................................7-12
7.6.1.1.3. 60-MHz 512-Kbyte Flight Times .....................................................................7-15
7.6.1.2. SIGNAL QUALITY...............................................................................................7-18
7.6.2. External Interface....................................................................................................7-20
7.6.2.1.
66 MHz A.C. SPECiFiCATIONS......................................................................... 7-21
7.6.2.2. 60 MHz A.C. SPECiFiCATIONS.........................................................................7-32
7.7. OVERSHOOT/UNDERSHOOT GUIDELINES ............................................................7-49
CHAPTER 8
1/0 BUFFER MODELS
8.1. OPTIMIZED INTERFACE BUFFERS ............................................................................8-2
8.2. EXTERNAL INTERFACE
BUFFERS ............................................................................8-5
8.3.
INPUT DIODE MODELS...............................................................................................8-6
CHAPTER 9
MECHANICAL SPECIFICATIONS
I
xi

CONTENTS
CHAPTER 10
THERMAL SPECIFICATIONS
CHAPTER 11
TESTABILITY Page
11.1. BUILT-IN SELT TEST (BIST)...................................................................................... 11-1
11.2. BOUNDARY SCAN.....................................................................................................11-2
11.2.1. Boundary Scan Architecture ...................................................................................11-3
11.2.2. Test Data Registers ................................................................................................11-3
11.2.2.1. BYPASS REGISTER ..........................................................................................11-4
11.2.2.2. BOUNDARY SCAN REGiSTER..........................................................................11-4
11.2.2.3. DEVICE IDENTIFICATION REGISTER ..............................................................11-5
11.2.2.4. RUNBIST REGISTER .........................................................................................11-6
11.2.3. Instruction Register.................................................................................................11-6
11.2.3.1. PENTIUM PROCESSOR CPU-CACHE CHIP SET BOUNDARY
SCAN INSTRUCTION SET.................................................................................11-6
11.2.4. Test Access Port (TAP) Controller..........................................................................11-8
11.2.4.1. TEST-LOGIC-RESET STATE.............................................................................11-9
11.2.4.2. CAPTURE-IR STATE........................................................................................11-10
11.2.5. Boundary Scan Register Cell................................................................................11-10
11.2.5.1. PENTIUM PROCESSOR BOUNDARY SCAN REGISTER CELL..................... 11-10
11.2.5.2. 82496 CACHE CONTROLLER BOUNDARY SCAN REGISTER CELL............ 11-11
11.2.5.3. 82491 CACHE SRAM BOUNDARY SCAN REGISTER CELL.......................... 11-13
11.2.6. ! Boundary Scan Description Language (BSDL).....................................................11-13
11.2.7. Boundary Scan Signal Descriptions......................................................................11-13
11.3.
82491 CACHE SRAM TESTING...............................................................................11-13
APPENDIX A
SUPPLEMENTAL INFORMATION
Figure
1-1.
1-2.
1-3.
1-4.
1-5.
1-6.
1-7.
2-1.
2-2.
2-3.
3-1.
3-2.
4-1.
4-2.
4-3.
4-4.
xii
Figures
Title Page
Pentium™ Processor Pinout (Top View) ................................................................... 1-1
Pentium™ Processor Pinout (Bottom View) ..............................................................1-2
82496 Cache Controller Pinout (Top View) ..............................................................1-3
82496 Cache Controller Pinout (Bottom View) .........................................................1-4
82491 Cache SRAM Memory Pinout (Top View)......................................................1-5
82491 Cache SRAM Pinout (Bottom View)...............................................................1-6
Brief
Pin Description Table Cross Reference .........................................................1-14
82496 Cache Controller Block Diagram....................................................................2-3
82491 Cache SRAM Block Diagram.........................................................................2-4
MBC Block Diagram..................................................................................................2-5
State Changes ..........................................................................................................3-5
Pentium™ Processor CPU-Cache Chip Set Cache Inclusion .................................3-17
82491 Cache Controller/82491 Cache SRAM Configurations with the
Pentium™ Processor................................................................................................
4-1
Configuration Input Sampling....................................................................................4-2
CPU-Cache Chip Set Configuration Inputs...............................................................4-3
Two-Way Set Associative Tag
RAM Structure ..........................................................4-6
I

Figure
4-5.
5-1.
5-2.
5-3.
5-4.
5-5.
5-6.
5-7.
5-8.
5-9.
5-10.
5-11.
5-12.
5-13.
5-14.
5-15.
5-16.
5-17.
5-18.
5-19.
5-20.
5-21.
5-22.
5-23.
5-24.
5-25.
5-26.
5-27.
5-28.
5-29.
5-30.
6-1.
6-2.
6-3.
6-4.
6-5.
6-6.
6-7.
6-8.
6-9.
6-10.
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
7-7.
7-8.
7-9.
7-10.
7-11.
7-12.
I
CONTENTS
Title Page
Address Latching ......................................................................................................4-8
MBC Block Diagram..............:...................................................................................5-2
Memory Bus Cycle Progress and Attribute Signals ..................................................5-3
Cycle Progress Signals and Responses...................................................................5-3
Synchronous Snoop Mode......................................................................................5-12
Clocked Snoop Mode..............................................................................................5-13
Strobed Snoop Mode ..............................................................................................5-14
82496 Cache Controller Snooping Operations .......................................................5-15
Fastest Synchronous Snooping..............................................................................5-16
Fastest Asynchronous Snooping ............................................................................5-16
Snoops without Invalidation ....................................................................................5-16
Snoops with Invalidation .........................................................................................5-17
Snoop Response During Cycles.............................................................................5-17
Snoop Response Blocking Using BGT# .................................................................5-18
Snoop Executing before BGT# Is Asserted ............................................................5-19
New SNPSTB# Not Allowed ...................................................................................5-20
Cycle Progress for Snoop Write Back Cycles.........................................................5-22
MAPERR# Timing for Synchronous Snoop Mode ..................................................5-23
MAPERR# Timing for Asynchronous Snoop Modes...............................................5-23·
BRDY# I BRDYC# I BRDYC1# I BRDYC2# Interconnection..................................5-24
82491 Cache SRAM Read Data Path.....................................................................5-28
Pentium™ Processor/82491 Cache SRAM Data Parity Connections .....................5-29
512K Cache, 64-Bit Bus..........................................................................................
5-31
BLEC# Deassertion Due to ADS# Assertion ..........................................................5-52
BLEC# Assertion Due to CNA# or CRDY# Assertion .............................................5-53
BLEC# Assertion Due to Hit
in 82496 Cache Controller TagRAM..........................5-53
KLOCK# to LOCK# Relationship ..........................................................................5-116
MBE# [PAR#] Timing After RESET.......................................................................5-133
MFRZ# Sampling ..................................................................................................5-151
Increasing Hold Time of Output Burst Data ..........................................................5-156
MZBT# Sampling ..................................................................................................5-169
Pipelined Read Hits ..................................................................................................6-2
Read Miss With Clean Replacement ........................................................................6-4
Read Miss with Replacement of Modified Line .........................................................6-7
Non Cacheable Read Miss .......................................................................................6-9
Write Hits
to [E] or [M] State Cycles........................................................................6-10
Write Miss with No Allocation or Write Hit
to [S] State Cycles ................................6-12
Write Miss with Allocation
to Modified Line.............................................................6-14
Locked Read Modify Write Cycles..........................................................................6-16
Snoop Hit to [M] State -Synchronous Snoop Mode ...............................................6-18
1/0 Cycles ............................................................................................................... 6-21
Determination of Flight Time.....................................................................................7-6
Derating the Flight Time................................:...........................................................7-7
In-System Measurement of Flight Time ....................................................................7-8
Driver and Receiver Signal Waveforms Showing Signal Quality Parameters......... 7-19
Clock Waveform......................................................................................................7-42
Valid Delay Timings ................................................................................................7-43
Setup and Hold Timings..........................................................................................7-43
Setup and Hold Timings in Strobed Snooping Mode..............................................7-43
Reset and Configuration Timings............................................................................7-44
Memory Interface Timings ......................................................................................7-44
Setup and Hold Timings to Strobes ........................................................................7-45
Setup and Hold Timings MxST................................................................................7-45
xiii

CONTENTS
Figure
7-13.
7-14.
7-15.
7-16.
7-17.
8-1.
8-2.
8-3.
8-4.
9-1.
9-2.
9-3.
10-1.
11-1.
11-2.
11-3.
Table
1-1.
1-2.
1-3.
1-4.
1-5.
1-6.
1-7.
1-8.
1-9.
1-10.
1-11.
1-12.
1-13.
1-14.
1-15.
1-16.
1-17.
1-18.
2-1.
2-2.
3-1.
3-2.
3-3.
3-4.
3-5.
3-6.
3-7.
3-8.
3-9.
xiv
m~ P~~
Valid Delay Timings from Strobes...................................:.......................................7-45
Test Timings ...........................................................................................................7-46
Test Reset Timings.................................................................................................7-46
Active/Inactive Timings...........................................................................................7-47
Overshoot/Undershoot and Ringback Guidelines...................................................7-49
First Order Input Buffer .............................................................................................
8-1
First Order Output Buffer .......................................................................................... 8-1
Input Diode Model.....................................................................................................8-7
Complete Input Model Including Diode.....................................................................8-7
Pentium™ Processor Mechanical Specifications ......................................................9-3
82496 Cache Controller Mechanical Specifications..................................................9-5
82491 Cache SRAM Mechanical Specifications.......................................................9-6
Technique For Measuring Tcase ............................................................................
10-1
Boundary Scan Register Structure of a Component............................................... 11-5
Device
10 Register..................................................................................................11-5
TAP Controller State Diagram ................................................................................11-9
Tables
Title Page
Pentium™ Processor Pin Cross Reference by Pin Name........................................ 1-7
82496 Cache Controller
Pin Cross Reference by Pin Name ....................................1-9
82491 Cache SRAM Pin Cross Reference by Pin Name........................................ 1-12
Pentium™ Processor/MBC Interface Signals..........................................................1-14
82496 Cache Controller/MBC Interface Signals .....................................................1-15
82491 Cache SRAM/MBC Interface Signals...........................................................1-15
Pentium™ Processor/82496 Cache Controller Interface Signals............................ 1-15
Pentium™ Processor/82491 Cache SRAM Interface Signals .................................1-15
82496 Cache Controller/82491 Cache SRAM Interface Signals ............................ 1-16
Pentium™ Processor CPU-Cache Chip Set Brief Pin Descriptions......................... 1-16
Pentium™ Processor CPU-Cache Chip Set Internal Pull-Up Resistors .................. 1-36
Pentium™ Processor CPU-Cache Chip Set Internal Pull-Down Resistors............. 1-36
Pentium™ Processor CPU-Cache Chip Set Glitch Free Pins ................................1-36
Signal Interconnects on Optimized Interface ..........................................................1-37
Pin States During RESET.......................................................................................1-39
Pentium™ Processor CPU-Cache Chip Set Output Pins ........................................ 1-40
Pentium™ Processor CPU-Cache Chip Set Input Pins...........................................1-43
Pentium™ Processor CPU-Cache Chip Set Input/Output Pins ............................... 1-47
Pentium™ Processor Signals Accessible by the MBC..............................................2-7
Pentium™ Processor Signals Latched in the 82496 Cache Controller and
82491 Cache SRAM .................................................................................................2-8
Basic MESI State Transitions ...................................................................................3-4
Master 82496 Cache Controller Read Cycle ..........................................................3-14
Master 82496 Cache Controller Write Cycle...........................................................3-15
Snooping 82496 Cache Controller without Invalidation Request............................3-16
Snooping 82496 Cache Controller with Invalidation Request.................................3-16
SYNC Cycles ..........................................................................................................3-16
FLUSH Cycles ........................................................................................................3-17
MESI State Changes for READ Cycles: CPU to 82496 Cache Controller/
82491 Cache SRAM Caches..................................................................................3-20
MESI State Changes for WRITE Cycles: CPU to 82496 Cache Controller/
82491 Cache SRAM Caches.................................................................................. 3-21
I

Table
3-10.
4-1.
4-2.
4-3.
4-4.
4-5.
4-6.
4-7.
5-1.
5-2.
5-3.
5-4.
5-5.
5-6.
5-7.
5-8.
5-9.
5-10.
5-11.
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
7-7.
7-8.
7-9.
7-10.
7-11.
7-12.
7-13.
7-14.
7-15.
7-16.
7-17.
7-18.
7-19.
7-20.
7-21.
7-22.
7-23.
7-24.
I
CONTENTS
Title Page
MESI State Changes for SNOOP Cycles: 82496'Cache Controller/82491
Cache SRAM to CPU Caches.................................................................................3-22
Pentium™ Processor Chip Set Initialization Recommendations ...............................4-4
82496 Cache Controller/82491 Cache SRAM Configuration Inputs.........................4-4
Pentium™ Processor CFA Address Connections .....................................................4-7
Memory Bus Address Control ...................................................................................4-8
MX!MTR Configurations............................................................................................4-9
Parity Configurations.................................................................................................4-9
82491 Cache SRAM Address Connections............................................................4-10
Cycle Identification and Length.................................................................................5-5
CCACHE# Use in Determining the Number of BRDY#s.........................................5-69
Using CPCD and CPWT to Determine Write Hit to
[SJ versus Write Miss.............. 5-80
FSIOUT# Operation Priorities.................................................................................5-98
Actions Based on 82496 Cache Controller Configuration Test Inputs
(HIGHZ# and SLFTST#) .......................................................................................5-100
KEN# Operation ., ..................................................................................................5-114
82491 Cache SRAM Line Ratio Configuration with LR[1
:OJ ..................................5-121
MCACHE# Status versus Cycle Type...................................................................5-139
Signals Sampled at RESET.......................................,..........................................5-184
SNPNCA Asserted During Snoop Requests (Inactive SNPINV)...........................5-198
Snooping Modes.......................................................................................
'" .........5-200
Absolute Maximum Ratings ......................................................................................7-2
D.C. Specifications....................................................................................................7-3
Three Specification Classes, Their Purpose and the New Parameters....................7-5
Description of Maximum Flight Time and Clock Skew..............................................7-8
Signal Group: CPU to Cache RAM (CPU-CRAM) (66 MHz 256 Kbyte Version) ......7-9
Signal Group: CPU to Cache (CPU-Cache) (66 MHz 256 Kbyte Version) .............7-10
Signal Group: CPU to Cache Controller (CPU-CCTL)
(66 MHz 256 Kbyte Version)...................................................................................7-11
Signal Group: Cache Controller to Cache RAM (CCTL-CRAM)
(66 MHz 256 Kbyte Version)...................................................................................7-12
Signal Group: CPU to Cache RAM (CPU-CRAM)
(60 MHz 256 Kbyte Version)...................................................................................7-12
Signal Group: CPU to Cache (CPU-Cache)
(60 MHz 256 Kbyte Version)...................................................................................7-13
Signal Group: CPU to Cache Controller (CPU-CCTL)
(60 MHz 256 Kbyte Version)...................................................................................7-14
Signal Group: Cache Controller to Cache RAM (CCTL-CRAM)
(60 MHz 256 Kbyte Version)...................................................................................7-15
Signal Group: CPU to Cache RAM (CPU-CRAM) (60 MHz 512 Kbyte Version) .... 7-15
Signal Group: CPU to Cache (CPU-Cache) (60 MHz 512 Kbyte Version) .............7-16
Signal Group: CPU to Cache Controller (CPU-CCTL)
(60 MHz 512 Kbyte Version)...................................................................................7-17
Signal Group: Cache Controller to Cache RAM (CCTL-CRAM)
(60 MHz 512 Kbyte Version)...................................................................................7-18
Specifications for Signal Quality .............................................................................7-20
66 MHz CPU Cache Chip Set Common Timings.................................................... 7-21
66 MHz Pentium™ Processor Memory Bus Interface Timings................................7-23
66 MHz 82496 Cache Controller Memory Bus Interface Timings...........................7-24
66 MHz 82491 Cache SRAM Memory Bus Interface Timings ................................7-27
60 MHz CPU Cache Chip Set Common Timings..........,.........................................7-32
60 MHz Pentium™ Processor Memory Bus Interface Timings................................7-34
60 MHz 82496 Cache Controller Memory Bus Interface Timings...........................7-35
xv

CONTENTS
Table
7-25.
7-26.
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
9-1.
9-2.
9-3.
9-4.
10-1.
10-2.
10-3.
11-1.
11-2.
11-3.
xvi
Title Page
60 MHz 82491 Cache SRAM Memory Bus Interface Timings ................................7-38
External Interface Signal Buffer Assignment ..........................................................7-48
Parameters Used in the Specification
of the First Order Input Buffer Model ............ 8-1
Parameters Used in the Specification of the First Order Output Buffer Model..........8-2
Specification of Input Optimized Interface Buffer Model Parameters .......................8-2
Specification of Output Optimized Interface Buffer Model Parameters.....................8-3
Specifications to be Used for Simulation of Flight Time
or Signal Quality ................8-4
Specification of Input External Interface Buffer Model Parameters ..........................8-5
Specification of Output External Interface Buffer Model Parameters........................8-6
Diode Parameter List ................................................................................................8-8
Data for Diode I-V Curves.........................................................................................8-9
CPU Cache Chip Set Package Information Summary..............................................
9-1
Pentium™ Processor Mechanical Specificatons.......................................................9-2
82496 Cache Controller Mechanical Specificatons ..................................................9-4
82491 Cache SRAM Mechanical Specificatons........................................................9-6
Junction-to-Case and Case-to-Ambient Thermal Resistances for
the Pentium
™ Processor (With and Without a Heat Sink)......................................10-2
Junction-to-Case and Case-to-Ambient Thermal Resistances for
the 82496 Cache Controller (With and Without a Heat Sink).................................. 10-2
Junction-to-Case and Caes-to-Ambient Thermal Resistances for
the 82491 Cache SRAM (With and Without a Heat Sink).......................................10-2
82496 Cache Controller/82491 Cache SRAM Boundary Scan Test
Data Register Length..............................................................................................11-4
Pentium™ Processor CPU-Cache Chip Set Component Device
Identification Code..................................................................................................11-6
82496 Cache Controller/82491 Cache SRAM Boundary Scan
I
nstruction Codes....................................................................................................11-7
I

1
Pinouts
I