Intel l2ICE User manual

inteT
THE l2ICE™
INTEGRATED INSTRUMENTATION
AND IN-CIRCUIT EMULATION
SYSTEM USER’S GUIDE
Copyright 1985, Intel Corporation, All Rights Reserved
Intel Corp., 3065 owers Ave., Santa Clara, CA 95051 Order Number: 166298-001

THENCE™
INTEGRATED INSTRUMENTATION
AND IN-CIRCUIT EMULATION
SYSTEM USER’S GUIDE
Order Number: 166298-001
Copyright 1985, Intel Corporation, All Rights Reserved
Intel Corporation, 3065 owers Avenue, Santa Clara, California 95051

This equipment generates, uses, and can radiate radio t'requency energy and if not installed and used in accordance with
the instruction manual, may cause interference to radio communications. As temporarily permitted by regulation, it has
not been tested for compliance with the limits for Class A Computing evices pursuant to Subpart J of Part 15 of FCC
rules, which arc designed to provide reasonable protection against such interference. Operation of this equipment in a
residential area is likely to cause interference in which case the user, at his own expense, will be required to take whatever
measures may be required to correct the interference.
| CAUrflON ^
Additional copies of this manual or other Intel literature may be obtained from:
Literature epartment
Intel Corporation
3065 Bowers Avenue
Santa Clara, CA 95051
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Above iLBX iPDS ONCE
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COMMputer iMDDX iRMX Plug A Bubble
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GENIUS Intel iSDM QueX
.A into I iSXM QUEST
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ICE indigent Identifier Megaehassis RUPI
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Copyright 1985, Intel Corporation. All Rights Reserved

CONTENTS
age
Preface..................................................................................................................................................... xi
Revision History.................................................................................................................................... xvii
Service Information................................................................................................................................ xix
CHA TER 1 l2ICE™ SYSTEM OVERVIEW
____________________________
The Microcomputer evelopment Process........................................................................................ 1-1
Features of a evelopment System with an Emulator................................................................... 1-1
Generalized Hardware esign Steps................................................................................................ 1-2
Generalized Software esign Steps................................................................................................ 1-2
Hardware/Software Integration......................................................................................................... 1-3
An Introduction to the PICE™ System..................................................................................
.. ............ 1-3
The Base Configuration of the PICE™ System
............................................................................. 1-4
PICE™ System O ptions................................................................................................................... 1-6
PICE™ System Accessories............................................................................................................. 1-7
Hardware Overview................................................................................................................................ 1-8
The Instrumentation Chassis............................................................................................................. 1-8
The Host Interface B oard................................................................................................................. 1-8
The Emulation Base Module............................................................................................................. 1-10
System Interface Cables................................................................................................................... 1-11
High-Speed Memory.....................................................................
.. .................................................. 1-11
Optional High-Speed Memory Board.............................................................................................. 1-11
The Intel Logic Timing Analyzer (iLTA)........................................................................................ 1-11
Emulation Personality Modules....................................................................................................... 1-11
Software Overview................................................................................................................................ 1-12
Software Environment....................................................................................................................... 1-12
The PICE™ System Command Language...................................................................................... 1-14
The PICE™ System Software........................................................................................................... 1-15
The PICE™ System Host isk(s)................................................................................................ 1-15
The PICE™ System Error/Help isk.......................................................................................... 1-15
The PICE™ System Probe isks................................................................................................ 1-15
The PICE™ System iagnostic isk.......................................................................................... 1-15
The iLTA isks.............................................................................................................................. 1-16
The PSCOPE-86 isk................................................................................................................... 1-16
The PICE™ System Tutorial isk(s).......................................................................................... 1-16
PICE™ System Specifications............................................................................................................. 1-17
Host Requirements...............................................................................................................
............ 1-17
System Performance......................................................................................................................... 1-18
Emulation Clips.................................................................................................................................. 1-18
The Target System User Interfaces.................................................................................................. 1-19

CHA TER 2 GUIDE TO THE ICE™ SYSTEM TUTORIAL
_______________ age
Tutorial U se..............................................
.. ............ . . . .............. .......................................................... 2-1
Invoking the Tutorial uring Program ebugging
. ...................................................................... 2-2
eactivating the Tutorial................................................................................................................... 2-2
Reactivating the Tutorial................................................................................................................... 2-2
Tutorial Screens and Structure............................................................................................................. 2-2
Copies of Selected Tutorial Screens................................................................................................ 2-4
An Overview of the Tutorial Structure............................................................................................ 2-5
List of All Tutorial Screens
. .............................................................................................................. 2-6
Tutorial Index,
. .. .. .. ............................................................................................................................. 2-13
Tutorial Program Listings..................................................................................................................... 2-16
Overview of the PL/M Tutorial Program........................................................................................ 2-16
PL/M Program Listing for the Two-Bug Version of the Change Maker Program
..................... 2-17
The ASM-86 Listing for the No-Bug Version of the Change Maker Program
........................... 2-21
Sample Programs in C, FORTRAN, and Pascal
............................................................................... 2-30
A Change Maker Program in C
...................................................................................................... 2-31
A Change Maker Program in FORTRAN...................................................................................... 2-32
A Change Maker Program in Pascal................................................................................................ 2-33
CHA TER 3 INTRODUCTION TO USING THE ICE™ SYSTEM
__________
Invoking PICE™ Software..................................................................................................................... 3-1
Entering PICE™ System Commands.................................................................................................... 3-3
Extending a Command to Another Line.......................................................................................... 3-3
Aborting Commands......................................................................................................................... 3-3
Multiple Commands on a Line......................................................................................................... 3-4
Comments.......................................................................................................................................... 3-4
The Command Line Editor
...................................................... .. ...................................................... 3-4
The PICE™ System Syntax M enu.................................................................................................. 3-4
The PICE™ Command History Buffer............................................................................................ 3-5
String Handling................................................................................................................................... 3-6
Block Commands................................................................................................................................. 3-7
Creating ebug Objects................................................................................................... 3-8
Creating a ebug Procedure............................................................................................................... 3-8
Creating a LITERALLY efinition.................................................................................................. 3-9
Creating a ebug Register................................................................................................................. 3-9
Creating a ebug Variable................................................................................................................. 3-9
The PICE™ Screen Editor................................................................................................................... 3-10
Inserting Text...................................................................................................................................... 3-10
eleting and Moving Text................................................................................................................. 3-11
Viewing Text...................................................................................................................................... 3-11
Overwriting Text................................................................................................................................ 3-11
Editing External Files........................................................................................................................ 3-11
Exiting the Screen E ditor................................................................................................................. 3-12
File Handling.......................................................................................................................................... 3-12
LIST F iles............................................................................................... 3-12
INCLU E Files: The INCLU E, PUT, and APPEN Commands
.......................................... 3-13
The LOA and SAVE Commands................................................................................................... 3-14
Memory Types........................................................................................................................................ 3-15
ebug Variables.................................................................................................................................. 3-16
iv Contents

Program Variables and Symbolic ebugging.................................................................................. 3-16
Program Variables and the PICE™ Memory Types....................................................................... 3-18
Managing the Memory and I/O Spaces.............................................................................................. 3-18
The PICE™ Memory M ap............................................................................................................... 3-19
Mapping Input/Output....................................................................................................................... 3-21
Simulating I/O from the Console................................................................................................ 3-22
Simulating I/O with a ebug Procedure.................................................................................... 3-23
The Emulation Clips............................................................................................................................. 3-25
The Clipsin L ines............................................................................................................................. 3-25
The Clipsout Lines........................................................................................................................... 3-25
Emulating a Program............................................................................................................................. 3-26
Preparing a Pascal Program............................................................................................................. 3-26
Compiling the Source F ile ........................................................................................................... 3-27
Linking the Object File................................................................................................ 3-27
Locating the Link File................................................................................................................... 3-27
Creating a Submit F ile ................................................................................................................. 3-27
Getting Ready to Emulate................................................................................................................. 3-28
Emulating Your Program................................................................................................................... 3-30
Breaking, Tracing, and Arming........................................................................................................... 3-33
The Example...................................................................................................................................... 3-33
Emulating a User Program............................................................................................................... 3-34
The Event Machines......................................................................................................................... 3-35
The ebug Registers....................................................................................................................... 3-35
Arm Registers............................................................................................................................... 3-36
Break Registers............................................................................................................................. 3-36
System Registers........................................................................................................................... 3-36
Trace Registers............................................................................................................................. 3-37
Event Registers............................................................................................................................. 3-37
ebug Registers Calling ebug Procedures............................................................................. 3-37
Interpreting the Trace Buffer............................................................................................................. 3-38
The Timetag........................................................................................................................................ 3-42
The Pseudo-variable TRCBUS......................................................................................................... 3-42
Trace Buffer Information................................................................................................................. 3-43
Hardware Slipping on a Breakpoint
....................... ............................................................................. 3-43
Even Addresses, Odd Addresses, and Breaking.................................................................................. 3-44
Word Writes to Even and Odd Addresses........................................................................................ 3-44
Byte Writes to Even and Odd Addresses.......................................................................................... 3-47
Word Reads from Even and Odd Addresses.................................................................................... 3-48
Byte Reads from Even and Odd Addresses ........................... .. ...................................................... 3-51
Moving the User Cable......................................................................................................................... 3-54
CHA TER 4 THE ICE™ SYSTEM ERSONALITY MODULES ( ROBES)
The 8086/8088 Probe........................................................................................................................... 4-1
Hardware and Software Considerations for the 8086/8088 P robe .............................................. 4-2
Address Wrap-Around................................................................................................................... 4-2
Break Information......................................................................................................................... 4-3
REA Y Signal Set-Up Time......................................................................................................... 4-4
Request/Grant Line ........ .. ............................................................................................................ 4-4
age
Contents v

Non-Maskable Interrupt Line and Interrupt Line
....................................................................... 4-4
Non-Maskable Interrupts and Program Stepping
....................................................................... 4-4
Synchronization between the Prototype and the Probe............................................................. 4-4
User-Accessible Test Points......................................................................................................... 4-4
Coprocessor Considerations......................................................................................................... 4-6
Inability to Break when RESET Is A sserted.............................................................................. 4-6
Getting a User NMI while in Emulation Mode ................................................................. 4-6
Using the PICE™ System as a Signal Generator....................................................................... 4-6
10-MHz 8086 Probe MAX Mode Operation
............................................................................. 4-7
Probe MIN Mode Operation.......................................................................................................
.. 4-7
Address/ ata Bus F lo at............................................................................................................... 4-7
The 80186/80188 Probe....................................................................................................................... 4-7
Hardware and Software Considerations for the 80186/80188 Probe
.......................................... 4-8
Address Wrap-Around................................................................................................................... 4-9
Break Information......................................................................................................................... 4-9
Mapping Considerations for the 80186/80188 P robe............................................................... 4-10
Synchronization Between the Prototype and the Probe............................................................. 4-11
User-Accessible Test Points......................................................................................................... 4-11
User Socket.................................................................................................................................... 4-12
The 80286 Probe.................................................................................................................................... 4-12
Address Translation............................................................................................................................ 4-13
8086 Address Translation............................................................................................................. 4-13
80286 Address Translation........................................................................................................... 4-14
Multitasking........................................................................................................................................ 4-16
Interrupts............................................................................................................................................ 4-17
Address Protection............................................................................................................................ 4-17
Real Mode and PCHECK............................................................................................................. 4-18
Protected Mode and PCHECK..................................................................................................... 4-18
Memory Mapping for the 80286 Probe
........................... ........................................................ .. 4-18
Support for Processor Extensions..................................................................................................... 4-19
isplaying 80286 Registers and Flags............................................................................................ 4-19
Real Mode and PCHECK = TRUE.............................................................................................. 4-19
Real Mode and PCHECK = FALSE............................................................................................ 4-19
Protected Mode and PCHECK = TRUE...................................................................................... 4-19
Protected Mode and PCHECK = FALSE.................................................................................... 4-20
Hardware and Software Considerations for the 80286 Probe....................................................... 4-20
Hardware Slipping Past a Breakpoint
............................................................................. .. .......... 4-21
High-Address Bits Override......................................................................................................... 4-22
Issuing a Reset Command When an 80287 Is Present............................................................... 4-22
Resetting the 80286 Chip and the 80286 Probe
......................................................................... 4-24
Timing ifferences Between the iAPX 286 and the 80286 P robe
.......................................... 4-24
User Substrate Capacitor and + 5 Volt Source.
. .. ....................................................................... 4-24
Tracing Considerations.................................................................................................
.. .............. 4-25
User Socket.................
................................. ............................................................ .................... 4-25
Synchronizing Emulation to an External Event......................................................................... 4-25
age
vi Contents

Using the Initialization Segment.................................................................................................. 4-25
Reading from and Mapping to Mapped Memory or I/O ........................................................... 4-26
Pascal-286 and FORTRAN-286 Array Size
............................................................................... 4-26
CHA TER 5 CO ROCESSOR SU ORT
____________________________
Mapping Restrictions When Using Coprocessors............................................................................. 5-1
The PHANG Pseudo-Variable............................................................................................................. 5-1
The 8087/80287 Numeric ata Processors........................................................................................ 5-1
The COENAB Pseudo-Variable...................................................................................................... 5-2
COENAB and an External Coprocessor...................................................................................... 5-3
COENAB and an Internal Coprocessor...................................................................................... 5-3
The CPMO E Pseudo-Variable...................................................................................................... 5-3
The COREQ Pseudo-Variable........................................................................................................... 5-4
The GET87 Command..................................................................................................................... 5-4
CHA TER 6 MULTI LE- ROBE SYSTEMS
___________________________
PICE™ System U nits........................................................................................................................... 6-1
Arming the PICE™ System................................................................................................................... 6-2
Asserting the System Break and Trace Lines...................................................................................... 6-3
Enabling PICE™ System Units............................................................................................................. 6-3
Symbolic Support for Multiple Probes................................................................................................ 6-4
Writing ebug Procedures for Multiple Probe Systems................................................................... 6-5
Synchronization Between U nits........................................................................................................... 6-6
The 8086/8088 and 80186/80188 Probes........................................................................................ 6-6
The 80286 Probe............................................................................................................................... 6-7
A ENDIX A ICE™ SYSTEM NON-HOST HARDWARE INSTALLATION
The PICE™ System Instrumentation Chassis Installation................................................................. A-l
Emulation Base Module Installation.................................................................................................... A-4
Buffer Base Assembly Jumpering.................................................................................................... A-4
Installing Personality Modules and User Cables
............................................................................... A-4
Installing the PICE™ System 8086/8088 Emulation Personality M odule
................................. A-4
Installing the 8086/8088 User C able
......................................................................... .................... A-10
Installing the PICE™ System 80186/80188 Emulation Personality M odule
............................. A-l 1
Installing the 80186/80188 User C able
............................. ............................................................ A-14
Installing the PICE™ System 80286 Emulation Personality M odule
........................... .............. A-16
Installing the 80286 User Cable...................................................................................................... A-16
Installing the Emulation Clips Module................................................................................................ A-18
Installing the iLTA Logic Timing Analyzer Option........................................................................... A-20
Host Installation Information............................................................................................................... A-20
A ENDIX B CONFIGURING THE ICE™ SYSTEM FOR NON-STANDARD
_____________ HOST TERMINALS ___________________________________
Creating a CRT F ile ............................................................................................................................. B-l
Configuration Commands................................................................................................................. B-2
age
Vll
Contents

A ENDIX C (and possibly other host installation appendixes)
________ age
Glossary
Index
TABLES__________________________________________________________
1-1 PICE™ System Hardware Components.................................................................................... 1-9
1- 2 PICE™ System Emulation Clips— C Characteristics
.......................................................... 1-19
2- 1 Main Tutorial Path Screens......................................................................................................... 2-10
2-2 Emulation Aid Module (AI 1) Screens.................................................................................... 2-11
2- 3 PICE™ Feature Aid Module (AI 2) Screens......................................................................... 2-12
3- 1 System Parameters Used with I/O ebug Procedures
............................................................ 3-23
4- 1 8086/8088 Segment Boundary Increments............................................................................... 4-3
4- 2 80186/80188 Segment Boundary Increments........................................................................... 4-10
5- 1 Coprocessor Pseudo-Variable Interaction................................................................................. 5-2
A-l 8086/8088 Emulation Personality Module Jumper Configurations
..................................... A-6
A-2 Jumpering for 8087 Support...................................................................................................... A-7
A-3 Intel Host Installation Appendixes
........................................................................................... A-21
B-l The A Configuration Command Values................................................................................... B-3
B-2 The AF Configuration Command Values................................................................................. B-4
FIGURES
_____________ ; ___________________________________________
1-1 Typical Microcomputer evelopment Process
.................. .................................................... 1-2
1-2 A Basic PICE™ System . .......................................................................................................... 1-5
1-3 A Maximum Configuration PICE™ System........................................................................... 1-7
1- 4 The PICE™ System ebugging Capabilities........................................................................... 1-13
2- 1 Tutorial Introductory Screen: SCR 1.......................................................................................... 2-3
2-2 Tutorial Main Menu: S C R 2...................................................................................................... 2-5
2-3 Menu for the Emulation Aid Modules: AI 1 ......................................................................... 2-6
2-4 Menu for the PICE™ System Feature Modules: AI 2
.......................................................... 2-7
2-5 Emulation isplay for the Screens SCR12 Through SCR15............................................
.. 2-8
2- 6 Tutorial Structure......................................................................................................................... 2-9
3- 1 Sample Trace Buffer INSTRUCTIONS isplay Showing the ata Write for Instruction
#12.......................................................................................................................................... 3-39
3-2 Sample Trace Buffer isplay in CYCLES Mode Showing Frames
f 006-008 and fOOB........................................................................................................... 3-40
3-3 Sample Trace Buffer isplay in INSTRUCTIONS Mode for Emulation with the System
Register EV EN...................................................................................................................... 3-45
3-4 Sample Trace Buffer isplay in CYCLES Mode for Emulation with the System Register
EV EN ...
.................... 3-46
3-5 Sample Trace Buffer isplays in Both Modes for Emulation with the System Register
O ........................................................................................................................................ 3-47
viii Contents

FIGURES (continued)
______________________________________________ age
3-6 Sample Trace Buffer isplays in Both Modes for Emulation with the System Register
EVENWOR ....................................................................................................................... 3-50
3-7 Sample Trace Buffer isplays in Both Modes for Emulation Using the Event Register
O WOR ........................................................................................................................... 3-52
3-8 Sample Trace Buffer isplays in Both Modes for Emulation with the System Register
EVENBYTE......................................................................................................................... 3-53
3- 9 Sample Trace Buffer isplays in Both Modes for Emulation with the System Register
O BYTE........................................................................................................................... 3-55
4- 1 REA Y Signal Set-Up Time..................................................................................................... 4-5
4-2 The G T and the L T.............................................................................................................. 4-15
4-3 80286 Virtual Address Translation........................................................................................... 4-16
4-4 The Segment Register and the escriptor Tables.................................................................... 4-17
4-5 Returning the Probe’s Microprocessor to Real M ode
........................................................... 4-23
6-1 A Multiple-Probe PICE™ System........................................................................................... 6-2
A-1 Power Cable................................................................................................................................ A-2
A-2 Circuit Breaker on the Rear Panel of the PICE™ System Instrumentation Chassis
........... A-2
A-3 Termination Switches on the Rear Panel of the PICE™ System Instrumentation
Chassis................................................................................................................................ A-3
A-4 Instrumentation Chassis Boards............................................................................................... A-5
A-5 Jumper Positions on the Map-I/O B oard................................................................................ A-5
A-6 Jumper Positions on the Buffer B oard.................................................................................... A-6
A-7 New Cable Installation for the 8086/8088 Probe.................................................................... A-7
A-8 8086/8088 Emulation Personality Module Installation
......................................................... A-8
A-9 Jumper Positions on the 8086/8088 Personality Board
......................................................... A-9
A-10 8086/8088 User Cable imensions......................................................................................... A-l 1
A -11 The Correct Orientation of the 8086/8088 User Cable
......................................................... A-12
A-12 80186/80188 and 80286 Emulation Personality Module Installation
.................................. A-13
A-13 Jumper Positions on the 80186/80188 Personality Board..................................................... A-13
A-14 80186/80188 User Cable imensions
........................................ .. . .. .. ................................... A-14
A -15 Connecting the 80186/80188 User Cable................................................................................ A-15
A-16 80286 User Cable imensions................................................................................................. A-17
A -17 Assembling the Emulation Clips Module................................................................................ A-18
A-18 Instrumentation Chassis Cables............................................................................................... A-19
Contents ix/x

REFACE
■ ■ ■ ■ ■ in te rs
This manual introduces Intel’s Integrated Instrumentation and In-Circuit Emulation (PICE™)
system. It assumes that you are familiar with the architecture of the iAPX 86, iAPX 88, iAPX
186, iAPX 188, and iAPX 286 microprocessors. It also assumes that you are familiar with the
concept of in-circuit emulation.
Chapter 1 describes the hardware/software design process and explains how the
PICE system aids this design process. Chapter 1 also provides general
information about the features and components of the PICE system, de
scribes the hardware components of the PICE system, and describes the
PICE system software packages.
Chapter 2 provides an overview of the PICE system on-line tutorial and contains a
listing of the program debugged during the tutorial session.
Chapter 3 introduces the user to the PICE system. This chapter reinforces and aug
ments information provided in the on-line tutorial. It explains symbolic
debugging, PICE debug procedures, file handling, the PICE editor, and
the single-line assembler. The chapter also contains a sample program that
illustrates how to get the PICE system up and running; it describes how to
set up and work with the PICE memory and I/O maps; and it describes
how to set breakpoints and interpret the trace buffer.
Chapter 4 is an overview of how the PICE system operates with the 8086/8088,
80186/80188, and 80286 personality modules (probes). This chapter also
describes special considerations that pertain to each of the probes.
Chapter 5 describes the special debugging aids offered by the PICE system for proto
types that use coprocessors and processor extensions.
Chapter 6 describes the operation of PICE systems with more than one probe.
Appendix A explains how to install PICE system hardware, except hardware that is
installed on the host system.
Appendix B shows how to configure the PICE system to run with non-standard
terminals.
Host Installation
Appendixes explain how to install the PICE system hardware in the host system and how to install the PICE system software.
Glossary defines specific PICE system terms used in this manual.
Index
XI

Related ublications
The following manuals contain additional information about the PICE system and its operating
environment.
Copies of the publications listed are available through the Intel Literature epartment.
I2ICE™ System ublications Library
The following manuals are supplied (together with this manual) with the PICE system; they
contain additional information about the PICE system and its operating environment. Copies
of the publications listed are also available through the Intel Literature epartment, located at
the following address:
Literature epartment
Intel Corporation
3065 Bowers Avenue
Santa Clara, CA 95051
[phone]
• PICE™ Integrated Instrumentation and In-Circuit Emulation System (data sheet), order
number 210469.
This publication provides an overview of the PICE system. It describes the hardware and
software, provides some general application information, and lists the system specifica
tions. The data sheet is available through Intel sales offices as well as the Intel Literature
epartment.
• PICE™ Reference Manual, order number 166302.
This manual is the principle reference for the PICE command language. It includes de
scriptions of PICE commands and PICE topics that are not probe-specific.
• PSCOPE-86 igh-Level Program Debugger User's Guide, order number 121790
[This manual is only supplied to users with Intel hosts.] The manual describes the opera
tion of PSCOPE-86, a high-level language symbolic debugger. It includes a tutorial and
invocation sections, a command dictionary, an error message listing, and configuration
information for non-Intel terminals.
• AEDIT Text Editor Users Guide, order number 121756
This manual describes features and operation of the screen editor that is part of the PICE
system software.
Reference ublications
The publications in the following sections are not supplied with the PICE system.
Xll Preface

Hardware Reference Publications
• Memory Components andbook, order number 210830.
This catalog contains data sheets on the memory components manufactured by Intel
Corporation.
• Microsystems Components andbook, order number 230843 (two volumes).
These handbooks contain data sheets on the microprocessor and peripheral products man
ufactured by Intel Corporation.
• OEM Systems andbook, order number 210941.
This catalog contains data sheets on integrated microcomputer systems, single-board com
puters, memory expansion boards, high-speed math boards (including the iSBC® 337
MULTIMO ULE™ board), peripheral controllers, communications controllers, digital
I/O expansion and signal conditioning boards, industrial control series, and analog I/O
expansion. It also contains data sheets on systems software, such as the iRMX™ operating
system.
• Development Systems andbook, order number 210940.
This catalog contains data sheets on microcomputer development systems (hardware and
software), in-circuit emulators (including the PICE system), network development sys
tems, system design kits, and third-party software.
• iAPX 86/88, 186/188 User's Manual, order number 210911.
This manual contains product descriptions and operating instructions for 8-bit and 16-bit
CPUs and support chips in the iAPX 86/88 and 80186/80188 families.
• iAPX 186 igh Integration 16-Bit Microprocessor (data sheet), order number 210451.
This publication provides an overview of the iAPX 186 microprocessor. It includes chip
pinouts, a functional description, hardware, software, and timing specifications, and an
instruction set summary.
• iAPX 286/10 igh Performance Microprocessor with Memory Management and Protec
tion (data sheet), order number 210253.
This publication provides an overview of the iAPX 286/10 microprocessor. It includes
chip pinouts, a functional description, chip architecture, hardware and timing specifica
tions, and an instruction set summary.
• iAPX 286 ardware Reference Manual, order number 210760.
This manual is the hardware reference guide for iAPX 286 system designs.
• iSBC® 337 MULTIMODULE™ Numeric Data Processor ardware Reference Manual,
order number 142887.
This manual contains design and operation information on the iSBC 337 N P MULTI
MO ULE board. The manual includes installation, program interface, operation, and
service information.
Software Reference Publications
• ASM-86 Language Reference Manual, order number 121703.
This manual provides design and operating information about the ASM-86 assembly
XlllPreface

language. The manual provides an overview of the language, procedures for program
structuring, information about data operation, and an appendix describing the 80186 in
struction set.
• iAPX 86/88 Family Utilities User’s Guide, order number 121616.
This guide provides a full description of the utility commands that support 86/88 program
development. It is intended for use with any language translator that generates object code
compatible with the utility commands.
• 8087 Support Library Reference Manual, order number 121725.
This manual provides design and operating information about the library of support utili
ties for the 8087 processor. It provides overviews of the support library, procedures for
program structuring, and information on data operation.
• iAPX 286 Programmer’s Reference Manual, order number 210498.
This manual describes the iAPX 286 architecture and instruction set.
• iAPX 286 Utilities User’s Guide, order number 121934.
This guide provides a full description of the utility commands that support 286 program
development. It is intended for use with any language translator that generates object code
compatible with the utility commands.
• iAPX286 Operating Systems Writer’s Guide, order number 121960.
This book is written for systems designers, operating system designers, and programmers
using the Intel iAPX 286 microprocessor in its protected, virtual-address mode.
• PL/M-86 Programming Manual, order number 980466.
This manual provides programming instructions for PL/M-86. It includes details on ex
pressions and assignments, procedures, variables, and a sample program.
• PL/M-86 User’s Guide, order number 121636.
• PL/M-286 User’s Guide, order number 121945.
• Pascal-86 User’s Guide, order number 121539.
• FORTRAN-86 User’s Guide, order number 121570.
• iC-86 Compiler User’s Guide, order number 122085.
These guides provide introductory and overview information on the high-level languages
supported by the PICE system. Each manual provides installation instructions, language
information, compiler operating instructions, and information on interfacing to other soft
ware modules.
Command Syntax
The following syntax notation is used throughout the PICE manual set:
COMMAN S Command keywords appear in all uppercase letters. You must enter com
mands exactly as they appear, except that you may enter them in either
uppercase or lowercase letters.
xiv Preface

elements Items for which you must substitute a value, expression, file name, etc., are
in lowercase letters and italicized.
{menu} Braces indicate that you must select one and only one of the items in the
enclosed menu.
{menu}* Braces followed by an asterisk (*) indicate that you must select at least one of
the items in the enclosed menu
[menu] Brackets indicate optional items of which you can select one and only one.
[menu]* Brackets followed by an asterisk (*) indicate optional items of which you can
select more than one item.
punctuation You must enter punctuation other than braces ({ }) and brackets ([ ]) ex
actly as shown. For example, you must enter all the punctuation shown in the
following command:
LIST : FImyprog ■ 001
apostrophe If your terminal has two apostrophes (or single quotes), determine which one
the PICE system accepts in command syntax.
CTRL CTRL denotes the terminal’s control key. For example, CTRL-C means
enter C while pressing the control key.
Preface xv/xvi

REV. REVISION HISTORY DATE
-001 Original Issue. 9/85
xvii/xviii