Intel 81342 User manual

Order Number: 315037-002US
Intel
®
81341 and 81342 I/O
Processors
Developer’s Manual
December 2007

Intel
®
81341 and 81342 I/O Processors
Developer’s Manual December 2007
2Order Number: 315037-002US
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Copyright © 2007, Intel Corporation

Intel
®
81341 and 81342 I/O Processors
December 2007 Developer’s Manual
Order Number: 315037-002US 3
Contents—Intel
®
81341 and 81342
Contents
1.0 Introduction............................................................................................................... 43
1.1 About This Document......................................................................................... 43
1.1.1 How To Read This Document ................................................................... 43
1.1.2 Other Relevant Documents ...................................................................... 43
1.2 About the Single-Core Intel
®
81341 I/O Processor................................................. 44
1.3 Single-Core Intel
®
81341 I/O Processor Features .................................................. 46
1.4 About the Dual-Core Intel
®
81342 I/O Processor ................................................... 47
1.5 Dual-Core Intel
®
81342 I/O Processor Features..................................................... 49
1.5.1 Host Interface........................................................................................ 49
1.5.2 Intel XScale
®
Processor .......................................................................... 49
1.5.3 Internal Busses...................................................................................... 50
1.5.4 Application DMA Controller ...................................................................... 50
1.5.5 Address Translation Unit .........................................................................50
1.5.6 Messaging Unit ...................................................................................... 51
1.5.7 DDR Memory Controller........................................................................... 51
1.5.8 SRAM Memory Controller......................................................................... 51
1.5.9 Peripheral Bus Interface .......................................................................... 51
1.5.10 Performance Monitoring Unit.................................................................... 51
1.5.11 I
2
C Bus Interface Unit............................................................................. 52
1.5.12 UART Unit ............................................................................................. 52
1.5.13 Interrupt Controller Unit.......................................................................... 52
1.5.14 Internal Bus System Controller.................................................................52
1.5.15 Inter-Processor Communication................................................................ 52
1.5.16 Inter-Processor Messaging Unit ................................................................ 52
1.5.17 Timers .................................................................................................. 52
1.5.18 GPIO .................................................................................................... 52
1.6 Terminology and Conventions ............................................................................. 53
1.6.1 Representing Numbers............................................................................ 53
1.6.2 Fields ................................................................................................... 53
1.6.3 Specifying Bit and Signal Values............................................................... 54
1.6.4 Signal Name Conventions........................................................................ 54
1.6.5 Terminology .......................................................................................... 54
2.0 Address Translation Unit (PCI-X) .................................................................................. 55
2.1 Overview ......................................................................................................... 55
2.2 ATU Address Translation .................................................................................... 58
2.2.1 Inbound Transactions ............................................................................. 60
2.2.1.1 Inbound Address Translation ......................................................61
2.2.1.2 Inbound Write Transaction ......................................................... 64
2.2.1.3 Inbound Read Transaction.......................................................... 66
2.2.1.4 Inbound Configuration Cycle Translation ...................................... 69
2.2.1.5 Discard Timers ......................................................................... 71
2.2.2 Outbound Transactions- Single Address Cycle (SAC) Internal Bus Transactions ...
72
2.2.2.1 Outbound Address Translation - Internal Bus Transactions.............. 73
2.2.2.2 Outbound Address Translation Windows....................................... 74
2.2.2.3 Outbound DMA Transactions....................................................... 76
2.2.3 Outbound Write Transaction .................................................................... 77
2.2.4 Outbound Read Transaction..................................................................... 79
2.2.5 Outbound Configuration Cycle Translation.................................................. 80
2.2.5.1 PCI-X Mode 1 Considerations for Outbound Configuration Cycles ..... 80
2.2.5.2 PCI-X Mode 2 Considerations for Outbound Configuration Cycles ..... 81
2.2.5.3 Outbound Configuration Cycle Error Conditions ............................. 81

Intel
®
81341 and 81342—Contents
Intel
®
81341 and 81342 I/O Processors
Developer’s Manual December 2007
4Order Number: 315037-002US
2.2.6 Internal Bus Operation ............................................................................82
2.3 Big Endian Byte Swapping...................................................................................83
2.3.1 Inbound Byte Swapping...........................................................................83
2.3.2 Outbound Byte Swapping.........................................................................84
2.4 CompactPCI Hot-Swap .......................................................................................85
2.4.1 Pin Interface ..........................................................................................85
2.4.1.1 Compact PCI Hot-Swap Mode Select ............................................86
2.5 Expansion ROM Translation Unit...........................................................................87
2.6 ATU Queue Architecture......................................................................................88
2.6.1 Inbound Queues .....................................................................................88
2.6.1.1 Inbound Write Queue Structure...................................................88
2.6.1.2 Inbound Read Queue Structure ...................................................89
2.6.1.3 Inbound Delayed Write Queue.....................................................90
2.6.1.4 Inbound Transaction Queues Command Translation Summary.........90
2.6.2 Outbound Queues...................................................................................91
2.6.2.1 Relaxed Ordering and No Snoop Outbound Request Attributes.........91
2.6.3 Transaction Ordering...............................................................................92
2.6.3.1 Transaction Ordering Summary...................................................95
2.6.4 Byte Parity Checking and Generation.........................................................97
2.6.4.1 Parity Generation ......................................................................97
2.6.4.2 Parity Checking.........................................................................98
2.6.4.3 Parity Disabled..........................................................................98
2.7 ATU Error Conditions..........................................................................................99
2.7.1 Uncorrectable Address and Uncorrectable Attribute Errors on the PCI Interface ..
100
2.7.2 Correctable Address and Correctable Attribute Errors on the PCI Interface....101
2.7.3 Uncorrectable Data Errors on the PCI Interface.........................................102
2.7.3.1 Outbound Read Request Uncorrectable Data Errors ......................103
2.7.3.1.1 Immediate Data Transfer ..................................................103
2.7.3.1.2 Split Response Termination..............................................104
2.7.3.2 Outbound Write Request Uncorrectable Data Errors ..................... 105
2.7.3.2.1 Outbound Writes that are not MSI (Message Signaled Inter-
rupts)105
2.7.3.2.2 MSI Outbound Writes........................................................105
2.7.3.3 Inbound Read Completions Uncorrectable Data Errors .................. 106
2.7.3.4 Inbound Configuration Write Completion Message Uncorrectable Data
Errors106
2.7.3.5 Inbound Read Request Uncorrectable Data Errors ........................ 106
2.7.3.5.1 Immediate Data Transfer ..................................................106
2.7.3.5.2 Split Response Termination..............................................106
2.7.3.6 Inbound Write Request Uncorrectable Data Errors........................ 106
2.7.3.7 Outbound Read Completion Uncorrectable Data Errors ................. 107
2.7.3.8 Outbound Split Write Uncorrectable Data Error Message ...............108
2.7.3.9 Inbound Configuration Write Request.........................................109
2.7.3.9.1 Conventional PCI Mode....................................................109
2.7.3.9.2 PCI-X Mode.......................................................................110
2.7.3.10 Split Completion Messages .......................................................111
2.7.4 Correctable Data Errors on the PCI Interface ............................................112
2.7.4.1 Inbound Read Request Correctable Data Errors ...........................112
2.7.4.1.1 Immediate Data Transfer ..................................................112
2.7.4.1.2 Split Response Termination..............................................112
2.7.4.2 Inbound Write Request Correctable Data Errors...........................112
2.7.4.3 Outbound Read Completion Correctable Data Errors..................... 113
2.7.4.4 Inbound Configuration Write Request.........................................113
2.7.4.5 Split Completion Messages .......................................................113
2.7.5 Master Aborts on the PCI Interface..........................................................114

Intel
®
81341 and 81342 I/O Processors
December 2007 Developer’s Manual
Order Number: 315037-002US 5
Contents—Intel
®
81341 and 81342
2.7.5.1 Master Aborts for Outbound Read or Write Request ..................... 114
2.7.5.2 Inbound Read Completion or Inbound Configuration Write Completion
Message115
2.7.5.3 Master-Aborts Signaled by the ATU as a Target........................... 115
2.7.5.3.1 Uncorrectable Address Errors...........................................115
2.7.5.3.2 Internal Bus Master-Abort .................................................115
2.7.6 Target Aborts on the PCI Interface.......................................................... 116
2.7.6.1 Target Aborts for Outbound Read Request or Outbound Write Request .
116
2.7.6.2 Inbound Read Completion or Inbound Configuration Write Completion
Message117
2.7.6.3 Target-Aborts Signaled by the ATU as a Target ........................... 117
2.7.6.3.1 Internal Bus Master Abort..................................................117
2.7.6.3.2 Internal Bus Target Abort..................................................117
2.7.6.3.3 Inbound EROM Memory Write..........................................117
2.7.7 Corrupted or Unexpected Split Completions ............................................. 118
2.7.7.1 Completer Address.................................................................. 118
2.7.7.2 Completer Attributes ............................................................... 118
2.7.8 SERR# Assertion and Detection.............................................................. 119
2.7.9 Internal Bus Error Conditions ................................................................. 120
2.7.9.1 Master Abort on the Internal Bus .............................................. 120
2.7.9.1.1 Inbound Write Request......................................................120
2.7.9.1.2 Inbound Read Request .....................................................121
2.7.9.2 Target Abort on the Internal Bus............................................... 122
2.7.9.2.1 Conventional Mode ...........................................................122
2.7.9.2.2 PCI-X Mode.......................................................................122
2.7.9.3 Parity Error on the Internal Bus ................................................ 123
2.7.9.3.1 Conventional Mode ...........................................................123
2.7.9.3.2 PCI-X Mode.......................................................................123
2.7.10 ATU Error Summary ............................................................................. 124
2.8 Message-Signaled Interrupts............................................................................. 130
2.9 Internal Interrupts .......................................................................................... 131
2.10 Vital Product Data ........................................................................................... 132
2.10.1 Configuring Vital Product Data Operation................................................. 132
2.10.2 Accessing Vital Product Data.................................................................. 133
2.10.2.1 Reading Vital Product Data....................................................... 133
2.10.2.2 Writing Vital Product Data ........................................................ 134
2.11 Central Resource Functionality .......................................................................... 135
2.11.1 Multi-Function Support.......................................................................... 135
2.11.2 Inbound Transactions ........................................................................... 135
2.11.3 Outbound Transactions ......................................................................... 135
2.11.4 PCI Reset ( P_RSTOUT# )...................................................................... 135
2.11.5 PCI Clock Outputs ( P_CLKOUT , P_CLKO[3:0] ) ...................................... 135
2.11.6 External Clock Driver ( CR_FREQ[1:0] ) .................................................. 136
2.11.7 Bus Mode and Frequency Initialization..................................................... 137
2.12 Embedded Bridge Functionality ......................................................................... 141
2.13 Register Definitions ......................................................................................... 144
2.13.1 PCI Configuration Registers ................................................................... 144
2.13.2 Internal Bus Registers........................................................................... 148
2.13.3 ATU Vendor ID Register - ATUVID .......................................................... 152
2.13.4 ATU Device ID Register - ATUDID........................................................... 152
2.13.5 ATU Command Register - ATUCMD ......................................................... 153
2.13.6 ATU Status Register - ATUSR................................................................. 154
2.13.7 ATU Revision ID Register - ATURID......................................................... 156
2.13.8 ATU Class Code Register - ATUCCR......................................................... 156
2.13.9 ATU Cacheline Size Register - ATUCLSR................................................... 157

Intel
®
81341 and 81342—Contents
Intel
®
81341 and 81342 I/O Processors
Developer’s Manual December 2007
6Order Number: 315037-002US
2.13.10ATU Latency Timer Register - ATULT .......................................................157
2.13.11ATU Header Type Register - ATUHTR .......................................................158
2.13.12ATU BIST Register - ATUBISTR...............................................................159
2.13.13Inbound ATU Base Address Register 0 - IABAR0........................................160
2.13.14Inbound ATU Upper Base Address Register 0 - IAUBAR0 ............................161
2.13.15Inbound ATU Base Address Register 1 - IABAR1........................................162
2.13.16Inbound ATU Upper Base Address Register 1 - IAUBAR1 ............................163
2.13.17Inbound ATU Base Address Register 2 - IABAR2........................................164
2.13.18Inbound ATU Upper Base Address Register 2 - IAUBAR2 ............................165
2.13.19ATU Subsystem Vendor ID Register - ASVIR.............................................166
2.13.20ATU Subsystem ID Register - ASIR .........................................................166
2.13.21Expansion ROM Base Address Register - ERBAR........................................167
2.13.22ATU Capabilities Pointer Register - ATU_Cap_Ptr .......................................168
2.13.23Determining Block Sizes for Base Address Registers ..................................169
2.13.24ATU Interrupt Line Register - ATUILR ......................................................171
2.13.25ATU Interrupt Pin Register - ATUIPR........................................................172
2.13.26ATU Minimum Grant Register - ATUMGNT.................................................172
2.13.27ATU Maximum Latency Register - ATUMLAT..............................................173
2.13.28Inbound ATU Limit Register 0 - IALR0......................................................174
2.13.29Inbound ATU Translate Value Register 0 - IATVR0..................................... 175
2.13.30Inbound ATU Upper Translate Value Register 0 - IAUTVR0..........................175
2.13.31Inbound ATU Limit Register 1 - IALR1......................................................176
2.13.32Inbound ATU Translate Value Register 1 - IATVR1..................................... 177
2.13.33Inbound ATU Upper Translate Value Register 1 - IAUTVR1..........................177
2.13.34Inbound ATU Limit Register 2 - IALR2......................................................178
2.13.35Inbound ATU Translate Value Register 2 - IATVR2..................................... 179
2.13.36Inbound ATU Upper Translate Value Register 2 - IAUTVR2..........................179
2.13.37Expansion ROM Limit Register - ERLR......................................................180
2.13.38Expansion ROM Translate Value Register - ERTVR .....................................181
2.13.39Expansion ROM Upper Translate Value Register - ERUTVR ..........................181
2.13.40ATU Configuration Register - ATUCR........................................................182
2.13.41PCI Configuration and Status Register - PCSR...........................................183
2.13.42ATU Interrupt Status Register - ATUISR...................................................186
2.13.43ATU Interrupt Mask Register - ATUIMR ....................................................188
2.13.44VPD Capability Identifier Register - VPD_Cap_ID....................................... 190
2.13.45VPD Next Item Pointer Register - VPD_Next_Item_Ptr ...............................190
2.13.46VPD Address Register - VPDAR ...............................................................191
2.13.47 VPD Data Register - VPDDR................................................................... 191
2.13.48PM Capability Identifier Register - PM_Cap_ID ..........................................192
2.13.49PM Next Item Pointer Register - PM_Next_Item_Ptr...................................192
2.13.50ATU Power Management Capabilities Register - APMCR .............................. 193
2.13.51ATU Power Management Control/Status Register - APMCSR........................ 194
2.13.52ATU Scratch Pad Register - ATUSPR ........................................................195
2.13.53PCI-X Capability Identifier Register - PCI-X_Cap_ID .................................. 195
2.13.54PCI-X Next Item Pointer Register - PCI-X_Next_Item_Ptr...........................196
2.13.55PCI-X Command Register - PCIXCMD ......................................................196
2.13.56PCI-X Status Register - PCIXSR ..............................................................198
2.13.57ECC Control and Status Register - ECCCSR............................................... 200
2.13.58ECC First Address Register - ECCFAR....................................................... 203
2.13.59ECC Second Address Register - ECCSAR ..................................................204
2.13.60ECC Attribute Register - ECCAR ..............................................................205
2.13.61CompactPCI Hot-Swap Capability ID Register ...........................................205
2.13.62Offset EDh: HS_NXTP - Next Item Pointer................................................206
2.13.63HS_CNTRL - Hot-Swap Control/Status Register.........................................207
2.13.64Inbound ATU Base Address Register 3 - IABAR3........................................209

Intel
®
81341 and 81342 I/O Processors
December 2007 Developer’s Manual
Order Number: 315037-002US 7
Contents—Intel
®
81341 and 81342
2.13.65Inbound ATU Upper Base Address Register 3 - IAUBAR3............................ 210
2.13.66Inbound ATU Limit Register 3 - IALR3 ..................................................... 211
2.13.67Inbound ATU Translate Value Register 3 - IATVR3 .................................... 212
2.13.68Inbound ATU Upper Translate Value Register 3 - IAUTVR3 ......................... 212
2.13.69Outbound I/O Base Address Register - OIOBAR ........................................ 213
2.13.70Outbound I/O Window Translate Value Register - OIOWTVR....................... 214
2.13.71Outbound Upper Memory Window Base Address Register 0 - OUMBAR0 ....... 215
2.13.72Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0
216
2.13.73Outbound Upper Memory Window Base Address Register 1 - OUMBAR1 ....... 217
2.13.74Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1
218
2.13.75Outbound Upper Memory Window Base Address Register 2 - OUMBAR2 ....... 219
2.13.76Outbound Upper 32-bit Memory Window Translate Value Register 2 - OUMWTVR2
220
2.13.77Outbound Upper Memory Window Base Address Register 3 - OUMBAR3 ....... 221
2.13.78Outbound Upper 32-bit Memory Window Translate Value Register 3 - OUMWTVR3
222
2.13.79Outbound Configuration Cycle Address Register - OCCAR........................... 223
2.13.80Outbound Configuration Cycle Data Register - OCCDR............................... 224
2.13.81Outbound Configuration Cycle Function Number - OCCFN .......................... 224
2.13.82PCI Interface Error Control and Status Register - PIECSR........................... 225
2.13.83PCI Interface Error Address Register - PCIEAR.......................................... 226
2.13.84PCI Interface Error Upper Address Register - PCIEUAR .............................. 227
2.13.85PCI Interface Error Context Address Register — PCIECAR .......................... 228
2.13.86Internal Arbiter Control Register - IACR................................................... 229
2.13.87Multi-Transaction Timer - MTT................................................................ 230
2.13.88PCIX RCOMP Control Register — PRCR .................................................... 231
2.13.89PCIX Pad ODT Drive Strength Manual Override Values Registers — PPODSMOVR
232
2.13.90PCIX PAD DRIVE STRENGTH Manual Override Values ........ Register(3.3 V/1.5 V
Switch Supply Voltage) — PPDSMOVR3.3_1.5233
2.13.91PCIX PAD DRIVE STRENGTH Manual Override Values Register (3.3 V Dedicated
Supply Voltage) — PPDSMOVR3.3234
3.0 Address Translation Unit (PCI Express)........................................................................ 235
3.1 Overview ....................................................................................................... 235
3.2 PCI Express Link Characteristics ........................................................................ 238
3.3 ATU Address Translation .................................................................................. 239
3.3.1 Inbound Transactions ........................................................................... 242
3.3.1.1 Inbound Address Translation .................................................... 242
3.3.1.2 Inbound Memory Write Transaction ........................................... 245
3.3.1.3 Inbound Memory Read Transaction ........................................... 246
3.3.1.4 Inbound I/O Cycle Translation .................................................. 247
3.3.1.5 Inbound Configuration Cycle Translation (ID Routed)................... 247
3.3.1.6 Inbound Vendor_Defined Message Transactions .......................... 248
3.3.2 Outbound Transactions ......................................................................... 249
3.3.2.1 Outbound Address Translation - Internal Bus Transactions............ 250
3.3.2.2 Outbound Address Translation Windows..................................... 251
3.3.2.3 Outbound DMA Transactions..................................................... 254
3.3.2.4 Outbound Function Number...................................................... 254
3.3.3 Outbound Write Transaction .................................................................. 255
3.3.4 Outbound Read Transaction................................................................... 256
3.3.5 Outbound Configuration Cycle Translation................................................ 257
3.3.5.1 Outbound Configuration Cycle Error Conditions ........................... 257
3.3.5.2 Outbound Configuration Completions with Retry Status (CRS)....... 257
3.3.5.3 Outbound PCI Express Message Transactions.............................. 258

Intel
®
81341 and 81342—Contents
Intel
®
81341 and 81342 I/O Processors
Developer’s Manual December 2007
8Order Number: 315037-002US
3.3.5.4 Completion Timeout Mechanism ................................................258
3.4 Big Endian Byte Swapping.................................................................................259
3.4.1 Inbound Byte Swapping.........................................................................259
3.4.2 Outbound Byte Swapping.......................................................................260
3.5 Messaging Unit................................................................................................261
3.6 PCI Express Messages ......................................................................................262
3.7 Expansion ROM Translation Unit.........................................................................264
3.8 ATU Queue Architecture....................................................................................265
3.8.1 Inbound Queues ...................................................................................265
3.8.1.1 Inbound Posted Queue Structure...............................................265
3.8.1.2 Inbound Non Posted Queue Structure ........................................266
3.8.1.3 Inbound Completion Queue Structure ........................................266
3.8.1.4 Inbound Transaction Queues Command Translation Summary .......266
3.8.2 Outbound Queues.................................................................................267
3.8.2.1 Relaxed Ordering and No Snoop Outbound Request Attributes.......267
3.8.3 Transaction Ordering.............................................................................268
3.8.3.1 Transaction Ordering Summary.................................................271
3.8.4 Byte Parity Checking and Generation.......................................................272
3.8.4.1 Parity Generation ....................................................................272
3.8.4.2 Parity Checking.......................................................................273
3.8.4.3 Parity Disabled........................................................................273
3.9 ATU Error Conditions........................................................................................274
3.9.1 PCI Express Errors ................................................................................275
3.9.1.1 Role Based Error Reporting.......................................................275
3.9.1.2 Malformed Packets ..................................................................276
3.9.1.3 ECRC Check Failed ..................................................................276
3.9.1.4 Unsupported Request...............................................................277
3.9.1.5 Completer Abort......................................................................277
3.9.1.6 Unexpected Completions ..........................................................277
3.9.1.7 Poisoned TLP Received.............................................................278
3.9.1.8 Completion Timeout ................................................................278
3.9.2 Parity Error on the Internal Bus ..............................................................279
3.9.3 ATU Error Summary..............................................................................279
3.10 PCI Express Hot-Plug Support ...........................................................................283
3.11 Reset.............................................................................................................284
3.12 Message-Signaled Interrupts.............................................................................285
3.12.1 Legacy Interrupts .................................................................................285
3.12.2 Internal Interrupts................................................................................285
3.13 Vital Product Data............................................................................................286
3.13.1 Configuring Vital Product Data Operation .................................................286
3.13.2 Accessing Vital Product Data ..................................................................287
3.13.2.1 Reading Vital Product Data .......................................................287
3.13.2.2 Writing Vital Product Data ........................................................288
3.14 Root Complex Functionality...............................................................................289
3.15 Embedded Bridge Functionality..........................................................................290
3.16 Register Definitions..........................................................................................293
3.16.1 Extended Capabilities Registers ..............................................................294
3.16.2 Internal Bus Addresses..........................................................................297
3.16.3 ATU Vendor ID Register - ATUVID...........................................................301
3.16.4 ATU Device ID Register - ATUDID ...........................................................301
3.16.5 ATU Command Register - ATUCMD..........................................................302
3.16.6 ATU Status Register - ATUSR .................................................................303
3.16.7 ATU Revision ID Register - ATURID .........................................................304
3.16.8 ATU Class Code Register - ATUCCR .........................................................304
3.16.9 ATU Cacheline Size Register - ATUCLSR................................................... 305
3.16.10ATU Latency Timer Register - ATULT .......................................................305

Intel
®
81341 and 81342 I/O Processors
December 2007 Developer’s Manual
Order Number: 315037-002US 9
Contents—Intel
®
81341 and 81342
3.16.11ATU Header Type Register - ATUHTR....................................................... 306
3.16.12ATU BIST Register - ATUBISTR............................................................... 307
3.16.13Inbound ATU Base Address Register 0 - IABAR0 ....................................... 308
3.16.14Inbound ATU Upper Base Address Register 0 - IAUBAR0............................ 309
3.16.15Determining Block Sizes for Base Address Registers.................................. 310
3.16.16Inbound ATU Base Address Register 1 - IABAR1 ....................................... 312
3.16.17Inbound ATU Upper Base Address Register 1 - IAUBAR1............................ 313
3.16.18Inbound ATU Base Address Register 2 - IABAR2 ....................................... 314
3.16.19Inbound ATU Upper Base Address Register 2 - IAUBAR2............................ 315
3.16.20ATU Subsystem Vendor ID Register - ASVIR ............................................ 316
3.16.21ATU Subsystem ID Register - ASIR......................................................... 316
3.16.22Expansion ROM Base Address Register - ERBAR........................................ 317
3.16.23ATU Capabilities Pointer Register - ATU_Cap_Ptr....................................... 318
3.16.24ATU Interrupt Line Register - ATUILR...................................................... 319
3.16.25ATU Interrupt Pin Register - ATUIPR ....................................................... 320
3.16.26ATU Minimum Grant Register - ATUMGNT ................................................ 320
3.16.27ATU Maximum Latency Register - ATUMLAT ............................................. 321
3.16.28Inbound ATU Limit Register 0 - IALR0 ..................................................... 322
3.16.29Inbound ATU Translate Value Register 0 - IATVR0 .................................... 323
3.16.30Inbound ATU Upper Translate Value Register 0 - IAUTVR0 ......................... 323
3.16.31Inbound ATU Limit Register 1 - IALR1 ..................................................... 324
3.16.32Inbound ATU Translate Value Register 1 - IATVR1 .................................... 325
3.16.33Inbound ATU Upper Translate Value Register 1 - IAUTVR1 ......................... 325
3.16.34Inbound ATU Limit Register 2 - IALR2 ..................................................... 326
3.16.35Inbound ATU Translate Value Register 2 - IATVR2 .................................... 327
3.16.36Inbound ATU Upper Translate Value Register 2 - IAUTVR2 ......................... 328
3.16.37Expansion ROM Limit Register - ERLR...................................................... 328
3.16.38Expansion ROM Translate Value Register - ERTVR..................................... 329
3.16.39Expansion ROM Upper Translate Value Register - ERUTVR.......................... 329
3.16.40ATU Configuration Register - ATUCR ....................................................... 330
3.16.41PCI Configuration and Status Register - PCSR .......................................... 331
3.16.42ATU Interrupt Status Register - ATUISR .................................................. 333
3.16.43ATU Interrupt Mask Register - ATUIMR.................................................... 336
3.16.44PCI Express Message Control/Status Register - PEMCSR ............................ 337
3.16.45PCI Express Link Control/Status Register - PELCSR ................................... 338
3.16.46VPD Capability Identifier Register - VPD_Cap_ID ...................................... 339
3.16.47VPD Next Item Pointer Register - VPD_Next_Item_Ptr............................... 339
3.16.48VPD Address Register - VPDAR............................................................... 340
3.16.49VPD Data Register - VPDDR ................................................................... 340
3.16.50PM Capability Identifier Register - PM_Cap_ID.......................................... 341
3.16.51PM Next Item Pointer Register - PM_Next_Item_Ptr .................................. 341
3.16.52ATU Power Management Capabilities Register - APMCR.............................. 342
3.16.53ATU Power Management Control/Status Register - APMCSR ....................... 343
3.16.54ATU Scratch Pad Register - ATUSPR........................................................ 344
3.16.55PCI Express Capability List Register - PCIE_CAPID .................................... 344
3.16.56PCI Express Next Item Pointer Register - PCIE_NXTP ................................ 345
3.16.57PCI Express Capabilities Register - PCIE_CAP ........................................... 346
3.16.58PCI Express Device Capabilities Register - PCIE_DCAP............................... 347
3.16.59PCI Express Device Control Register - PE_DCTL........................................ 348
3.16.60PCI Express Device Status Register - PE_DSTS......................................... 350
3.16.61PCI Express Link Capabilities Register - PE_LCAP...................................... 351
3.16.62PCI Express Link Control Register - PE_LCTL ............................................ 352
3.16.63PCI Express Link Status Register - PE_LSTS............................................. 353
3.16.64PCI Express Slot Capabilities Register - PE_SCAP...................................... 354
3.16.65PCI Express Slot Control Register - PE_SCR ............................................. 355

Intel
®
81341 and 81342—Contents
Intel
®
81341 and 81342 I/O Processors
Developer’s Manual December 2007
10 Order Number: 315037-002US
3.16.66PCI Express Slot Status Register - PE_SSTS .............................................356
3.16.67PCI Express Root Control Register - PE_RCR.............................................357
3.16.68PCI Express Root Status Register - PE_RSR.............................................. 358
3.16.69PCI Express Advanced Error Capability Identifier - ADVERR_CAPID.............. 359
3.16.70PCI Express Uncorrectable Error Status - ERRUNC_STS..............................360
3.16.71PCI Express Uncorrectable Error Mask - ERRUNC_MSK...............................361
3.16.72PCI Express Uncorrectable Error Severity - ERRUNC_SEV ........................... 362
3.16.73PCI Express Correctable Error Status - ERRCOR_STS................................. 363
3.16.74PCI Express Correctable Error Mask - ERRCOR_MSK ..................................364
3.16.75Advanced Error Control and Capability Register - ADVERR_CTL ...................365
3.16.76PCI Express Advanced Error Header Log - ADVERR_LOG0 ..........................365
3.16.77PCI Express Advanced Error Header Log - ADVERR_LOG1 ..........................366
3.16.78PCI Express Advanced Error Header Log - ADVERR_LOG2 ..........................366
3.16.79PCI Express Advanced Error Header Log - ADVERR_LOG3 ..........................367
3.16.80Root Error Command Register - RERR_CMD .............................................367
3.16.81Root Error Status Register .....................................................................368
3.16.82Error Source Identification Register - RERR_ID .........................................369
3.16.83Device Serial Number Capability - DSN_CAP.............................................369
3.16.84Device Serial Number Lower DW Register - DSN_LDW ...............................370
3.16.85Device Serial Number Upper DW Register - DSN_UDW...............................370
3.16.86PCI Express Advisory Error Control Register - PIE_AEC .............................. 371
3.16.87Power Budgeting Enhanced Capability Header - PWRBGT_CAPID ................. 372
3.16.88Power Budgeting Data Select Register - PWRBGT_DSEL .............................372
3.16.89Power Budgeting Data Register - PWRBGT_DATA ......................................373
3.16.90Power Budgeting Capability Register - PWRBGT_CAP ................................. 374
3.16.91Power Budgeting Information Registers[0:23]—PWRBGT_INFO[0:23] ..........375
3.16.92Outbound I/O Base Address Register - OIOBAR......................................... 376
3.16.93Outbound I/O Window Translate Value Register - OIOWTVR .......................377
3.16.94Outbound Upper Memory Window Base Address Register 0 - OUMBAR0........ 378
3.16.95Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0
379
3.16.96Outbound Upper Memory Window Base Address Register 1 - OUMBAR1........ 380
3.16.97Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1
381
3.16.98Outbound Upper Memory Window Base Address Register 2 - OUMBAR2........ 382
3.16.99Outbound Upper 32-bit Memory Window Translate Value Register 2 - OUMWTVR2
383
3.16.100Outbound Upper Memory Window Base Address Register 3 - OUMBAR3 ......384
3.16.101Outbound Upper 32-bit Memory Window Translate Value Register 3 -
OUMWTVR3385
3.16.102Outbound Configuration Cycle Address Register - OCCAR..........................386
3.16.103Outbound Configuration Cycle Data Register - OCCDR..............................387
3.16.104Outbound Configuration Cycle Function Number - OCCFN .........................388
3.16.105Inbound Vendor Message Header Register 0 - IVMHR0 .............................389
3.16.106Inbound Vendor Message Header Register 1 - IVMHR1 .............................390
3.16.107Inbound Vendor Message Header Register 2 - IVMHR2 .............................391
3.16.108Inbound Vendor Message Header Register 3 - IVMHR3 .............................392
3.16.109Inbound Vendor Message Payload Register - IVMPR .................................392
3.16.110Outbound Vendor Message Header Register 0 - OVMHR0 ..........................393
3.16.111Outbound Vendor Message Header Register 1 - OVMHR1 ..........................394
3.16.112Outbound Vendor Message Header Register 2 - OVMHR2 ..........................395
3.16.113Outbound Vendor Message Header Register 3 - OVMHR3 ..........................395
3.16.114Outbound Vendor Message Payload Register - OVMPR ..............................396
3.16.115PCI Interface Error Control and Status Register - PIE_CSR........................ 397
3.16.116PCI Interface Error Status - PIE_STS .....................................................398