Intel 81342 User manual

Order Number: 315037-002US

Intel

81341 and 81342 I/O

Processors

Developer’s Manual

December 2007

Intel

81341 and 81342 I/O Processors

Developer’s Manual December 2007

2Order Number: 315037-002US

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Current characterized errata are available on request.

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Intel

81341 and 81342 I/O Processors

December 2007 Developer’s Manual

Order Number: 315037-002US 3

Contents—Intel

81341 and 81342

Contents

1.0 Introduction............................................................................................................... 43

1.1 About This Document......................................................................................... 43

1.1.1 How To Read This Document ................................................................... 43

1.1.2 Other Relevant Documents ...................................................................... 43

1.2 About the Single-Core Intel

81341 I/O Processor................................................. 44

1.3 Single-Core Intel

81341 I/O Processor Features .................................................. 46

1.4 About the Dual-Core Intel

81342 I/O Processor ................................................... 47

1.5 Dual-Core Intel

81342 I/O Processor Features..................................................... 49

1.5.1 Host Interface........................................................................................ 49

1.5.2 Intel XScale

Processor .......................................................................... 49

1.5.3 Internal Busses...................................................................................... 50

1.5.4 Application DMA Controller ...................................................................... 50

1.5.5 Address Translation Unit .........................................................................50

1.5.6 Messaging Unit ...................................................................................... 51

1.5.7 DDR Memory Controller........................................................................... 51

1.5.8 SRAM Memory Controller......................................................................... 51

1.5.9 Peripheral Bus Interface .......................................................................... 51

1.5.10 Performance Monitoring Unit.................................................................... 51

1.5.11 I

C Bus Interface Unit............................................................................. 52

1.5.12 UART Unit ............................................................................................. 52

1.5.13 Interrupt Controller Unit.......................................................................... 52

1.5.14 Internal Bus System Controller.................................................................52

1.5.15 Inter-Processor Communication................................................................ 52

1.5.16 Inter-Processor Messaging Unit ................................................................ 52

1.5.17 Timers .................................................................................................. 52

1.5.18 GPIO .................................................................................................... 52

1.6 Terminology and Conventions ............................................................................. 53

1.6.1 Representing Numbers............................................................................ 53

1.6.2 Fields ................................................................................................... 53

1.6.3 Specifying Bit and Signal Values............................................................... 54

1.6.4 Signal Name Conventions........................................................................ 54

1.6.5 Terminology .......................................................................................... 54

2.0 Address Translation Unit (PCI-X) .................................................................................. 55

2.1 Overview ......................................................................................................... 55

2.2 ATU Address Translation .................................................................................... 58

2.2.1 Inbound Transactions ............................................................................. 60

2.2.1.1 Inbound Address Translation ......................................................61

2.2.1.2 Inbound Write Transaction ......................................................... 64

2.2.1.3 Inbound Read Transaction.......................................................... 66

2.2.1.4 Inbound Configuration Cycle Translation ...................................... 69

2.2.1.5 Discard Timers ......................................................................... 71

2.2.2 Outbound Transactions- Single Address Cycle (SAC) Internal Bus Transactions ...

2.2.2.1 Outbound Address Translation - Internal Bus Transactions.............. 73

2.2.2.2 Outbound Address Translation Windows....................................... 74

2.2.2.3 Outbound DMA Transactions....................................................... 76

2.2.3 Outbound Write Transaction .................................................................... 77

2.2.4 Outbound Read Transaction..................................................................... 79

2.2.5 Outbound Configuration Cycle Translation.................................................. 80

2.2.5.1 PCI-X Mode 1 Considerations for Outbound Configuration Cycles ..... 80

2.2.5.2 PCI-X Mode 2 Considerations for Outbound Configuration Cycles ..... 81

2.2.5.3 Outbound Configuration Cycle Error Conditions ............................. 81

Intel

81341 and 81342—Contents

Intel

81341 and 81342 I/O Processors

Developer’s Manual December 2007

4Order Number: 315037-002US

2.2.6 Internal Bus Operation ............................................................................82

2.3 Big Endian Byte Swapping...................................................................................83

2.3.1 Inbound Byte Swapping...........................................................................83

2.3.2 Outbound Byte Swapping.........................................................................84

2.4 CompactPCI Hot-Swap .......................................................................................85

2.4.1 Pin Interface ..........................................................................................85

2.4.1.1 Compact PCI Hot-Swap Mode Select ............................................86

2.5 Expansion ROM Translation Unit...........................................................................87

2.6 ATU Queue Architecture......................................................................................88

2.6.1 Inbound Queues .....................................................................................88

2.6.1.1 Inbound Write Queue Structure...................................................88

2.6.1.2 Inbound Read Queue Structure ...................................................89

2.6.1.3 Inbound Delayed Write Queue.....................................................90

2.6.1.4 Inbound Transaction Queues Command Translation Summary.........90

2.6.2 Outbound Queues...................................................................................91

2.6.2.1 Relaxed Ordering and No Snoop Outbound Request Attributes.........91

2.6.3 Transaction Ordering...............................................................................92

2.6.3.1 Transaction Ordering Summary...................................................95

2.6.4 Byte Parity Checking and Generation.........................................................97

2.6.4.1 Parity Generation ......................................................................97

2.6.4.2 Parity Checking.........................................................................98

2.6.4.3 Parity Disabled..........................................................................98

2.7 ATU Error Conditions..........................................................................................99

2.7.1 Uncorrectable Address and Uncorrectable Attribute Errors on the PCI Interface ..

100

2.7.2 Correctable Address and Correctable Attribute Errors on the PCI Interface....101

2.7.3 Uncorrectable Data Errors on the PCI Interface.........................................102

2.7.3.1 Outbound Read Request Uncorrectable Data Errors ......................103

2.7.3.1.1 Immediate Data Transfer ..................................................103

2.7.3.1.2 Split Response Termination..............................................104

2.7.3.2 Outbound Write Request Uncorrectable Data Errors ..................... 105

2.7.3.2.1 Outbound Writes that are not MSI (Message Signaled Inter-

rupts)105

2.7.3.2.2 MSI Outbound Writes........................................................105

2.7.3.3 Inbound Read Completions Uncorrectable Data Errors .................. 106

2.7.3.4 Inbound Configuration Write Completion Message Uncorrectable Data

Errors106

2.7.3.5 Inbound Read Request Uncorrectable Data Errors ........................ 106

2.7.3.5.1 Immediate Data Transfer ..................................................106

2.7.3.5.2 Split Response Termination..............................................106

2.7.3.6 Inbound Write Request Uncorrectable Data Errors........................ 106

2.7.3.7 Outbound Read Completion Uncorrectable Data Errors ................. 107

2.7.3.8 Outbound Split Write Uncorrectable Data Error Message ...............108

2.7.3.9 Inbound Configuration Write Request.........................................109

2.7.3.9.1 Conventional PCI Mode....................................................109

2.7.3.9.2 PCI-X Mode.......................................................................110

2.7.3.10 Split Completion Messages .......................................................111

2.7.4 Correctable Data Errors on the PCI Interface ............................................112

2.7.4.1 Inbound Read Request Correctable Data Errors ...........................112

2.7.4.1.1 Immediate Data Transfer ..................................................112

2.7.4.1.2 Split Response Termination..............................................112

2.7.4.2 Inbound Write Request Correctable Data Errors...........................112

2.7.4.3 Outbound Read Completion Correctable Data Errors..................... 113

2.7.4.4 Inbound Configuration Write Request.........................................113

2.7.4.5 Split Completion Messages .......................................................113

2.7.5 Master Aborts on the PCI Interface..........................................................114

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81341 and 81342 I/O Processors

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Contents—Intel

81341 and 81342

2.7.5.1 Master Aborts for Outbound Read or Write Request ..................... 114

2.7.5.2 Inbound Read Completion or Inbound Configuration Write Completion

Message115

2.7.5.3 Master-Aborts Signaled by the ATU as a Target........................... 115

2.7.5.3.1 Uncorrectable Address Errors...........................................115

2.7.5.3.2 Internal Bus Master-Abort .................................................115

2.7.6 Target Aborts on the PCI Interface.......................................................... 116

2.7.6.1 Target Aborts for Outbound Read Request or Outbound Write Request .

116

2.7.6.2 Inbound Read Completion or Inbound Configuration Write Completion

Message117

2.7.6.3 Target-Aborts Signaled by the ATU as a Target ........................... 117

2.7.6.3.1 Internal Bus Master Abort..................................................117

2.7.6.3.2 Internal Bus Target Abort..................................................117

2.7.6.3.3 Inbound EROM Memory Write..........................................117

2.7.7 Corrupted or Unexpected Split Completions ............................................. 118

2.7.7.1 Completer Address.................................................................. 118

2.7.7.2 Completer Attributes ............................................................... 118

2.7.8 SERR# Assertion and Detection.............................................................. 119

2.7.9 Internal Bus Error Conditions ................................................................. 120

2.7.9.1 Master Abort on the Internal Bus .............................................. 120

2.7.9.1.1 Inbound Write Request......................................................120

2.7.9.1.2 Inbound Read Request .....................................................121

2.7.9.2 Target Abort on the Internal Bus............................................... 122

2.7.9.2.1 Conventional Mode ...........................................................122

2.7.9.2.2 PCI-X Mode.......................................................................122

2.7.9.3 Parity Error on the Internal Bus ................................................ 123

2.7.9.3.1 Conventional Mode ...........................................................123

2.7.9.3.2 PCI-X Mode.......................................................................123

2.7.10 ATU Error Summary ............................................................................. 124

2.8 Message-Signaled Interrupts............................................................................. 130

2.9 Internal Interrupts .......................................................................................... 131

2.10 Vital Product Data ........................................................................................... 132

2.10.1 Configuring Vital Product Data Operation................................................. 132

2.10.2 Accessing Vital Product Data.................................................................. 133

2.10.2.1 Reading Vital Product Data....................................................... 133

2.10.2.2 Writing Vital Product Data ........................................................ 134

2.11 Central Resource Functionality .......................................................................... 135

2.11.1 Multi-Function Support.......................................................................... 135

2.11.2 Inbound Transactions ........................................................................... 135

2.11.3 Outbound Transactions ......................................................................... 135

2.11.4 PCI Reset (

P_RSTOUT#

)...................................................................... 135

2.11.5 PCI Clock Outputs (

P_CLKOUT

P_CLKO[3:0]

) ...................................... 135

2.11.6 External Clock Driver (

CR_FREQ[1:0]

) .................................................. 136

2.11.7 Bus Mode and Frequency Initialization..................................................... 137

2.12 Embedded Bridge Functionality ......................................................................... 141

2.13 Register Definitions ......................................................................................... 144

2.13.1 PCI Configuration Registers ................................................................... 144

2.13.2 Internal Bus Registers........................................................................... 148

2.13.3 ATU Vendor ID Register - ATUVID .......................................................... 152

2.13.4 ATU Device ID Register - ATUDID........................................................... 152

2.13.5 ATU Command Register - ATUCMD ......................................................... 153

2.13.6 ATU Status Register - ATUSR................................................................. 154

2.13.7 ATU Revision ID Register - ATURID......................................................... 156

2.13.8 ATU Class Code Register - ATUCCR......................................................... 156

2.13.9 ATU Cacheline Size Register - ATUCLSR................................................... 157

Intel

81341 and 81342—Contents

Intel

81341 and 81342 I/O Processors

Developer’s Manual December 2007

6Order Number: 315037-002US

2.13.10ATU Latency Timer Register - ATULT .......................................................157

2.13.11ATU Header Type Register - ATUHTR .......................................................158

2.13.12ATU BIST Register - ATUBISTR...............................................................159

2.13.13Inbound ATU Base Address Register 0 - IABAR0........................................160

2.13.14Inbound ATU Upper Base Address Register 0 - IAUBAR0 ............................161

2.13.15Inbound ATU Base Address Register 1 - IABAR1........................................162

2.13.16Inbound ATU Upper Base Address Register 1 - IAUBAR1 ............................163

2.13.17Inbound ATU Base Address Register 2 - IABAR2........................................164

2.13.18Inbound ATU Upper Base Address Register 2 - IAUBAR2 ............................165

2.13.19ATU Subsystem Vendor ID Register - ASVIR.............................................166

2.13.20ATU Subsystem ID Register - ASIR .........................................................166

2.13.21Expansion ROM Base Address Register - ERBAR........................................167

2.13.22ATU Capabilities Pointer Register - ATU_Cap_Ptr .......................................168

2.13.23Determining Block Sizes for Base Address Registers ..................................169

2.13.24ATU Interrupt Line Register - ATUILR ......................................................171

2.13.25ATU Interrupt Pin Register - ATUIPR........................................................172

2.13.26ATU Minimum Grant Register - ATUMGNT.................................................172

2.13.27ATU Maximum Latency Register - ATUMLAT..............................................173

2.13.28Inbound ATU Limit Register 0 - IALR0......................................................174

2.13.29Inbound ATU Translate Value Register 0 - IATVR0..................................... 175

2.13.30Inbound ATU Upper Translate Value Register 0 - IAUTVR0..........................175

2.13.31Inbound ATU Limit Register 1 - IALR1......................................................176

2.13.32Inbound ATU Translate Value Register 1 - IATVR1..................................... 177

2.13.33Inbound ATU Upper Translate Value Register 1 - IAUTVR1..........................177

2.13.34Inbound ATU Limit Register 2 - IALR2......................................................178

2.13.35Inbound ATU Translate Value Register 2 - IATVR2..................................... 179

2.13.36Inbound ATU Upper Translate Value Register 2 - IAUTVR2..........................179

2.13.37Expansion ROM Limit Register - ERLR......................................................180

2.13.38Expansion ROM Translate Value Register - ERTVR .....................................181

2.13.39Expansion ROM Upper Translate Value Register - ERUTVR ..........................181

2.13.40ATU Configuration Register - ATUCR........................................................182

2.13.41PCI Configuration and Status Register - PCSR...........................................183

2.13.42ATU Interrupt Status Register - ATUISR...................................................186

2.13.43ATU Interrupt Mask Register - ATUIMR ....................................................188

2.13.44VPD Capability Identifier Register - VPD_Cap_ID....................................... 190

2.13.45VPD Next Item Pointer Register - VPD_Next_Item_Ptr ...............................190

2.13.46VPD Address Register - VPDAR ...............................................................191

2.13.47 VPD Data Register - VPDDR................................................................... 191

2.13.48PM Capability Identifier Register - PM_Cap_ID ..........................................192

2.13.49PM Next Item Pointer Register - PM_Next_Item_Ptr...................................192

2.13.50ATU Power Management Capabilities Register - APMCR .............................. 193

2.13.51ATU Power Management Control/Status Register - APMCSR........................ 194

2.13.52ATU Scratch Pad Register - ATUSPR ........................................................195

2.13.53PCI-X Capability Identifier Register - PCI-X_Cap_ID .................................. 195

2.13.54PCI-X Next Item Pointer Register - PCI-X_Next_Item_Ptr...........................196

2.13.55PCI-X Command Register - PCIXCMD ......................................................196

2.13.56PCI-X Status Register - PCIXSR ..............................................................198

2.13.57ECC Control and Status Register - ECCCSR............................................... 200

2.13.58ECC First Address Register - ECCFAR....................................................... 203

2.13.59ECC Second Address Register - ECCSAR ..................................................204

2.13.60ECC Attribute Register - ECCAR ..............................................................205

2.13.61CompactPCI Hot-Swap Capability ID Register ...........................................205

2.13.62Offset EDh: HS_NXTP - Next Item Pointer................................................206

2.13.63HS_CNTRL - Hot-Swap Control/Status Register.........................................207

2.13.64Inbound ATU Base Address Register 3 - IABAR3........................................209

Intel

81341 and 81342 I/O Processors

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Contents—Intel

81341 and 81342

2.13.65Inbound ATU Upper Base Address Register 3 - IAUBAR3............................ 210

2.13.66Inbound ATU Limit Register 3 - IALR3 ..................................................... 211

2.13.67Inbound ATU Translate Value Register 3 - IATVR3 .................................... 212

2.13.68Inbound ATU Upper Translate Value Register 3 - IAUTVR3 ......................... 212

2.13.69Outbound I/O Base Address Register - OIOBAR ........................................ 213

2.13.70Outbound I/O Window Translate Value Register - OIOWTVR....................... 214

2.13.71Outbound Upper Memory Window Base Address Register 0 - OUMBAR0 ....... 215

2.13.72Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0

216

2.13.73Outbound Upper Memory Window Base Address Register 1 - OUMBAR1 ....... 217

2.13.74Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1

218

2.13.75Outbound Upper Memory Window Base Address Register 2 - OUMBAR2 ....... 219

2.13.76Outbound Upper 32-bit Memory Window Translate Value Register 2 - OUMWTVR2

220

2.13.77Outbound Upper Memory Window Base Address Register 3 - OUMBAR3 ....... 221

2.13.78Outbound Upper 32-bit Memory Window Translate Value Register 3 - OUMWTVR3

222

2.13.79Outbound Configuration Cycle Address Register - OCCAR........................... 223

2.13.80Outbound Configuration Cycle Data Register - OCCDR............................... 224

2.13.81Outbound Configuration Cycle Function Number - OCCFN .......................... 224

2.13.82PCI Interface Error Control and Status Register - PIECSR........................... 225

2.13.83PCI Interface Error Address Register - PCIEAR.......................................... 226

2.13.84PCI Interface Error Upper Address Register - PCIEUAR .............................. 227

2.13.85PCI Interface Error Context Address Register — PCIECAR .......................... 228

2.13.86Internal Arbiter Control Register - IACR................................................... 229

2.13.87Multi-Transaction Timer - MTT................................................................ 230

2.13.88PCIX RCOMP Control Register — PRCR .................................................... 231

2.13.89PCIX Pad ODT Drive Strength Manual Override Values Registers — PPODSMOVR

232

2.13.90PCIX PAD DRIVE STRENGTH Manual Override Values ........ Register(3.3 V/1.5 V

Switch Supply Voltage) — PPDSMOVR3.3_1.5233

2.13.91PCIX PAD DRIVE STRENGTH Manual Override Values Register (3.3 V Dedicated

Supply Voltage) — PPDSMOVR3.3234

3.0 Address Translation Unit (PCI Express)........................................................................ 235

3.1 Overview ....................................................................................................... 235

3.2 PCI Express Link Characteristics ........................................................................ 238

3.3 ATU Address Translation .................................................................................. 239

3.3.1 Inbound Transactions ........................................................................... 242

3.3.1.1 Inbound Address Translation .................................................... 242

3.3.1.2 Inbound Memory Write Transaction ........................................... 245

3.3.1.3 Inbound Memory Read Transaction ........................................... 246

3.3.1.4 Inbound I/O Cycle Translation .................................................. 247

3.3.1.5 Inbound Configuration Cycle Translation (ID Routed)................... 247

3.3.1.6 Inbound Vendor_Defined Message Transactions .......................... 248

3.3.2 Outbound Transactions ......................................................................... 249

3.3.2.1 Outbound Address Translation - Internal Bus Transactions............ 250

3.3.2.2 Outbound Address Translation Windows..................................... 251

3.3.2.3 Outbound DMA Transactions..................................................... 254

3.3.2.4 Outbound Function Number...................................................... 254

3.3.3 Outbound Write Transaction .................................................................. 255

3.3.4 Outbound Read Transaction................................................................... 256

3.3.5 Outbound Configuration Cycle Translation................................................ 257

3.3.5.1 Outbound Configuration Cycle Error Conditions ........................... 257

3.3.5.2 Outbound Configuration Completions with Retry Status (CRS)....... 257

3.3.5.3 Outbound PCI Express Message Transactions.............................. 258

Intel

81341 and 81342—Contents

Intel

81341 and 81342 I/O Processors

Developer’s Manual December 2007

8Order Number: 315037-002US

3.3.5.4 Completion Timeout Mechanism ................................................258

3.4 Big Endian Byte Swapping.................................................................................259

3.4.1 Inbound Byte Swapping.........................................................................259

3.4.2 Outbound Byte Swapping.......................................................................260

3.5 Messaging Unit................................................................................................261

3.6 PCI Express Messages ......................................................................................262

3.7 Expansion ROM Translation Unit.........................................................................264

3.8 ATU Queue Architecture....................................................................................265

3.8.1 Inbound Queues ...................................................................................265

3.8.1.1 Inbound Posted Queue Structure...............................................265

3.8.1.2 Inbound Non Posted Queue Structure ........................................266

3.8.1.3 Inbound Completion Queue Structure ........................................266

3.8.1.4 Inbound Transaction Queues Command Translation Summary .......266

3.8.2 Outbound Queues.................................................................................267

3.8.2.1 Relaxed Ordering and No Snoop Outbound Request Attributes.......267

3.8.3 Transaction Ordering.............................................................................268

3.8.3.1 Transaction Ordering Summary.................................................271

3.8.4 Byte Parity Checking and Generation.......................................................272

3.8.4.1 Parity Generation ....................................................................272

3.8.4.2 Parity Checking.......................................................................273

3.8.4.3 Parity Disabled........................................................................273

3.9 ATU Error Conditions........................................................................................274

3.9.1 PCI Express Errors ................................................................................275

3.9.1.1 Role Based Error Reporting.......................................................275

3.9.1.2 Malformed Packets ..................................................................276

3.9.1.3 ECRC Check Failed ..................................................................276

3.9.1.4 Unsupported Request...............................................................277

3.9.1.5 Completer Abort......................................................................277

3.9.1.6 Unexpected Completions ..........................................................277

3.9.1.7 Poisoned TLP Received.............................................................278

3.9.1.8 Completion Timeout ................................................................278

3.9.2 Parity Error on the Internal Bus ..............................................................279

3.9.3 ATU Error Summary..............................................................................279

3.10 PCI Express Hot-Plug Support ...........................................................................283

3.11 Reset.............................................................................................................284

3.12 Message-Signaled Interrupts.............................................................................285

3.12.1 Legacy Interrupts .................................................................................285

3.12.2 Internal Interrupts................................................................................285

3.13 Vital Product Data............................................................................................286

3.13.1 Configuring Vital Product Data Operation .................................................286

3.13.2 Accessing Vital Product Data ..................................................................287

3.13.2.1 Reading Vital Product Data .......................................................287

3.13.2.2 Writing Vital Product Data ........................................................288

3.14 Root Complex Functionality...............................................................................289

3.15 Embedded Bridge Functionality..........................................................................290

3.16 Register Definitions..........................................................................................293

3.16.1 Extended Capabilities Registers ..............................................................294

3.16.2 Internal Bus Addresses..........................................................................297

3.16.3 ATU Vendor ID Register - ATUVID...........................................................301

3.16.4 ATU Device ID Register - ATUDID ...........................................................301

3.16.5 ATU Command Register - ATUCMD..........................................................302

3.16.6 ATU Status Register - ATUSR .................................................................303

3.16.7 ATU Revision ID Register - ATURID .........................................................304

3.16.8 ATU Class Code Register - ATUCCR .........................................................304

3.16.9 ATU Cacheline Size Register - ATUCLSR................................................... 305

3.16.10ATU Latency Timer Register - ATULT .......................................................305

Intel

81341 and 81342 I/O Processors

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Order Number: 315037-002US 9

Contents—Intel

81341 and 81342

3.16.11ATU Header Type Register - ATUHTR....................................................... 306

3.16.12ATU BIST Register - ATUBISTR............................................................... 307

3.16.13Inbound ATU Base Address Register 0 - IABAR0 ....................................... 308

3.16.14Inbound ATU Upper Base Address Register 0 - IAUBAR0............................ 309

3.16.15Determining Block Sizes for Base Address Registers.................................. 310

3.16.16Inbound ATU Base Address Register 1 - IABAR1 ....................................... 312

3.16.17Inbound ATU Upper Base Address Register 1 - IAUBAR1............................ 313

3.16.18Inbound ATU Base Address Register 2 - IABAR2 ....................................... 314

3.16.19Inbound ATU Upper Base Address Register 2 - IAUBAR2............................ 315

3.16.20ATU Subsystem Vendor ID Register - ASVIR ............................................ 316

3.16.21ATU Subsystem ID Register - ASIR......................................................... 316

3.16.22Expansion ROM Base Address Register - ERBAR........................................ 317

3.16.23ATU Capabilities Pointer Register - ATU_Cap_Ptr....................................... 318

3.16.24ATU Interrupt Line Register - ATUILR...................................................... 319

3.16.25ATU Interrupt Pin Register - ATUIPR ....................................................... 320

3.16.26ATU Minimum Grant Register - ATUMGNT ................................................ 320

3.16.27ATU Maximum Latency Register - ATUMLAT ............................................. 321

3.16.28Inbound ATU Limit Register 0 - IALR0 ..................................................... 322

3.16.29Inbound ATU Translate Value Register 0 - IATVR0 .................................... 323

3.16.30Inbound ATU Upper Translate Value Register 0 - IAUTVR0 ......................... 323

3.16.31Inbound ATU Limit Register 1 - IALR1 ..................................................... 324

3.16.32Inbound ATU Translate Value Register 1 - IATVR1 .................................... 325

3.16.33Inbound ATU Upper Translate Value Register 1 - IAUTVR1 ......................... 325

3.16.34Inbound ATU Limit Register 2 - IALR2 ..................................................... 326

3.16.35Inbound ATU Translate Value Register 2 - IATVR2 .................................... 327

3.16.36Inbound ATU Upper Translate Value Register 2 - IAUTVR2 ......................... 328

3.16.37Expansion ROM Limit Register - ERLR...................................................... 328

3.16.38Expansion ROM Translate Value Register - ERTVR..................................... 329

3.16.39Expansion ROM Upper Translate Value Register - ERUTVR.......................... 329

3.16.40ATU Configuration Register - ATUCR ....................................................... 330

3.16.41PCI Configuration and Status Register - PCSR .......................................... 331

3.16.42ATU Interrupt Status Register - ATUISR .................................................. 333

3.16.43ATU Interrupt Mask Register - ATUIMR.................................................... 336

3.16.44PCI Express Message Control/Status Register - PEMCSR ............................ 337

3.16.45PCI Express Link Control/Status Register - PELCSR ................................... 338

3.16.46VPD Capability Identifier Register - VPD_Cap_ID ...................................... 339

3.16.47VPD Next Item Pointer Register - VPD_Next_Item_Ptr............................... 339

3.16.48VPD Address Register - VPDAR............................................................... 340

3.16.49VPD Data Register - VPDDR ................................................................... 340

3.16.50PM Capability Identifier Register - PM_Cap_ID.......................................... 341

3.16.51PM Next Item Pointer Register - PM_Next_Item_Ptr .................................. 341

3.16.52ATU Power Management Capabilities Register - APMCR.............................. 342

3.16.53ATU Power Management Control/Status Register - APMCSR ....................... 343

3.16.54ATU Scratch Pad Register - ATUSPR........................................................ 344

3.16.55PCI Express Capability List Register - PCIE_CAPID .................................... 344

3.16.56PCI Express Next Item Pointer Register - PCIE_NXTP ................................ 345

3.16.57PCI Express Capabilities Register - PCIE_CAP ........................................... 346

3.16.58PCI Express Device Capabilities Register - PCIE_DCAP............................... 347

3.16.59PCI Express Device Control Register - PE_DCTL........................................ 348

3.16.60PCI Express Device Status Register - PE_DSTS......................................... 350

3.16.61PCI Express Link Capabilities Register - PE_LCAP...................................... 351

3.16.62PCI Express Link Control Register - PE_LCTL ............................................ 352

3.16.63PCI Express Link Status Register - PE_LSTS............................................. 353

3.16.64PCI Express Slot Capabilities Register - PE_SCAP...................................... 354

3.16.65PCI Express Slot Control Register - PE_SCR ............................................. 355

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81341 and 81342—Contents

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81341 and 81342 I/O Processors

Developer’s Manual December 2007

10 Order Number: 315037-002US

3.16.66PCI Express Slot Status Register - PE_SSTS .............................................356

3.16.67PCI Express Root Control Register - PE_RCR.............................................357

3.16.68PCI Express Root Status Register - PE_RSR.............................................. 358

3.16.69PCI Express Advanced Error Capability Identifier - ADVERR_CAPID.............. 359

3.16.70PCI Express Uncorrectable Error Status - ERRUNC_STS..............................360

3.16.71PCI Express Uncorrectable Error Mask - ERRUNC_MSK...............................361

3.16.72PCI Express Uncorrectable Error Severity - ERRUNC_SEV ........................... 362

3.16.73PCI Express Correctable Error Status - ERRCOR_STS................................. 363

3.16.74PCI Express Correctable Error Mask - ERRCOR_MSK ..................................364

3.16.75Advanced Error Control and Capability Register - ADVERR_CTL ...................365

3.16.76PCI Express Advanced Error Header Log - ADVERR_LOG0 ..........................365

3.16.77PCI Express Advanced Error Header Log - ADVERR_LOG1 ..........................366

3.16.78PCI Express Advanced Error Header Log - ADVERR_LOG2 ..........................366

3.16.79PCI Express Advanced Error Header Log - ADVERR_LOG3 ..........................367

3.16.80Root Error Command Register - RERR_CMD .............................................367

3.16.81Root Error Status Register .....................................................................368

3.16.82Error Source Identification Register - RERR_ID .........................................369

3.16.83Device Serial Number Capability - DSN_CAP.............................................369

3.16.84Device Serial Number Lower DW Register - DSN_LDW ...............................370

3.16.85Device Serial Number Upper DW Register - DSN_UDW...............................370

3.16.86PCI Express Advisory Error Control Register - PIE_AEC .............................. 371

3.16.87Power Budgeting Enhanced Capability Header - PWRBGT_CAPID ................. 372

3.16.88Power Budgeting Data Select Register - PWRBGT_DSEL .............................372

3.16.89Power Budgeting Data Register - PWRBGT_DATA ......................................373

3.16.90Power Budgeting Capability Register - PWRBGT_CAP ................................. 374

3.16.91Power Budgeting Information Registers[0:23]—PWRBGT_INFO[0:23] ..........375

3.16.92Outbound I/O Base Address Register - OIOBAR......................................... 376

3.16.93Outbound I/O Window Translate Value Register - OIOWTVR .......................377

3.16.94Outbound Upper Memory Window Base Address Register 0 - OUMBAR0........ 378

3.16.95Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0

379

3.16.96Outbound Upper Memory Window Base Address Register 1 - OUMBAR1........ 380

3.16.97Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1

381

3.16.98Outbound Upper Memory Window Base Address Register 2 - OUMBAR2........ 382

3.16.99Outbound Upper 32-bit Memory Window Translate Value Register 2 - OUMWTVR2

383

3.16.100Outbound Upper Memory Window Base Address Register 3 - OUMBAR3 ......384

3.16.101Outbound Upper 32-bit Memory Window Translate Value Register 3 -

OUMWTVR3385

3.16.102Outbound Configuration Cycle Address Register - OCCAR..........................386

3.16.103Outbound Configuration Cycle Data Register - OCCDR..............................387

3.16.104Outbound Configuration Cycle Function Number - OCCFN .........................388

3.16.105Inbound Vendor Message Header Register 0 - IVMHR0 .............................389

3.16.106Inbound Vendor Message Header Register 1 - IVMHR1 .............................390

3.16.107Inbound Vendor Message Header Register 2 - IVMHR2 .............................391

3.16.108Inbound Vendor Message Header Register 3 - IVMHR3 .............................392

3.16.109Inbound Vendor Message Payload Register - IVMPR .................................392

3.16.110Outbound Vendor Message Header Register 0 - OVMHR0 ..........................393

3.16.111Outbound Vendor Message Header Register 1 - OVMHR1 ..........................394

3.16.112Outbound Vendor Message Header Register 2 - OVMHR2 ..........................395

3.16.113Outbound Vendor Message Header Register 3 - OVMHR3 ..........................395

3.16.114Outbound Vendor Message Payload Register - OVMPR ..............................396

3.16.115PCI Interface Error Control and Status Register - PIE_CSR........................ 397

3.16.116PCI Interface Error Status - PIE_STS .....................................................398

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Order Number: 315037-002US 11

Contents—Intel

81341 and 81342

3.16.117PCI Interface Error Mask - PIE_MSK ...................................................... 399

3.16.118PCI Interface Error Header Log - PIE_LOG0 ............................................ 400

3.16.119PCI Interface Error Header Log 1 - PIE_LOG1 ......................................... 400

3.16.120PCI Interface Error Header Log 2 - PIE_LOG2 ......................................... 401

3.16.121PCI Interface Error Header Log - PIE_LOG3 ............................................ 401

3.16.122PCI Interface Error Descriptor Log......................................................... 402

3.16.123ATU Reset Control Register - ATURCR.................................................... 402

4.0 Messaging Unit......................................................................................................... 403

4.1 Overview ....................................................................................................... 403

4.2 Theory of Operation......................................................................................... 404

4.2.1 Transaction Ordering ............................................................................ 407

4.3 Message Registers........................................................................................... 408

4.3.1 Outbound Messages.............................................................................. 408

4.3.2 Inbound Messages................................................................................ 408

4.4 Doorbell Registers ........................................................................................... 409

4.4.1 Outbound Doorbells.............................................................................. 409

4.4.2 Inbound Doorbells................................................................................ 409

4.5 Circular Queues .............................................................................................. 410

4.5.1 Inbound Free Queue ............................................................................. 414

4.5.2 Inbound Post Queue ............................................................................. 415

4.5.3 Outbound Post Queue ........................................................................... 416

4.5.4 Outbound Free Queue........................................................................... 417

4.6 Index Registers............................................................................................... 419

4.7 Messaging Unit Error Conditions ........................................................................ 420

4.8 Message-Signaled Interrupts............................................................................. 421

4.8.1 MSI Capability Structure ....................................................................... 421

4.8.2 MSI-X Capability and Table Structures .................................................... 422

4.8.3 Level-Triggered Versus Edge-Triggered Interrupts .................................... 424

4.9 Register Definitions ......................................................................................... 425

4.9.1 Inbound Message Register - IMRx........................................................... 427

4.9.2 Outbound Message Register - OMRx ....................................................... 427

4.9.3 Inbound Doorbell Register - IDR............................................................. 428

4.9.4 Inbound Interrupt Status Register - IISR ................................................. 429

4.9.5 Inbound Interrupt Mask Register - IIMR .................................................. 430

4.9.6 Outbound Doorbell Register - ODR.......................................................... 431

4.9.7 Outbound Interrupt Status Register - OISR.............................................. 432

4.9.8 Outbound Interrupt Mask Register - OIMR ............................................... 433

4.9.9 Inbound Reset Control and Status Register - IRCSR .................................. 434

4.9.10 Outbound Reset Control and Status Register - ORCSR ............................... 435

4.9.11 MSI Inbound Message Register — MIMR .................................................. 436

4.9.12 MU Configuration Register - MUCR.......................................................... 437

4.9.13 Queue Base Address Register - QBAR...................................................... 438

4.9.14 Inbound Free Head Pointer Register - IFHPR ............................................ 439

4.9.15 Inbound Free Tail Pointer Register - IFTPR............................................... 439

4.9.16 Inbound Post Head Pointer Register - IPHPR ............................................ 440

4.9.17 Inbound Post Tail Pointer Register - IPTPR ............................................... 440

4.9.18 Outbound Free Head Pointer Register - OFHPR ......................................... 441

4.9.19 Outbound Free Tail Pointer Register - OFTPR............................................ 441

4.9.20 Outbound Post Head Pointer Register - OPHPR ......................................... 442

4.9.21 Outbound Post Tail Pointer Register - OPTPR............................................ 442

4.9.22 Index Address Register - IAR ................................................................. 443

4.9.23 MU Base Address Register - MUBAR ........................................................ 444

4.9.24 MU Upper Base Address Register - MUUBAR............................................. 445

4.9.25 MU MSI-X Table Message Address Registers - M_MT_MAR[0:7] .................. 446

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81341 and 81342 I/O Processors

Developer’s Manual December 2007

12 Order Number: 315037-002US

4.9.26 MU MSI-X Table Message Upper Address Registers - M_MT_MUAR[0:7]........ 447

4.9.27 MU MSI-X Table Message Data Registers - M_MT_MDR[0:7] .......................448

4.9.28 MU MSI-X Table Message Vector Control Registers - M_MT_MVCR[0:7]........ 449

4.9.29 MU MSI-X Pending Bits Array Register - M_MPBAR ....................................450

4.9.30 MSI Capability Identifier Register - Cap_ID ..............................................450

4.9.31 MSI Next Item Pointer Register - MSI_Next_Ptr ........................................451

4.9.32 Message Control Register - Message_Control............................................452

4.9.33 Message Address Register - Message_Address ..........................................453

4.9.34 Message Upper Address Register - Message_Upper_Address.......................454

4.9.35 Message Data Register- Message_Data ....................................................455

4.9.36 MSI-X Capability Identifier Register - MSI-X_Cap_ID ................................. 456

4.9.37 MSI-X Next Item Pointer Register - MSI-X_Next_Item_Ptr..........................457

4.9.38 MSI-X Message Control Register - MSI-X_MCR..........................................458

4.9.39 MSI-X Table Offset Register — MSI-X_Table_Offset ................................... 459

4.9.40 MSI-X Pending Bit Array Offset Register - MSI-X_PBA_Offset...................... 460

4.9.41 MU MSI-X Control Register X — MMCRx ...................................................461

4.9.42 Inbound MSI Interrupt Pending Register x — IMIPRx .................................462

4.10 Power/Default Status .......................................................................................462

5.0 Application DMA Unit.................................................................................................463

5.1 Overview........................................................................................................463

5.2 Theory of Operation .........................................................................................464

5.3 ADMA Descriptors............................................................................................466

5.3.1 Basic Chain Descriptor Format................................................................467

5.3.2 Full Chain Descriptor Format ..................................................................469

5.3.3 P+Q Chain Descriptor Format.................................................................472

5.3.4 Dual XOR Descriptor Format...................................................................476

5.3.5 P+Q Update Descriptor Format...............................................................478

5.4 ADMA Descriptor Processing..............................................................................480

5.4.1 Scatter Gather Transfers........................................................................482

5.4.2 Synchronizing a Program to Chained Operation.........................................482

5.4.3 Appending to the End of a Chain.............................................................484

5.5 Data Queues...................................................................................................485

5.5.1 Data Transfer Options ...........................................................................485

5.6 Data Alignment ...............................................................................................487

5.6.1 64-bit Unaligned Data Transfers .............................................................487

5.6.2 64/32-bit Unaligned Data Transfers.........................................................488

5.7 ADMA Operations.............................................................................................489

5.7.1 Per Channel Support for ADMA Operations ...............................................490

5.7.2 XOR Operation .....................................................................................491

5.7.3 XOR Operation with P+Q RAID-6 ............................................................494

5.7.4 Dual XOR Operation..............................................................................497

5.7.5 P+Q Update Operation ..........................................................................500

5.7.6 Zero Result Buffer Check .......................................................................502

5.7.7 P+Q Zero Result Buffer Check ................................................................503

5.7.8 Memory Block Fill Operation...................................................................505

5.8 CRC Generation...............................................................................................506

5.8.1 CRC Mode Configuration and Operation....................................................506

5.8.1.1 Chaining of CRC Calculation Across Multiple Descriptors................507

5.8.2 CRC-32C Algorithm...............................................................................508

5.9 Programming Model State Diagram ....................................................................509

5.10 Application DMA Priority ...................................................................................510

5.11 Programming the Application DMA .....................................................................511

5.11.1 Application DMA Initialization .................................................................511

5.11.2 Start Transfer ......................................................................................511

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Contents—Intel

81341 and 81342

5.11.3 Suspend Application DMA ...................................................................... 512

5.12 Internal Interface Parity Checking and Generation ............................................... 513

5.12.1 Address and Data Parity Generation........................................................ 514

5.12.1.1 Address Parity Generation........................................................ 514

5.12.1.2 Data Parity Generation ............................................................ 515

5.12.2 Address and Data Parity Checking .......................................................... 516

5.12.2.1 Address Parity Checking .......................................................... 516

5.12.2.2 Data Parity Checking............................................................... 517

5.12.2.3 Parity Disabled ....................................................................... 517

5.12.2.4 Parity Testing......................................................................... 517

5.13 Interrupts ...................................................................................................... 518

5.14 Error Conditions.............................................................................................. 519

5.14.1 Fatal Errors ......................................................................................... 519

5.14.2 Non-Fatal Errors................................................................................... 519

5.15 Power-Up/Default Status .................................................................................. 519

5.16 Register Definitions ......................................................................................... 520

5.16.1 ADMA Channel Control Register x — ACCRx ............................................. 521

5.16.2 ADMA Channel Status Register x — ACSRx .............................................. 522

5.16.3 ADMA Descriptor Address Register x — ADARx ......................................... 524

5.16.4 Internal Interface Parity Control Register x — IIPCRx ................................ 524

5.16.5 ADMA Next Descriptor Address Register x — ANDARx................................ 525

5.16.6 ADMA Descriptor Control Register x — ADCRx .......................................... 526

5.16.7 CRC Address/Memory Block Fill Data/Q_Destination

5.16.8 ADMA Byte Count Register x — ABCRx .................................................... 530

5.16.9 Destination Lower Address / P_Destination Lower Address Register x — DLADRx

531

5.16.10Destination Upper Address / PQ_Destination Upper

Address Register x — DUADRx ............................................................... 532

5.16.11Source Lower Address Register 0…15_x — SLAR0…15_x............................ 533

5.16.12Source Upper Address Register 0…15_x — SUAR0…15_x ........................... 535

6.0 System Controller (SC) and Internal Bus Bridge............................................................ 537

6.1 Overview ....................................................................................................... 537

6.2 Theory of Operation......................................................................................... 538

6.2.1 System Controller ................................................................................ 538

6.2.2 Internal Bus Requester IDs.................................................................... 538

6.2.3 Parity Testing ...................................................................................... 539

6.3 Internal Bus Bridge.......................................................................................... 541

6.3.1 Theory of Operation.............................................................................. 542

6.3.2 Internal Bus Commands ........................................................................ 543

6.3.3 Transaction Queues .............................................................................. 543

6.3.4 Bridge Memory Window......................................................................... 544

6.3.5 Ordering and Passing Rules ................................................................... 545

6.3.5.1 Strong Ordering Rule Requirements .......................................... 545

6.3.6 Parity Support ..................................................................................... 546

6.3.6.1 Address Parity Generation........................................................ 546

6.3.6.2 Address Parity Checking .......................................................... 546

6.3.6.3 Data Parity on Outbound Transactions ....................................... 546

6.3.6.4 Data Parity on Inbound Transactions ......................................... 546

6.3.7 Error Detection and Handling ................................................................. 547

6.3.7.1 Bridge North Internal Bus Interface Error ................................... 547

6.3.7.2 Bridge South Internal Bus Interface Error................................... 548

6.4 System Controller Register Definitions................................................................ 549

6.5 Internal Bus Bridge Register Definitions.............................................................. 550

6.5.1 Internal Bus Arbitration Control Register — IBACR .................................... 551

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81341 and 81342—Contents

Intel

81341 and 81342 I/O Processors

Developer’s Manual December 2007

14 Order Number: 315037-002US

6.5.2 South Internal Bus Address Test Control Register — SIBATCR..................... 553

6.5.3 South Internal Bus Data Test Control Register — SIBDTCR......................... 554

6.5.4 Peripheral Memory-Mapped Register Base Address Register — PMMRBAR .....555

6.5.5 Determining Block Sizes for Memory Windows ..........................................556

6.5.6 Bridge Window Base Address Register — BWBAR ......................................557

6.5.7 Bridge Window Upper Base Address Register — BWUBAR...........................558

6.5.8 Bridge Window Limit Register — BWLR ....................................................559

6.5.9 Bridge Error Control and Status Register — BECSR....................................560

6.5.10 Bridge Error Address Register — BERAR...................................................562

6.5.11 Bridge Error Upper Address Register — BERUAR........................................ 562

7.0 DDR SDRAM Memory Controller ..................................................................................563

7.1 Overview........................................................................................................563

7.2 Glossary.........................................................................................................564

7.3 Theory of Operation .........................................................................................565

7.3.1 Functional Blocks..................................................................................565

7.3.1.1 Transaction Ports ....................................................................566

7.3.1.1.1 North Internal Bus Port......................................................566

7.3.1.1.2 South Internal Bus Port.....................................................566

7.3.1.1.3 Application DMA Ports......................................................566

7.3.1.1.4 Messaging Unit Port..........................................................566

7.3.1.2 Address Decode Blocks ............................................................567

7.3.1.2.1 DDR SDRAM Memory Array Space..................................567

7.3.1.2.2 Memory-Mapped Register Space .....................................567

7.3.1.2.3 North Internal Bus Port Address Decode..........................567

7.3.1.2.4 South Internal Bus Port Address Decode .........................567

7.3.1.2.5 Application DMA Port Address Decode ............................567

7.3.1.3 Memory Transaction Queues.....................................................568

7.3.1.3.1 North Internal Bus Port Transaction Queue (NIBPTQ) .....568

7.3.1.3.2 South Internal Bus Port Transaction Queue (SIBPTQ).....568

7.3.1.4 Configuration Registers ............................................................568

7.3.1.5 Refresh Counter......................................................................568

7.3.1.6 Memory Controller Arbiter (DMARB)...........................................568

7.3.1.7 DDR SDRAM Control Block........................................................569

7.3.1.7.1 Page Control Block ...........................................................569

7.3.1.7.2 DDR SDRAM State Machine and Pipeline Queues..........569

7.3.1.7.3 Error Correction Logic.......................................................569

7.3.2 DMCU Arbitration and Configuration ........................................................570

7.3.2.1 DMCU Port Priority...................................................................570

7.3.2.2 DMCU Port Transaction Count ...................................................570

7.3.2.3 North Internal Bus Port Preemption ...........................................571

7.3.2.4 North Internal Bus Port Transaction Ordering ..............................571

7.3.2.5 South Internal Bus Port Ordering...............................................571

7.3.2.6 Application DMAs Port Ordering.................................................571

7.3.2.7 DMCU Port Coherency..............................................................571

7.3.3 DDR SDRAM Memory Support.................................................................572

7.3.3.1 DDR SDRAM Interface..............................................................572

7.3.3.2 DDR SDRAM Addressing ...........................................................575

7.3.3.3 DDR SDRAM Bank Sizes and Configurations ................................578

7.3.3.4 32-bit Data Bus Width..............................................................588

7.3.3.5 Page Hit/Miss Determination.....................................................589

7.3.3.6 DDR SDRAM Commands...........................................................593

7.3.3.7 DDR SDRAM Initialization .........................................................594

7.3.3.8 DDR SDRAM Mode Programming ...............................................601

7.3.3.9 DDR SDRAM Read Cycle ........................................................... 603

7.3.3.10 DDR SDRAM Write Cycle ..........................................................604

7.3.3.11 DDR SDRAM Refresh Cycle .......................................................606

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Order Number: 315037-002US 15

Contents—Intel

81341 and 81342

7.3.4 DDR Error Correction and Detection........................................................ 607

7.3.4.1 DDR ECC Generation ............................................................... 608

7.3.4.2 DDR ECC Generation for Partial Writes....................................... 609

7.3.4.3 DDR ECC Checking.................................................................. 611

7.3.4.4 Scrubbing .............................................................................. 615

7.3.4.4.1 DDR ECC Example Using H-Matrix..................................615

7.3.4.5 DDR ECC Disabled .................................................................. 616

7.3.4.6 DDR ECC Testing .................................................................... 616

7.3.5 Memory Regions .................................................................................. 616

7.3.6 DDR SDRAM Clocking............................................................................ 616

7.4 Power Failure Mode ......................................................................................... 617

7.4.1 Theory of Operation.............................................................................. 617

7.4.2 Power Failure Sequence ........................................................................ 618

7.4.2.1 Power Failure Impact on the System ......................................... 618

7.4.2.2 System Assumptions ............................................................... 618

7.4.3 Memory Controller Response to

P_RST#

................................................. 619

7.5 ECC Interrupts/Error Conditions ........................................................................ 621

7.5.1 Single-Bit Error Detection...................................................................... 622

7.5.2 Multi-bit Error Detection ........................................................................ 623

7.6 Parity Interrupts/Error Conditions...................................................................... 624

7.7 Reset Conditions ............................................................................................. 624

7.8 Register Definitions ......................................................................................... 625

7.8.1 SDRAM Initialization Register — SDIR ..................................................... 627

7.8.2 SDRAM Control Register 0 — SDCR0 ....................................................... 628

7.8.3 SDRAM Control Register 1 — SDCR1 ....................................................... 630

7.8.4 SDRAM Base Register — SDBR............................................................... 632

7.8.5 SDRAM Upper Base Register — SDUBR.................................................... 633

7.8.6 Secondary SDRAM Base Register - SSDBR............................................... 634

7.8.7 SDRAM Bank Size Register — SBSR ........................................................ 635

7.8.8 SDRAM 32-bit Region Size Register — S32SR........................................... 637

7.8.9 DDR ECC Control Register — DECCR ....................................................... 638

7.8.10 DDR ECC Log Registers — DELOG0, DELOG1............................................ 639

7.8.11 DDR ECC Address Registers — DEAR0, DEAR1.......................................... 641

7.8.12 DDR ECC Context Address Registers — DECAR0, DECAR1 .......................... 642

7.8.13 DDR ECC Context Upper Address Registers — DECUAR0, DECUAR1............. 643

7.8.14 DDR ECC Test Register — DECTST .......................................................... 643

7.8.15 DDR Parity Control and Status Register — DPCSR..................................... 644

7.8.16 DDR Parity Address Register — DPAR...................................................... 645

7.8.17 DDR Parity Upper Address Register — DPUAR........................................... 645

7.8.18 DDR Parity Context Address Register — DPCAR ........................................ 646

7.8.19 DDR Parity Context Upper Address Register — DPCUAR ............................. 646

7.8.20 DDR Memory Controller Interrupt Status Register — DMCISR ..................... 647

7.8.21 DMCU Port Transaction Count Register — DMPTCR.................................... 648

7.8.22 DMCU Preemption Control Register — DMPCR .......................................... 650

7.8.23 Frequency Register — RFR..................................................................... 651

7.8.24 DDR RCOMP Control Register — DRCR .................................................... 652

7.8.25 RCOMP Pad Drive Strength Select Register — RPDSR ................................ 654

7.8.26 DQ Pad ODT Drive Strength Manual Override Values Register — DQPODSR .. 655

7.8.27 DQ Pad Drive Strength Manual Override Values Register — DQPDSR ........... 656

7.8.28 MA Pad Drive Strength Manual Override Values Register — MAPDSR ........... 657

7.8.29 MCLK Pad Drive Strength Manual Override Values Register — MPDSR.......... 658

7.8.30 CKE/CS Pad Drive Strength Manual Override Values Register — CKEPDSR.... 659

7.8.31 DLL Delay Register 0 — DLLR0............................................................... 660

7.8.32 DLL Delay Register 1 — DLLR1............................................................... 661

7.8.33 DLL Delay Register 2 — DLLR2............................................................... 662

Intel

81341 and 81342—Contents

Intel

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Developer’s Manual December 2007

16 Order Number: 315037-002US

7.8.34 DLL Delay Register 3 — DLLR3 ............................................................... 663

7.8.35 DLL Delay Register 4 — DLLR4 ............................................................... 664

7.8.36 DLL Delay for Receive Enable Register — DLLRCVER..................................665

7.8.36.1 Determining DLLRCVEREN Pulse Optimum Location...................... 668

7.8.36.1.1 DLLRCVREN Algorithm....................................................669

7.8.37 DDR RCOMP Status Register for 15 Ohm RCOMP — DRSR15.......................672

7.8.38 DDR RCOMP Status Register for 17.9 Ohm RCOMP — DRSR17 .................... 672

7.8.39 DDR RCOMP Status Register for 25 Ohm RCOMP — DRSR25.......................673

7.8.40 DDR RCOMP Status Register for 35 Ohm RCOMP — DRSR35.......................673

7.8.41 DDR RCOMP Status Register for 50 Ohm RCOMP — DRSR50.......................674

8.0 SRAM Memory Controller ...........................................................................................675

8.1 Overview........................................................................................................675

8.2 Glossary.........................................................................................................676

8.3 Theory of Operation .........................................................................................677

8.3.1 Functional Block ...................................................................................677

8.3.1.1 Transaction Ports ....................................................................677

8.3.1.1.1 North Internal Bus Ports....................................................677

8.3.1.2 Address Decode Blocks ............................................................678

8.3.1.2.1 SRAM Memory Array Space.............................................678

8.3.1.2.2 Memory-Mapped Register Space .....................................678

8.3.1.2.3 North Internal Bus Port Address Decode..........................678

8.3.1.3 Memory Transaction Queues.....................................................678

8.3.1.3.1 North Internal Bus Port Transaction Queue (NIBPTQ) .....678

8.3.1.4 Configuration Registers ............................................................678

8.3.1.5 SRAM Control Block .................................................................678

8.3.1.5.1 SRAM State Machine and Pipeline Queues .....................678

8.3.1.5.2 Error Correction Logic.......................................................679

8.3.1.6 North Internal Bus Port Transaction Ordering ..............................680

8.3.1.7 SMCU Port Coherency ..............................................................680

8.3.2 SRAM Memory Interface Support ............................................................681

8.3.2.1 SRAM Initialization ..................................................................681

8.3.2.2 SRAM Read Sequence ..............................................................681

8.3.2.3 SRAM Write Sequence..............................................................682

8.3.3 Error Correction and Detection ...............................................................683

8.3.3.1 ECC Generation.......................................................................684

8.3.3.2 ECC Generation for Partial Writes ..............................................685

8.3.3.3 ECC Checking .........................................................................686

8.3.3.4 Scrubbing ..............................................................................690

8.3.3.4.1 ECC Example Using the H-Matrix.....................................690

8.3.3.5 ECC Disabled ..........................................................................691

8.3.3.6 ECC Testing............................................................................691

8.3.4 Byte Parity Checking and Generation.......................................................692

8.3.4.1 Parity Generation ....................................................................693

8.3.4.2 Parity Checking.......................................................................694

8.3.4.3 Parity Disabled........................................................................694

8.3.4.4 Parity Testing .........................................................................694

8.4 ECC Interrupts/Error Conditions......................................................................... 695

8.4.1 Single-Bit Error Detection ......................................................................696

8.4.2 Multi-bit Error Detection ........................................................................697

8.5 Parity Interrupts/Error Conditions ......................................................................698

8.6 Register Definitions..........................................................................................699

8.6.1 SRAM Base Address Register — SRAMBAR................................................700

8.6.2 SRAM Upper Base Address Register — SRAMUBAR ....................................700

8.6.3 SRAM ECC Control Register — SECR........................................................701

8.6.4 SRAM ECC Log Register — SELOGR .........................................................702

8.6.5 SRAM ECC Address Register — SEAR.......................................................704

Intel

81341 and 81342 I/O Processors

December 2007 Developer’s Manual

Order Number: 315037-002US 17

Contents—Intel

81341 and 81342

8.6.6 SRAM ECC Context Address Register — SECAR......................................... 704

8.6.7 SRAM ECC Test Register — SECTST ........................................................ 705

8.6.8 SRAM Parity Control and Status Register — SPARCSR................................ 706

8.6.9 SRAM Parity Address Register — SPAR .................................................... 707

8.6.10 SRAM Parity Upper Address Register — SPUAR ......................................... 707

8.6.11 SRAM Memory Controller Interrupt Status Register — SMCISR ................... 708

9.0 Peripheral Bus Interface Unit...................................................................................... 709

9.1 Overview ....................................................................................................... 710

9.2 Peripheral Bus Signals...................................................................................... 711

9.2.1 Address Signal Definitions ..................................................................... 711

9.2.2 Data Signal Definitions.......................................................................... 711

9.2.3 Control/Status Signal Definitions ............................................................ 711

9.2.4 Bus Width ........................................................................................... 712

9.2.5 Detailed Signal Descriptions................................................................... 713

9.2.6 Flash Memory Support .......................................................................... 714

9.2.6.1 Flash Read Cycle .................................................................... 715

9.2.6.2 Flash Write Cycle .................................................................... 717

9.3 Register Definitions ......................................................................................... 718

9.3.1 PBI Control Register — PBCR ................................................................. 719

9.3.2 PBI Status Register — PBISR ................................................................. 719

9.3.3 Determining Block Sizes for Memory Windows.......................................... 720

9.3.4 PBI Base Address Register 0 — PBBAR0 .................................................. 721

9.3.5 PBI Limit Register 0 — PBLR0 ................................................................ 722

9.3.6 PBI Base Address Register 1 — PBBAR1 .................................................. 723

9.3.7 PBI Limit Register 1 — PBLR1 ................................................................ 724

9.3.8 PBI Drive Strength Control Register — PBDSCR ........................................ 725

9.3.9 Processor Frequency Register - PFR ........................................................ 726

9.3.10 External Strap Status Register 0 — ESSTSR0 ........................................... 727

9.3.11 Unique ID Register 0 — UID0................................................................. 728

9.3.12 Unique ID Register 1 — UID1................................................................. 728

10.0 Exception Initiator and Boot Sequence ........................................................................ 729

10.1 Overview ....................................................................................................... 729

10.2 Theory of Operation......................................................................................... 730

10.2.1 Core Identity ....................................................................................... 731

10.2.2 Targeted Reset .................................................................................... 731

10.2.3 Inter-Processor Interrupt Generation ...................................................... 731

10.3 Intel XScale

Processor Boot Sequence.............................................................. 732

10.3.1 Theory of Operation.............................................................................. 732

10.3.2 81341 and 81342 Boot Sequence ........................................................... 733

10.3.2.1 Boot Sequence — coreID0 and coreID1 simultaneous start running from

Flash Memory733

10.3.2.2 Boot Sequence — Both coreID0 and coreID1 run from SRAM Memory

(no Flash Memory)733

10.3.2.3 Boot Sequence — coreID0 runs from Flash Memory and coreID1 runs

from SRAM Memory734

10.4 Register Definitions ......................................................................................... 735

10.4.1 Core Identification Register — CIDR........................................................ 735

10.4.2 Reset Cause Status Register — RCSR...................................................... 736

10.4.3 Software Interrupt Generation Register — SINTGENR................................ 737

10.4.4 Targeted Reset Register — TARRSTR ...................................................... 738

11.0 Interrupt Controller Unit............................................................................................ 739

11.1 Overview ....................................................................................................... 739

11.2 Theory of Operation......................................................................................... 740

11.2.1 Interrupt Controller Unit........................................................................ 740

Intel

81341 and 81342—Contents

Intel

81341 and 81342 I/O Processors

Developer’s Manual December 2007

18 Order Number: 315037-002US

11.3 The Intel XScale

Processor Exceptions Architecture ............................................741

11.3.1 CPSR and SPSR....................................................................................741

11.3.2 The Exception Process...........................................................................742

11.3.3 Exception Priorities and Vectors..............................................................742

11.3.4 Software Requirements For Exception Handling.........................................743

11.3.4.1 Nesting FIQ and IRQ Exceptions ................................................743

11.4 Intel

81341 and 81342 I/O Processors External Interrupt Interface ......................744

11.4.1 Interrupt Inputs ...................................................................................744

11.4.2 Outbound Interrupts .............................................................................746

11.5 The Intel

81341 and 81342 I/O Processors Interrupt Controller Unit..................... 747

11.5.1 Programmer Model................................................................................748

11.5.1.1 Active Interrupt Source Control and Status .................................748

11.5.1.2 Prioritization and Vector Generation for Active Interrupt Sources ... 748

11.5.2 Operational Blocks ................................................................................750

11.5.3 Intel

81341 and 81342 I/O Processors: Internal Peripheral Interrupt ......... 751

11.5.3.1 Normal Interrupt Sources.........................................................752

11.5.3.2 Error Interrupt Sources ............................................................753

11.5.4 High-Priority Interrupt (

HPI#

) ...............................................................754

11.5.5 Timer Interrupts...................................................................................754

11.5.6 Inter-Processor Interrupts......................................................................754

11.5.7 Intel XScale

processor Interrupts..........................................................754

11.5.8 Software Interrupts...............................................................................754

11.6 Default Status.................................................................................................755

11.7 Interrupt Control Unit Registers .........................................................................756

11.7.1 Interrupt Base Register — INTBASE ........................................................758

11.7.2 Interrupt Size Register — INTSIZE ..........................................................759

11.7.3 IRQ Interrupt Vector Register — IINTVEC.................................................760

11.7.4 FIQ Interrupt Vector Register — FINTVEC.................................................761

11.7.5 Inter-Processor Interrupt Pending Register — IPIPNDR ..............................762

11.7.6 Interrupt Pending Register 0 — INTPND0 .................................................763

11.7.7 Interrupt Pending Register 1 — INTPND1 .................................................764

11.7.8 Interrupt Pending Register 2 — INTPND2 .................................................765

11.7.9 Interrupt Pending Register 3 — INTPND3 .................................................766

11.7.10Interrupt Control Register 0 — INTCTL0................................................... 767

11.7.11Interrupt Control Register 1 — INTCTL1................................................... 770

11.7.12Interrupt Control Register 2 — INTCTL2................................................... 772

11.7.13Interrupt Control Register 3 — INTCTL3................................................... 773

11.7.14Interrupt Steering Register 0 — INTSTR0................................................. 775

11.7.15Interrupt Steering Register 1 — INTSTR1................................................. 778

11.7.16Interrupt Steering Register 2 — INTSTR2................................................. 780

11.7.17Interrupt Steering Register 3 — INTSTR3................................................. 781

11.7.18IRQ Interrupt Source Register 0 — IINTSRC0 ...........................................783

11.7.19IRQ Interrupt Source Register 1 — IINTSRC1 ...........................................786

11.7.20IRQ Interrupt Source Register 2 — IINTSRC2 ...........................................788

11.7.21IRQ Interrupt Source Register 3 — IINTSRC3 ...........................................789

11.7.22FIQ Interrupt Source Register 0 — FINTSRC0 ...........................................791

11.7.23FIQ Interrupt Source Register 1 — FINTSRC1 ...........................................794

11.7.24FIQ Interrupt Source Register 2 — FINTSRC2 ...........................................796

11.7.25FIQ Interrupt Source Register 3 — FINTSRC3 ...........................................797

11.7.26Interrupt Priority Register 0 — IPR0 ........................................................799

11.7.27Interrupt Priority Register 1 — IPR1 ........................................................800

11.7.28Interrupt Priority Register 2 — IPR2 ........................................................801

11.7.29Interrupt Priority Register 3 — IPR3 ........................................................802

11.7.30Interrupt Priority Register 4 — IPR4 ........................................................803

11.7.31Interrupt Priority Register 5 — IPR5 ........................................................804

Intel

81341 and 81342 I/O Processors

December 2007 Developer’s Manual

Order Number: 315037-002US 19

Contents—Intel

81341 and 81342

11.7.32Interrupt Priority Register 6 — IPR6........................................................ 805

11.7.33Interrupt Priority Register 7 — IPR7........................................................ 806

12.0 Timers .................................................................................................................... 807

12.1 Timer Operation.............................................................................................. 808

12.1.1 Basic Programmable Timer Operation...................................................... 808

12.1.2 Watch Dog Timer Operation................................................................... 809

12.1.3 Load/Store Access Latency for Timer Registers......................................... 810

12.2 Timer Interrupts ............................................................................................. 811

12.3 Timer State Diagram ....................................................................................... 812

12.4 Timer Registers............................................................................................... 813

12.4.1 Power Up/Reset Initialization ................................................................. 813

12.4.2 Timer Mode Registers – TMR0:1 ............................................................. 814

12.4.2.1 Bit 0 — Terminal Count Status Bit (TMRx.tc)............................... 815

12.4.2.2 Bit 1 — Timer Enable (TMRx.enable) ......................................... 815

12.4.2.3 Bit 2 — Timer Auto Reload Enable (TMRx.reload) ........................ 815

12.4.2.4 Bit 3 — Timer Register Privileged Read/Write Control (TMRx.pri) ... 816

12.4.2.5 Bits 4, 5 — Timer Input Clock Select (TMRx.csel1:0).................... 816

12.4.3 Timer Count Register – TCR0:1 .............................................................. 817

12.4.4 Timer Reload Register – TRR0:1............................................................. 817

12.4.5 Timer Interrupt Status Register – TISR ................................................... 818

12.4.6 Watch Dog Timer Control Register – WDTCR ............................................ 819

12.4.7 Watch Dog Timer Setup Register – WDTSR .............................................. 819

12.5 Uncommon TCRX and TRRX Conditions .............................................................. 820

13.0 Inter-Processor Messaging Unit ................................................................................. 821

13.1 Overview ....................................................................................................... 821

13.2 Door Bell Registers.......................................................................................... 822

13.2.1 Door Bell Register Operation.................................................................. 823

13.3 Circular Queues .............................................................................................. 824

13.3.1 Circular Queue Operation ...................................................................... 825

13.3.1.1 Send Queue Management ........................................................ 827

13.3.1.2 Receive Queue Management..................................................... 827

13.4 Interrupts ...................................................................................................... 828

13.4.1 Interrupt Prioritization........................................................................... 829

13.5 Power-up/Default Status .................................................................................. 830

13.6 Register Definitions ......................................................................................... 830

13.6.1 Door Bell Control Register — DBCR......................................................... 832

13.6.2 Door Bell Enable Register — DBER.......................................................... 834

13.6.3 Door Bell Assertion Register — DBAR ...................................................... 835

13.6.4 Door Bell Enable Other Processor Register — DBEOR................................. 835

13.6.5 Send Queue Put/Get Pointer Register 0 — SQPG0..................................... 836

13.6.6 Send Queue Control Register 0 — SQCR0 ................................................ 837

13.6.7 Send Queue Lower Base Address Register 0 — SQLBAR0 ........................... 838

13.6.8 Send Queue Upper Base Address Register 0 — SQUBAR0........................... 838

13.6.9 Receive Queue Put/Get Pointer Register 0 — RQPG0 ................................. 839

13.6.10Receive Queue Control Register 0 — RQCR0 ............................................ 840

13.6.11Receive Queue Lower Base Address Register 0 — RQLBAR0 ....................... 840

13.6.12Receive Queue Upper Base Address Register 0 — RQUBAR0....................... 841

13.6.13Send Queue Put/Get Pointer Register 1 — SQPG1..................................... 841

13.6.14Send Queue Control Register 1 — SQCR1 ................................................ 842

13.6.15Send Queue Lower Base Address Register 1 — SQLBAR1 ........................... 843

13.6.16Send Queue Upper Base Address Register 1 — SQUBAR1........................... 843

13.6.17Receive Queue Put/Get Pointer Register 1 — RQPG1 ................................. 844

13.6.18Receive Queue Control Register 1 — RQCR1 ............................................ 845

13.6.19Receive Queue Lower Base Address Register 1 — RQLBAR1 ....................... 846

Intel

81341 and 81342—Contents

Intel

81341 and 81342 I/O Processors

Developer’s Manual December 2007

20 Order Number: 315037-002US

13.6.20Receive Queue Upper Base Address Register 1 — RQUBAR1 .......................846

13.6.21Send Queue Put/Get Pointer Register 2 — SQPG2 .....................................847

13.6.22Send Queue Control Register 2 — SQCR2................................................. 848

13.6.23Send Queue Lower Base Address Register 2 — SQLBAR2 ...........................849

13.6.24Send Queue Upper Base Address Register 2 — SQUBAR2...........................849

13.6.25Receive Queue Put/Get Pointer Register 2 — RQPG2..................................850

13.6.26Receive Queue Control Register 2 — RQCR2.............................................851

13.6.27Receive Queue Lower Base Address Register 2 — RQLBAR2........................ 852

13.6.28Receive Queue Upper Base Address Register 2 — RQUBAR2 .......................852

13.6.29Send Queue Put/Get Pointer Register 3 — SQPG3 .....................................853

13.6.30Send Queue Control Register 3 — SQCR3................................................. 854

13.6.31Send Queue Lower Base Address Register 3 — SQLBAR3 ...........................854

13.6.32Send Queue Upper Base Address Register 3 — SQUBAR3...........................855

13.6.33Receive Queue Put/Get Pointer Register 3 — RQPG3..................................855

13.6.34Receive Queue Control Register 3 — RQCR3.............................................856

13.6.35Receive Queue Lower Base Address Register 3 — RQLBAR3........................ 856

13.6.36Receive Queue Upper Base Address Register 3 — RQUBAR3 .......................857

13.6.37IMU Test and Set Registers — IMUTSR[0:511]..........................................858

13.6.37.1Endian Mode Support...............................................................859

14.0 SMBus Interface Unit.................................................................................................861

14.1 Overview........................................................................................................861

14.2 SMBus Interface ..............................................................................................861

14.3 System Management Bus Interface ....................................................................862

14.3.1 SMBus Controller..................................................................................863

14.3.1.1 SMBus Commands...................................................................863

14.3.1.2 Initialization Sequence.............................................................864

14.3.2 SMBus Signaling...................................................................................865

14.3.2.1 Overview ...............................................................................865

14.3.2.2 Waveforms.............................................................................865

14.3.2.2.1 Start Phase .......................................................................865

14.3.2.2.2 Stop Phase........................................................................866

14.3.2.2.3 ACK/NACK........................................................................866

14.3.2.2.4 Wait States........................................................................866

14.3.3 Architecture.........................................................................................867

14.3.3.1 Data Transfer Examples ...........................................................869

14.3.3.2 Configuration and Memory Reads ..............................................869

14.3.3.3 Configuration and Memory Writes..............................................872

14.3.4 Error Handling......................................................................................874

14.3.5 SMBus Interface Reset ..........................................................................874

14.4 Register Definitions..........................................................................................875

14.4.1 SMBus Controller Command Register — SM_CMD......................................875

14.4.2 SMBus Controller Byte Count Register — SM_BC.......................................876

14.4.3 SMBus Controller ADDR3 Register — SM_ADDR3.......................................876

14.4.4 SMBus Controller ADDR2 Register — SM_ADDR2.......................................876

14.4.5 SMBus Controller ADDR1 Register Number — SM_ADDR1...........................877

14.4.6 SMBus Controller ADDR0 Register Number — SM_ADDR0...........................877

14.4.7 SMBus Controller Data Register — SM_DATA ............................................ 878

14.4.8 SMBus Controller Status Register — SM_STS............................................878

15.0 UARTs.....................................................................................................................879

15.1 Overview........................................................................................................879

15.1.1 Compatibility with 16550 and 16750 .......................................................880

15.2 Signal Descriptions ..........................................................................................881

15.3 Theory of Operation .........................................................................................882

15.3.1 FIFO Interrupt Mode Operation...............................................................883

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