Intel CORE 2 DUO E4000 - 3-2008 User manual

Intel®Core™2 Extreme Processor
X6800Δand Intel®Core™2 Duo
Desktop Processor E6000Δand
E4000ΔSequence
Specification Update
— on 65 nm Process in the 775-land LGA Package supporting
Intel®64ΦArchitecture, Intel®Virtualization Technology± and
Intel®Trusted Execution Technologyŧ
May 2008
Notice: The Intel®CoreTM2 Extreme and Intel®CoreTM2 Duo desktop processor may
contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are documented in
this Specification Update.
Document Number: 313279-026

2 Intel®Core™2 Extreme Processor X6800 and
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL®PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY
WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL
PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY,
OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended
for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from
future changes to them.
Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting
operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
The Intel®Core™2 Duo and Intel®Core™2 Extreme Processors may contain design defects or errors known as errata which may
cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
ΦIntel®64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications
enabled for Intel 64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will
vary depending on your hardware and software configurations. See http://www.intel.com/technology/intel64/ for more
information including details on which processors support Intel 64, or consult with your system vendor for more information.
± Intel®Virtualization Technology requires a computer system with an enabled Intel®processor, BIOS, virtual machine monitor
(VMM) and for some uses, certain platform software enabled for it. Functionality, performance or other benefits will vary
depending on hardware and software configurations. Intel Virtualization Technology-enabled BIOS and VMM applications are
currently in development.
ŧNo computer system can provide absolute security under all conditions. Intel Trusted Execution Technology is a security
technology under development by Intel and requires for operation a computer system with Intel® Virtualization Technology, an
Intel Trusted Execution Technology-enabled Intel processor, chipset, BIOS, Authenticated Code Modules, and an Intel or other
Intel Trusted Execution Technology compatible measured virtual machine monitor. In addition, Intel Trusted Execution
Technology requires the system to contain a TPMv1.2 as defined by the Trusted Computing Group and specific software for some
uses.
ΔIntel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor
family, not across different processor families. See http://www.intel.com/products/processor_number for details.
Intel, the Intel logo, Celeron, Pentium, Xeon, Intel SpeedStep, Intel Core, and Core Inside are trademarks of Intel Corporation in
the U.S. and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2006 - 2008, Intel Corporation

Intel®Core™2 Extreme Processor X6800 and
Intel®Core™2 Duo Desktop Processor E6000 and E4000 Sequence 3
Specification Update
Contents
Contents .............................................................................................................................3
Revision History ...................................................................................................................4
Preface ...............................................................................................................................6
Summary Tables of Changes ..................................................................................................8
Identification Information ....................................................................................................17
Component Identification Information....................................................................................20
Errata ...............................................................................................................................23
Specification Changes .........................................................................................................70
Specification Clarifications ...................................................................................................71
Documentation Changes ......................................................................................................72
§

4 Intel®Core™2 Extreme Processor X6800 and
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
Revision History
Revision Description Date
-001 •Initial release of the Intel®Core™2 Extreme Processor X6800 and Intel®
Core™2 Duo Desktop Processor E6000 Sequence Specification Update
July 2006
Out of Cycle
-002
•Updated Erratum AI19, AI29 and AI40
•Added Erratum AI58-AI67
Aug 2006
-003
•Updated Erratum AI20, AI38
•Added Erratum AI68-AI77
Sept 2006
-004
•Updated Erratum AI72
•Updated Status for Erratum AI55 in Errata table
•Added Erratum AI78-AI82
•Added Specification change AI1
Oct 2006
-005
•Updated Erratum AI46 and AI53
•Replaced Erratum AI10 with a new erratum
•Added Erratum AI83 – AI85
•Corrected Plan information in Summary Table of Changes for Errata
AI16, AI69, AI70, AI72 and AI75
Nov 2006
-006
•Updated Erratum AI75 and AI83
•Replaced Erratum AI61 with a new erratum
•Added Erratum AI86 – AI90
•Corrected Plan information in Summary Table of Changes for Errata AI8
Dec 2006
-007 •Added Erratum AI91 - AI94 Jan 2007
-008
•Added L step information
•Added processor number E4300 information
Jan 2007
Out Of Cycle
-009
•Updated Erratum AI70
•Added Erratum AI95-AI97
•Updated Component Identification information table
Feb 2007
-010 •Added Erratum AI98 - AI100 Mar 2007
-011
•Added Erratum AI101-AI104
•Updated Erratum AI33 in Summary table of changes
Apr 2007
-012 •Added processor number E6320, E6420 and E4400 information Apr 2007
Out Of Cycle
-013 •Added Erratum AI105 Apr 2007
Out Of Cycle

Intel®Core™2 Extreme Processor X6800 and
Intel®Core™2 Duo Desktop Processor E6000 and E4000 Sequence 5
Specification Update
•Added Specification Clarification AI1
-014 •Updated Erratum AI14, AI25 and AI26 May 2007
-015 •Included M0 stepping and G0 stepping information (updated summary
tables of change and updated processor identification information)
July 2007
Out of Cycle
-016 •Added Errata AI106 to AI111 July 2007
-017 •Added processor number E4400 on M0 stepping information Aug 2007
Out Of Cycle
-018
•Updated Plan Status for AI33 and AI43
•Added Erratum AI112
Aug 2007
-019 •Added Erratum AI113 and AI114 Sept 2007
-020
•Added Erratum AI115 - AI123
•Updated Plan Status for AI6, AI21 - AI23, AI38 - AI42, AI44, AI50, AI55
- AI57, AI61, AI66, AI69, AI72, AI75, AI79, AI91, AI92, AI94, AI101,
AI109
Oct 2007
-021
•Added processor number E4600 information
•Added Erratum AI124
•Updated Plan status for errata AI20, AI24, AI31, AI70, AI102, AI121,
AI122 and AI123
Nov 2007
-022
•Updated Erratum AI8
•Added Erratum AI125
Dec 2007
-023 •Added Erratum AI126 Jan 16th 2008
-024
•Updated Erratum AI51
•Deleted Erratum AI123 (because it is repeat of AI108) and replaced with
a new Erratum
Feb 13th 2008
-025 •Added processor number E4700 information Mar 3rd 2008
-026 •Added Erratum AI127, AI128 May 2008

Preface
6 Intel®Core™2 Extreme Processor X6800 and
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
Preface
This document is an update to the specifications contained in the documents listed in
the following Affected Documents/Related Documents table. It is a compilation of
device and document errata and specification clarifications and changes, and is
intended for hardware system manufacturers and for software developers of
applications, operating system, and tools.
Information types defined in the Nomenclature section of this document are
consolidated into this update document and are no longer published in other
documents. This document may also contain information that has not been previously
published.
Affected Documents
Document Title Document Number
Intel®Core™2 Extreme Processor X6800 and Intel®Core™2 Duo
Desktop Processor E6000 and E4000 Sequence Datasheet 313278-008
Related Documents
Document Title Document Location
Intel®64 and IA-32 Architectures Software Developer’s
Manual Volume 1: Basic Architecture
Intel®64 and IA-32 Architectures Software Developer’s
Manual Volume 2A: Instruction Set Reference Manual A–M
Intel®64 and IA-32 Architectures Software Developer’s
Manual Volume 2B: Instruction Set Reference Manual, N–Z
Intel®64 and IA-32 Architectures Software Developer’s
Manual Volume 3A: System Programming Guide
Intel®64 and IA-32 Architectures Software Developer’s
Manual Volume 3B: System Programming Guide
http://www.intel.com/product
s/processor/manuals/index.h
tm

Preface
Intel®Core™2 Extreme Processor X6800 and
Intel®Core™2 Duo Desktop Processor E6000 and E4000 Sequence 7
Specification Update
Nomenclature
S-Spec Number is a five-digit code used to identify products. Products are
differentiated by their unique characteristics (e.g., core speed, L2 cache size, package
type, etc.) as described in the processor identification information table. Care should
be taken to read all notes associated with each S-Spec number
QDF Number is a several digit code that is used to distinguish between engineering
samples. These processors are used for qualification and early design validation. The
functionality of these parts can range from mechanical only to fully functional. The
NDA specification update has a processor identification information table that lists
these QDF numbers and the corresponding product sample details.
Errata are design defects or errors. Errata may cause the processor’s behavior to
deviate from published specifications. Hardware and software designed to be used
with any given stepping must assume that all errata documented for that stepping are
present on all devices.
Specification Changes are modifications to the current published specifications.
These changes will be incorporated in the next release of the specifications.
Specification Clarifications describe a specification in greater detail or further
highlight a specification’s impact to a complex design situation. These clarifications
will be incorporated in the next release of the specifications.
Documentation Changes include typos, errors, or omissions from the current
published specifications. These changes will be incorporated in the next release of the
specifications.
Note: Errata remain in the specification update throughout the product’s lifecycle, or until a
particular stepping is no longer commercially available. Under these circumstances,
errata removed from the specification update are archived and available upon request.
Specification changes, specification clarifications and documentation changes are
removed from the specification update when the appropriate changes are made to the
appropriate product specification or user documentation (datasheets, manuals, etc.).
§

Summary Tables of Changes
8 Intel®Core™2 Extreme Processor X6800 and
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
Summary Tables of Changes
The following table indicates the Specification Changes, Errata, Specification
Clarifications or Documentation Changes, which apply to the listed MCH steppings.
Intel intends to fix some of the errata in a future stepping of the component, and to
account for the other outstanding issues through documentation or Specification
Changes as noted. This table uses the following notations:
Codes Used in Summary Table
Stepping
X: Erratum, Specification Change or Clarification that applies
to this stepping.
(No mark) or (Blank Box): This erratum is fixed in listed stepping or specification
change does not apply to listed stepping.
Status
Doc: Document change or update that will be implemented.
PlanFix: This erratum may be fixed in a future stepping of the
product.
Fixed: This erratum has been previously fixed.
NoFix: There are no plans to fix this erratum.
Row
Shaded: This item is either new or modified from the previous
version of the document.

Summary Tables of Changes
Intel®Core™2 Extreme Processor X6800 and
Intel®Core™2 Duo Desktop Processor E6000 and E4000 Sequence 9
Specification Update
Item Numbering
Each Specification Update item is prefixed with a capital letter to distinguish the
product. The key below details the letters that are used in Intel’s microprocessor
specification updates:
A = Dual-Core Intel® Xeon® processor 7000 sequence
C = Intel® Celeron® processor
D = Dual-Core Intel® Xeon® processor 2.80 GHz
E = Intel® Pentium® III processor
F =
Intel® Pentium® processor Extreme Edition and Intel® Pentium® D
processor
I = Dual-Core Intel® Xeon® processor 5000 series
J = 64-bit Intel® Xeon® processor MP with 1MB L2 cache
K = Mobile Intel® Pentium® III processor
L = Intel® Celeron® D processor
M = Mobile Intel® Celeron® processor
N = Intel® Pentium® 4 processor
O = Intel® Xeon® processor MP
P = Intel ® Xeon® processor
Q =
Mobile Intel® Pentium® 4 processor supporting Hyper-Threading technology
on 90-nm process technology
R = Intel® Pentium® 4 processor on 90 nm process
S =
64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2
cache versions)
T = Mobile Intel® Pentium® 4 processor-M
U = 64-bit Intel® Xeon® processor MP with up to 8MB L3 cache
V =
Mobile Intel® Celeron® processor on .13 micron process in Micro-FCPGA
package
W= Intel® Celeron® M processor
X =
Intel® Pentium® M processor on 90nm process with 2-MB L2 cache and
Intel® processor A100 and A110 with 512-KB L2 cache
Y = Intel® Pentium® M processor
Z = Mobile Intel® Pentium® 4 processor with 533 MHz system bus
AA =
Intel® Pentium® D processor 900 sequence and Intel® Pentium® processor
Extreme Edition 955, 965
AB = Intel® Pentium® 4 processor 6x1 sequence
AC = Intel(R) Celeron(R) processor in 478 pin package
AD = Intel(R) Celeron(R) D processor on 65nm process
AE =
Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65nm
process
AF = Dual-Core Intel® Xeon® processor LV
AG = Dual-Core Intel® Xeon® processor 5100 series

Summary Tables of Changes
10 Intel®Core™2 Extreme Processor X6800 and
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
AH =
Intel® Core™2 Duo/Solo processor for Intel® Centrino® Duo processor
technology
AI =
Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop
processor E6000 and E4000 sequence
AJ = Quad-Core Intel® Xeon® processor 5300 series
AK =
Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel®
Core™2 Quad processor Q6000 sequence
AL = Dual-Core Intel® Xeon® processor 7100 series
AM = Intel® Celeron® processor 400 sequence
AN = Intel® Pentium® dual-core processor
AO = Quad-Core Intel® Xeon® processor 3200 series
AP = Dual-Core Intel® Xeon® processor 3000 series
AQ = Intel® Pentium® dual-core desktop processor E2000 sequence
AR = Intel® Celeron® processor 500 series
AS = Intel® Xeon® processor 7200, 7300 series
AV = Intel® Core™2 Extreme processor QX9650 and Intel® Core™2 Quad processor
Q9000 series
AW = Intel® Core™ 2 Duo processor E8000 series
AX = Quad-Core Intel® Xeon® processor 5400 series
AY= Dual-Core Intel® Xeon® processor 5200 series
AZ =
Intel® Core™2 Duo Processor and Intel® Core™2 Extreme Processor on 45-
nm Process
AAA = Quad-Core Intel® Xeon® processor 3300 series
AAB = Dual-Core Intel® Xeon® E3110 Processor
AAC = Intel® Celeron® dual-core processor E1000 series
AAD = Intel® Core™2 Extreme Processor QX9775Δ
AAE = Intel® Atom™ processor Z5xx series
The Specification Updates for the Pentium®processor, Pentium®Pro processor, and
other Intel products do not use this convention.
NO B1 B2 L2 M0 G0 Plan ERRATA
AI1 X X X X X No Fix
Writing the Local Vector Table (LVT) when an Interrupt is Pending May
Cause an Unexpected Interrupt
AI2 X X X X X No Fix
LOCK# Asserted During a Special Cycle Shutdown Transaction May
Unexpectedly De-assert
AI3 X X X X X No Fix
Address Reported by Machine-Check Architecture (MCA) on Single-bit
L2 ECC Errors May be Incorrect
AI4 X X X X X No Fix
VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last
Exception Record (LER) MSR
AI5 X X X X X No Fix
DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store Instruction
May Incorrectly Increment Performance Monitoring Count for Saturating
SIMD Instructions Retired (Event CFH)
AI6 X X X X Fixed SYSRET May Incorrectly Clear RF (Resume Flag) in the RFLAGS Register
AI7 X X X X X No Fix
General Protection Fault (#GP) for Instructions Greater than 15 Bytes
May be Preempted