Intel 80331 Guide

Intel®80331 I/O Processor
Design Guide
March 2005
Order Number:273823-003

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Intel® 80331 I/O Processor Design Guide
Contents
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Intel® 80331 I/O Processor Design Guide
Contents
Contents
1 Introduction..................................................................................................................................11
1.1 About This Document .........................................................................................................11
1.1.1 Terminology and Definitions ..................................................................................12
1.1.2 Other Relevant Documents ...................................................................................14
1.2 About the Intel®80331 I/O Processor.................................................................................15
2 Package Information ...................................................................................................................17
2.1 Power Plane Layout............................................................................................................21
2.2 Intel®80331 I/O Processor Applications.............................................................................22
3Terminations................................................................................................................................23
3.1 Analog Filters......................................................................................................................27
3.1.1 VCCPLL Pin Requirements......................................................................................27
3.2 DDR Resistor Compensation..............................................................................................28
3.3 DDR Driver Compensation .................................................................................................29
4 Routing Guidelines......................................................................................................................31
4.1 General Routing Guidelines................................................................................................31
4.2 Crosstalk.............................................................................................................................32
4.3 EMI Considerations ............................................................................................................34
4.4 Power Distribution and Decoupling.....................................................................................34
4.4.1 Decoupling.............................................................................................................34
4.5 Trace Impedance................................................................................................................36
5 Board Layout Guidelines............................................................................................................37
5.1 Motherboard Stack Up Information.....................................................................................37
5.2 Adapter Card Stackup ........................................................................................................39
6 PCI-X Layout Guidelines.............................................................................................................41
6.1 Interrupt Routing and IDSEL Lines.....................................................................................41
6.1.1 PCI Arbitration .......................................................................................................42
6.1.2 PCI Resistor Compensation ..................................................................................42
6.2 PCI General Layout Guidelines ..........................................................................................43
6.3 PCI-X Topology Layout Guidelines.....................................................................................43
6.4 Intel®80331 I/O Processor PCI/X Layout Analysis ............................................................44
6.4.1 PCI Clock Layout Guidelines.................................................................................45
6.4.2 Single-Slot at 133 MHz..........................................................................................48
6.4.3 Embedded PCI-X 133 MHz ...................................................................................49
6.4.4 Embedded PCI-X 133 MHz Alternate Topology ....................................................50
6.4.5 Combination of PCI-X 133 MHz Slot and Embedded Topology ............................51
6.4.6 Combination PCI-X 133 MHz Slot and Embedded Topology 2 .............................52
6.4.7 PCI-X 100 MHz Slot Topology...............................................................................53
6.4.8 PCI-X 100 MHz Embedded Topology....................................................................54
6.4.9 PCI-X 100 MHz Slot and Embedded Topology......................................................55
6.4.10 PCI-X 100 MHz Slot and Embedded Topology 2...................................................56
6.4.11 PCI-X 66 MHz Slot Topology.................................................................................57
6.4.12 PCI-X 66 MHz Embedded Topology......................................................................58
6.4.13 PCI-X 66 MHz Mixed Mode Topology....................................................................59

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6.4.14 PCI 66 MHz Slot Topology ....................................................................................60
6.4.15 PCI 66 MHz Embedded Topology .........................................................................61
6.4.16 PCI 66 MHz Mixed Mode Topology.......................................................................62
6.4.17 PCI 33 MHz Slot Topology ....................................................................................63
6.4.18 PCI 33 MHz Embedded Mode Topology...............................................................64
6.4.19 PCI 33 MHz Mixed Topology.................................................................................65
7 Memory Controller.......................................................................................................................67
7.1 DDR Bias Voltages.............................................................................................................67
7.2 Intel®80331 I/O Processor DDR Overview........................................................................68
7.3 DDR 333 Signal Integrity Simulation Conditions ................................................................69
7.3.1 DDR 333 Stackup Example...................................................................................70
7.4 DDR Layout Guidelines......................................................................................................72
7.4.1 Source Synchronous Signal Group .......................................................................72
7.4.1.1 Routing Requirements...........................................................................73
7.4.2 Clock Signal Groups..............................................................................................81
7.4.2.1 Control Signals Termination...................................................................85
7.4.3 Embedded Configuration.......................................................................................89
7.4.3.1 DDR 333 Source Synchronous Routine Guidelines ..............................89
7.4.3.2 DDR 333 Embedded Clock Routing Recommendations .......................92
7.4.3.3 DDR 333 Embedded Address/Command/Control Routing Guidelines..96
7.5 DDR II 400 Layout Guidelines..........................................................................................101
7.5.1 Simulation Conditions..........................................................................................102
7.5.2 DDRII-400 Trace Width/Impedance Requirements .............................................103
7.5.3 DIMM Layout Design...........................................................................................104
7.5.3.1 DDR II 400 DIMM Source Synchronous Routing.................................104
7.5.3.2 DDRII 400 Clock Routing Guidelines...................................................107
7.5.3.3 DDRII 400 Address/Command/Control Routing Guidelines ................108
7.5.4 Embedded Configuration.....................................................................................110
7.5.4.1 DDRII 400 Embedded Source Synchronous Routine Guidelines........110
7.5.4.2 DDRII 400 Embedded Clock Routing Recommendations ...................113
7.5.4.3 DDRII 400 Embedded Address/Command/Control Routing Guidelines....
116
7.6 DDR Signal Termination...................................................................................................120
7.7 DDR Termination Voltage.................................................................................................121
7.8 DDR VREF Voltage............................................................................................................121
8 Peripheral Local Bus.................................................................................................................123
8.1 Peripheral Bus Signals .....................................................................................................123
8.1.1 Address/Data Signal Definitions..........................................................................123
8.1.2 Control/Status Signal Definitions.........................................................................123
8.1.3 Bus Width ............................................................................................................124
8.1.4 Flash Memory Support ........................................................................................125
8.1.5 Layout Guidelines for the Peripheral Bus............................................................126
8.2 Topology Layout Guidelines.............................................................................................127
9 Power Delivery...........................................................................................................................131
9.1 Power Sequencing............................................................................................................131
9.2 Power Failure....................................................................................................................132
9.2.1 Theory of Operation.............................................................................................132
9.2.2 Power Failure Sequence .....................................................................................132
9.2.3 Power Delay ........................................................................................................133

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9.3 Battery Backup .................................................................................................................134
9.3.1 Non-Battery Backup Circuits................................................................................135
10 Intel®IQ80331 Evaluation Platform Board ..............................................................................137
11 JTAG Circuitry for Debug .........................................................................................................139
11.1 Requirements ...................................................................................................................139
11.2 JTAG Signals / Header.....................................................................................................140
11.3 System Requirements ......................................................................................................141
11.4 JTAG Hardware Requirements.........................................................................................142
11.4.1 Macraigor Raven and WindRiver Systems visionPROBE / visionICE.................142
11.4.2 ARM Multi-ICE.....................................................................................................142
12 Debug Connectors and Logic Analyzer Connectivity............................................................143
12.1 Probing PCI-X Signals......................................................................................................143
13 References .................................................................................................................................147
13.1 Related Documents ..........................................................................................................147
13.2 Electronic Information.......................................................................................................148

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Intel® 80331 I/O Processor Design Guide
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Figures
1Intel
®80331 I/O Processor Functional Block Diagram...............................................................16
2Intel
®80331 I/O Processor 829-Ball FCBGA Package Diagram................................................18
3Intel
®80331 I/O Processor Preliminary Ballout (Top View) .......................................................19
4Intel
®80331 I/O Processor Preliminary Ballout (Bottom View)..................................................20
5Intel
®80331 I/O Processor Power Plane Layout........................................................................21
6Intel
®80331 I/O Processor PCI-X Adapter Card Block Diagram ...............................................22
7V
CCPLL Configuration..................................................................................................................27
8 Intel
®80331 I/O Processor DDRRES Resistor Compensation Circuitry...................................28
9 DDR Driver Compensation Circuitry...........................................................................................29
10 Crosstalk Effects on Trace Distance and Height........................................................................32
11 PCB Ground Layout Around Connectors ...................................................................................33
12 Motherboard Stackup Recommendations ..................................................................................38
13 Adapter Card Stackup ................................................................................................................40
14 Interrupt and IDSEL Mapping.....................................................................................................41
15 PCI RCOMP ...............................................................................................................................42
16 PCI Clock Distribution and Matching Requirements...................................................................45
17 Single-Slot Point-to-Point Topology............................................................................................48
18 Embedded PCI-X 133 MHz Topology ........................................................................................49
19 Embedded PCI-X 133 MHz Alternate Topology.........................................................................50
20 Embedded PCI-X 133 MHz Topology ........................................................................................51
21 Embedded PCI-X 133 MHz Topology ........................................................................................52
22 Slot PCI-X 100 MHz Slot Routing Topology...............................................................................53
23 Embedded PCI-X 100 MHz Routing Topology...........................................................................54
24 Combination of Slot and Embedded PCI-X 100 MHz Routing Topology....................................55
25 Combination of Slots and Embedded PCI-X 100 MHz Routing Topology..................................56
26 PCI-X 66 MHz Slot Routing Topology ........................................................................................57
27 PCI-X 66 MHz Embedded Routing Topology.............................................................................58
28 PCI-X 66 MHz Mixed Mode Routing Topology...........................................................................59
29 PCI 66 MHz Topology ................................................................................................................60
30 PCI 66 MHz Embedded Topology..............................................................................................61
31 PCI 66 MHz Mixed Topology......................................................................................................62
32 PCI 33 MHz Slot Routing Topology............................................................................................63
33 PCI 33 MHz Embedded Mode Routing Topology.......................................................................64
34 PCI 33 MHz Mixed Mode Routing Topology ..............................................................................65
35 100 ohm Differential Trace .........................................................................................................71
36 Source Synchronous Length Matching.......................................................................................73
37 Data Group Length Matching .....................................................................................................73
38 DIMM DQ/DQS Topology...........................................................................................................79
39 DIMM DQ/DQS Split Termination Topology...............................................................................80
40 DDR 333 Registered DIMM Clock Topology..............................................................................83
41 DDR 333 Unbuffered DIMM Clock Topology..............................................................................84
42 Trace Length Requirements for Source Clocked Routing..........................................................85
43 DDR 333 DIMM Unbuffered/Registered Address/CMD Topology Lengths................................87
44 Embedded DDR 333 DQ/DQS Topology ...................................................................................91
45 Embedded DDR 333 Buffered Clock Topology..........................................................................92
46 Embedded DDR 333 Unbuffered Clock Topology......................................................................95
47 Embedded DDR 333 Unbuffered ADDR/CMD Topology ...........................................................98
48 Embedded DDR 333 Registered ADDR/CMD Topology..........................................................100

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49 Intel®80331 I/O Processor DDRII 400 DIMM Source Synchronous Routing..........................104
50 DDR II 400 DIMM DQ Topology...............................................................................................106
51 DDR II 400 DIMM DQS Topology.............................................................................................106
52 DDR II 400 DIMM Clock Topology............................................................................................107
53 DDR II 400 DIMM Address/CMD Topology..............................................................................109
54 DDR II 400 DIMM Address/CMD Split Termination Topology..................................................109
55 DDR II 400 Embedded DQ Topology .......................................................................................111
56 DDR II 400 Embedded DQS Topology.....................................................................................112
57 DDR II 400 Embedded Clock Topology....................................................................................115
58 DDR II 400 Embedded Address/Control Topology...................................................................118
59 DDR II 400 Embedded Address/Control Topology With Split Termination...............................119
60 Routing Termination Resistors (top view).................................................................................120
61 DDR VREF Circuit......................................................................................................................121
62 Data Width and Low Order Address Lines ...............................................................................124
63 Four MByte Flash Memory System ..........................................................................................125
64 Peripheral Bus Unlatched Bidirectional Single Load Topology.................................................127
65 Peripheral Bus Latched Bidirectional Single Load Topology....................................................128
66 Peripheral Bus Latched Bidirectional Two Load Topology.......................................................129
67 Power Failure Comparator Circuit ............................................................................................133
68 SCKE Circuit.............................................................................................................................134
69 Intel®IQ80331 Evaluation Platform Board CRB Block Diagram ..............................................137
70 Intel®80331 I/O Processor CRB Form Factor..........................................................................138
71 JTAG Header Pin Out...............................................................................................................140
72 JTAG Signals at Powerup.........................................................................................................141
73 JTAG Signals at Debug Startup................................................................................................141
74 Example Power-Up Circuit for nTRST......................................................................................142

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Tables
1 Terminology and Definitions.......................................................................................................12
2 FC-style, H-PBGA Package Dimensions....................................................................................17
3 Terminations: Pull-up/Pull-down.................................................................................................23
4 Decoupling Recommendations...................................................................................................34
5 Motherboard Stack Up, Stripline and Microstrip.........................................................................37
6 Adapter Card Stack Up, Microstrip and Stripline........................................................................39
7 PCI-X Slot Guidelines.................................................................................................................43
8 PCI-X Clock Layout Requirements Summary ............................................................................46
9 PCI-X 133 MHz Single Slot Routing Recommendations............................................................48
10 Embedded PCI-X 133 MHz Routing Recommendations............................................................49
11 Embedded PCI-X 133 MHz Alternate Topology Routing Recommendations.............................50
12 Embedded and Slot PCI-X 133 MHz Routing Recommendations..............................................51
13 Embedded and Slot PCI-X 133 MHz Routing Recommendations..............................................52
14 PCI-X 100 MHz Slot Topology Routing Recommendations .......................................................53
15 PCI-X 100 MHz Embedded Routing Recommendations............................................................54
16 Combination of Slot and Embedded PCI-X 100 MHz Routing Recommendations ....................55
17 Combination of Slot and Embedded PCI-X 100 MHz Routing 2 Recommendations .................56
18 PCI-X 66 MHz Slot Routing Recommendations.........................................................................57
19 PCI-X 66 MHz Embedded Routing Recommendations..............................................................58
20 PCI-X 66 MHz Mixed Mode Routing Recommendations............................................................59
21 PCI 66 MHz Slot Table...............................................................................................................60
22 PCI 66 MHz Embedded Table....................................................................................................61
23 PCI 66 MHz Mixed Mode Table..................................................................................................62
24 PCI 33 MHz Slot Routing Recommendations.............................................................................63
25 PCI 33 MHz Embedded Routing Recommendations .................................................................64
26 PCI 33 MHz Mixed Mode Routing Recommendations ...............................................................65
27 DDR Bias Voltages.....................................................................................................................67
28 DDR II Bias Voltage....................................................................................................................67
29 Core Speed and Memory Configuration.....................................................................................68
30 Simulated DDR 333 Topologies.................................................................................................69
31 Example Topologies for DDR Trace...........................................................................................71
32 x64 DDR Memory Configuration.................................................................................................72
33 x72 DDR Memory Configuration.................................................................................................72
34 Source Synchronous Termination Requirements.......................................................................73
35 Source Synchronous Routing Recommendations......................................................................74
36 DIMM DQ/DQS Topology Lengths.............................................................................................75
37 Die to Ball Internal Lengths ........................................................................................................75
38 DIMM DQ/DQS Split Termination Topology Lengths .................................................................80
39 DIMM Clocked Signal Group Termination..................................................................................81
40 Clock Signal Group Registered/Unbuffered DIMM Routing Requirements................................82
41 Registered DIMM Clock Topology Lengths................................................................................83
42 DDR 333 Unbuffered DIMM Clock Topology Lengths................................................................84
43 Source Clocked Signal Routing..................................................................................................85
44 Control Signals Routing Guidelines............................................................................................86
45 Control Signal DIMM Topology Lengths.....................................................................................88
46 DDR 333 Embedded Source Synchronous Routing Recommendations....................................89
47 Embedded DDR 333 DQ/DQS Topology Lengths......................................................................91
48 DDR 333 Embedded Registered/Unbuffered Clock Routing Recommendations.......................93

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Intel® 80331 I/O Processor Design Guide
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49 Embedded DDR 333 Buffered Clock Topology Lengths ............................................................94
50 Embedded DDR 333 Unbuffered Clock Topology Lengths........................................................95
51 DDR 333 Embedded Address/Command Routing Recommendations ......................................96
52 Embedded DDR 333 Unbuffered Address/CMD Topology Lengths...........................................98
53 Embedded DDR 333 Registered Address/CMD Topology Lengths...........................................99
54 x64 DDR Memory Configuration...............................................................................................101
55 x72 DDR Memory Configuration...............................................................................................101
56 DDR II Topologies Simulated ...................................................................................................102
57 Example Topology for DDRII Trace Width/Impedance Requirements .....................................103
58 DDRII 400 DIMM Source Synchronous Routing Recommendations........................................105
60 DDR II 400 DIMM DQS Lengths...............................................................................................106
59 DDR II 400 DIMM DQ Lengths.................................................................................................106
61 DDRII 400 DIMM Clock Routing Recommendations................................................................107
62 DDR II 400 DIMM Clock Lengths..............................................................................................107
63 DDRII 400 DIMM Address/Command/Control Routing Recommendation ...............................108
64 DDR II 400 DIMM Address/CMD Lengths................................................................................109
65 DDRII 400 Embedded Source Synchronous Routing Recommendations................................110
66 DDR II 400 Embedded DQ Lengths .........................................................................................111
67 DDR II 400 Embedded DQS Lengths.......................................................................................112
68 DDRII 400 Embedded Clock Routing Recommendations........................................................113
69 DDR II 400 Embedded Clock (PLL) Lengths............................................................................114
70 DDRII 400 Embedded Address/Command/Control Routing Recommendations......................116
71 DDR II 400 Embedded Address/CMD Lengths ........................................................................117
72 Flash Wait State Profile Programming .....................................................................................125
73 Routing Guideline Bidirectional Single Load.............................................................................127
74 Routing Guideline Latched Bidirectional Latch Single Load.....................................................128
75 Routing Guideline Latch Bidirectional Two Loads....................................................................129
76 Intel®80331 I/O Processor Bias Voltages...............................................................................131
77 Four Peaks Customer Reference Board Features ...................................................................138
78 Logic Analyzer Pod 1................................................................................................................143
80 Logic Analyzer Pod 3................................................................................................................144
79 Logic Analyzer Pod 2................................................................................................................144
82 Logic Analyzer Pod 5................................................................................................................145
81 Logic Analyzer Pod 4................................................................................................................145
83 Logic Analyzer Pod 6................................................................................................................146
84 Design References...................................................................................................................147
85 Intel Related Documentation ....................................................................................................147
86 Electronic Information...............................................................................................................148

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Intel® 80331 I/O Processor Design Guide
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Revision History
TaTa
Date Revision Description
March 2005 003 Updated Figure 27, Figure 33, and Figure 49.
October 2004 002
In Chapter 6:
Table 8: added row Preferred Topology: stripline
Table 8: changed Clock Layout Requirements Add-in card
impedance from 60 ohms to 57 ohms.
Changed topology information in Figure 24 and Table 16.
Table 17 Added alternate PCI-X 100MHz Slot and Embedded
Topology Figure 25 and Table 16.
Table 18 Changed Add-in card impedance from 60 ohms +/-
15% to 57 ohms +/- 15%.
In Chapter 7:
DDR 333 Source Synchronous recommendations removed the
requirement for length matching for DQS groups based on
simulations
Removed row in Table 48 “Length Matching Requirements:
between clock groups”. This is required only for unbuffered
clocks and was already mentioned in the previous row.
Table 51: removed row in “Trace Length: 80331 signal Ball to
Series Termination” because the series termination is no
longer needed.
Table 52: Removed Routing Guideline 4 because unbuffered
and registered DIMM’s have the same topology.
Deleted Figure 57 because simulations showed that series
resistors is no longer needed for DDR 333 DIMM control
signals
Table 53: Removed Length Matching within DQS group
recommendation now because length matching will happen
when matching to M_CK.
Changed Embedded DDR 333 DQ/DQS Topology Figure 44
resistor listed as 50 ohms +/- 5% to 51 ohms +/- 5% because
this is a standard value resistor.
In Chapter 9
Removed VCC25/VCC18 from the power up sequence order
and added a note stating that there is no sequence order
requirements for the VCC25 or VCC18 rail.
Other:
Moved the decoupling guidelines from Chapter 3 to Chapter 4.
Removed reference to the Hot Plug controller. This feature is
not part of the 80331 product.
September 2003 001 Initial Release.