Intel 80331 Guide

Intel®80331 I/O Processor
Design Guide
March 2005
Order Number:273823-003

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Intel® 80331 I/O Processor Design Guide
Contents
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Intel® 80331 I/O Processor Design Guide
Contents
Contents
1 Introduction..................................................................................................................................11
1.1 About This Document .........................................................................................................11
1.1.1 Terminology and Definitions ..................................................................................12
1.1.2 Other Relevant Documents ...................................................................................14
1.2 About the Intel®80331 I/O Processor.................................................................................15
2 Package Information ...................................................................................................................17
2.1 Power Plane Layout............................................................................................................21
2.2 Intel®80331 I/O Processor Applications.............................................................................22
3Terminations................................................................................................................................23
3.1 Analog Filters......................................................................................................................27
3.1.1 VCCPLL Pin Requirements......................................................................................27
3.2 DDR Resistor Compensation..............................................................................................28
3.3 DDR Driver Compensation .................................................................................................29
4 Routing Guidelines......................................................................................................................31
4.1 General Routing Guidelines................................................................................................31
4.2 Crosstalk.............................................................................................................................32
4.3 EMI Considerations ............................................................................................................34
4.4 Power Distribution and Decoupling.....................................................................................34
4.4.1 Decoupling.............................................................................................................34
4.5 Trace Impedance................................................................................................................36
5 Board Layout Guidelines............................................................................................................37
5.1 Motherboard Stack Up Information.....................................................................................37
5.2 Adapter Card Stackup ........................................................................................................39
6 PCI-X Layout Guidelines.............................................................................................................41
6.1 Interrupt Routing and IDSEL Lines.....................................................................................41
6.1.1 PCI Arbitration .......................................................................................................42
6.1.2 PCI Resistor Compensation ..................................................................................42
6.2 PCI General Layout Guidelines ..........................................................................................43
6.3 PCI-X Topology Layout Guidelines.....................................................................................43
6.4 Intel®80331 I/O Processor PCI/X Layout Analysis ............................................................44
6.4.1 PCI Clock Layout Guidelines.................................................................................45
6.4.2 Single-Slot at 133 MHz..........................................................................................48
6.4.3 Embedded PCI-X 133 MHz ...................................................................................49
6.4.4 Embedded PCI-X 133 MHz Alternate Topology ....................................................50
6.4.5 Combination of PCI-X 133 MHz Slot and Embedded Topology ............................51
6.4.6 Combination PCI-X 133 MHz Slot and Embedded Topology 2 .............................52
6.4.7 PCI-X 100 MHz Slot Topology...............................................................................53
6.4.8 PCI-X 100 MHz Embedded Topology....................................................................54
6.4.9 PCI-X 100 MHz Slot and Embedded Topology......................................................55
6.4.10 PCI-X 100 MHz Slot and Embedded Topology 2...................................................56
6.4.11 PCI-X 66 MHz Slot Topology.................................................................................57
6.4.12 PCI-X 66 MHz Embedded Topology......................................................................58
6.4.13 PCI-X 66 MHz Mixed Mode Topology....................................................................59

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Intel® 80331 I/O Processor Design Guide
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6.4.14 PCI 66 MHz Slot Topology ....................................................................................60
6.4.15 PCI 66 MHz Embedded Topology .........................................................................61
6.4.16 PCI 66 MHz Mixed Mode Topology.......................................................................62
6.4.17 PCI 33 MHz Slot Topology ....................................................................................63
6.4.18 PCI 33 MHz Embedded Mode Topology...............................................................64
6.4.19 PCI 33 MHz Mixed Topology.................................................................................65
7 Memory Controller.......................................................................................................................67
7.1 DDR Bias Voltages.............................................................................................................67
7.2 Intel®80331 I/O Processor DDR Overview........................................................................68
7.3 DDR 333 Signal Integrity Simulation Conditions ................................................................69
7.3.1 DDR 333 Stackup Example...................................................................................70
7.4 DDR Layout Guidelines......................................................................................................72
7.4.1 Source Synchronous Signal Group .......................................................................72
7.4.1.1 Routing Requirements...........................................................................73
7.4.2 Clock Signal Groups..............................................................................................81
7.4.2.1 Control Signals Termination...................................................................85
7.4.3 Embedded Configuration.......................................................................................89
7.4.3.1 DDR 333 Source Synchronous Routine Guidelines ..............................89
7.4.3.2 DDR 333 Embedded Clock Routing Recommendations .......................92
7.4.3.3 DDR 333 Embedded Address/Command/Control Routing Guidelines..96
7.5 DDR II 400 Layout Guidelines..........................................................................................101
7.5.1 Simulation Conditions..........................................................................................102
7.5.2 DDRII-400 Trace Width/Impedance Requirements .............................................103
7.5.3 DIMM Layout Design...........................................................................................104
7.5.3.1 DDR II 400 DIMM Source Synchronous Routing.................................104
7.5.3.2 DDRII 400 Clock Routing Guidelines...................................................107
7.5.3.3 DDRII 400 Address/Command/Control Routing Guidelines ................108
7.5.4 Embedded Configuration.....................................................................................110
7.5.4.1 DDRII 400 Embedded Source Synchronous Routine Guidelines........110
7.5.4.2 DDRII 400 Embedded Clock Routing Recommendations ...................113
7.5.4.3 DDRII 400 Embedded Address/Command/Control Routing Guidelines....
116
7.6 DDR Signal Termination...................................................................................................120
7.7 DDR Termination Voltage.................................................................................................121
7.8 DDR VREF Voltage............................................................................................................121
8 Peripheral Local Bus.................................................................................................................123
8.1 Peripheral Bus Signals .....................................................................................................123
8.1.1 Address/Data Signal Definitions..........................................................................123
8.1.2 Control/Status Signal Definitions.........................................................................123
8.1.3 Bus Width ............................................................................................................124
8.1.4 Flash Memory Support ........................................................................................125
8.1.5 Layout Guidelines for the Peripheral Bus............................................................126
8.2 Topology Layout Guidelines.............................................................................................127
9 Power Delivery...........................................................................................................................131
9.1 Power Sequencing............................................................................................................131
9.2 Power Failure....................................................................................................................132
9.2.1 Theory of Operation.............................................................................................132
9.2.2 Power Failure Sequence .....................................................................................132
9.2.3 Power Delay ........................................................................................................133

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9.3 Battery Backup .................................................................................................................134
9.3.1 Non-Battery Backup Circuits................................................................................135
10 Intel®IQ80331 Evaluation Platform Board ..............................................................................137
11 JTAG Circuitry for Debug .........................................................................................................139
11.1 Requirements ...................................................................................................................139
11.2 JTAG Signals / Header.....................................................................................................140
11.3 System Requirements ......................................................................................................141
11.4 JTAG Hardware Requirements.........................................................................................142
11.4.1 Macraigor Raven and WindRiver Systems visionPROBE / visionICE.................142
11.4.2 ARM Multi-ICE.....................................................................................................142
12 Debug Connectors and Logic Analyzer Connectivity............................................................143
12.1 Probing PCI-X Signals......................................................................................................143
13 References .................................................................................................................................147
13.1 Related Documents ..........................................................................................................147
13.2 Electronic Information.......................................................................................................148

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Intel® 80331 I/O Processor Design Guide
Contents
Figures
1Intel
®80331 I/O Processor Functional Block Diagram...............................................................16
2Intel
®80331 I/O Processor 829-Ball FCBGA Package Diagram................................................18
3Intel
®80331 I/O Processor Preliminary Ballout (Top View) .......................................................19
4Intel
®80331 I/O Processor Preliminary Ballout (Bottom View)..................................................20
5Intel
®80331 I/O Processor Power Plane Layout........................................................................21
6Intel
®80331 I/O Processor PCI-X Adapter Card Block Diagram ...............................................22
7V
CCPLL Configuration..................................................................................................................27
8 Intel
®80331 I/O Processor DDRRES Resistor Compensation Circuitry...................................28
9 DDR Driver Compensation Circuitry...........................................................................................29
10 Crosstalk Effects on Trace Distance and Height........................................................................32
11 PCB Ground Layout Around Connectors ...................................................................................33
12 Motherboard Stackup Recommendations ..................................................................................38
13 Adapter Card Stackup ................................................................................................................40
14 Interrupt and IDSEL Mapping.....................................................................................................41
15 PCI RCOMP ...............................................................................................................................42
16 PCI Clock Distribution and Matching Requirements...................................................................45
17 Single-Slot Point-to-Point Topology............................................................................................48
18 Embedded PCI-X 133 MHz Topology ........................................................................................49
19 Embedded PCI-X 133 MHz Alternate Topology.........................................................................50
20 Embedded PCI-X 133 MHz Topology ........................................................................................51
21 Embedded PCI-X 133 MHz Topology ........................................................................................52
22 Slot PCI-X 100 MHz Slot Routing Topology...............................................................................53
23 Embedded PCI-X 100 MHz Routing Topology...........................................................................54
24 Combination of Slot and Embedded PCI-X 100 MHz Routing Topology....................................55
25 Combination of Slots and Embedded PCI-X 100 MHz Routing Topology..................................56
26 PCI-X 66 MHz Slot Routing Topology ........................................................................................57
27 PCI-X 66 MHz Embedded Routing Topology.............................................................................58
28 PCI-X 66 MHz Mixed Mode Routing Topology...........................................................................59
29 PCI 66 MHz Topology ................................................................................................................60
30 PCI 66 MHz Embedded Topology..............................................................................................61
31 PCI 66 MHz Mixed Topology......................................................................................................62
32 PCI 33 MHz Slot Routing Topology............................................................................................63
33 PCI 33 MHz Embedded Mode Routing Topology.......................................................................64
34 PCI 33 MHz Mixed Mode Routing Topology ..............................................................................65
35 100 ohm Differential Trace .........................................................................................................71
36 Source Synchronous Length Matching.......................................................................................73
37 Data Group Length Matching .....................................................................................................73
38 DIMM DQ/DQS Topology...........................................................................................................79
39 DIMM DQ/DQS Split Termination Topology...............................................................................80
40 DDR 333 Registered DIMM Clock Topology..............................................................................83
41 DDR 333 Unbuffered DIMM Clock Topology..............................................................................84
42 Trace Length Requirements for Source Clocked Routing..........................................................85
43 DDR 333 DIMM Unbuffered/Registered Address/CMD Topology Lengths................................87
44 Embedded DDR 333 DQ/DQS Topology ...................................................................................91
45 Embedded DDR 333 Buffered Clock Topology..........................................................................92
46 Embedded DDR 333 Unbuffered Clock Topology......................................................................95
47 Embedded DDR 333 Unbuffered ADDR/CMD Topology ...........................................................98
48 Embedded DDR 333 Registered ADDR/CMD Topology..........................................................100

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Intel® 80331 I/O Processor Design Guide
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49 Intel®80331 I/O Processor DDRII 400 DIMM Source Synchronous Routing..........................104
50 DDR II 400 DIMM DQ Topology...............................................................................................106
51 DDR II 400 DIMM DQS Topology.............................................................................................106
52 DDR II 400 DIMM Clock Topology............................................................................................107
53 DDR II 400 DIMM Address/CMD Topology..............................................................................109
54 DDR II 400 DIMM Address/CMD Split Termination Topology..................................................109
55 DDR II 400 Embedded DQ Topology .......................................................................................111
56 DDR II 400 Embedded DQS Topology.....................................................................................112
57 DDR II 400 Embedded Clock Topology....................................................................................115
58 DDR II 400 Embedded Address/Control Topology...................................................................118
59 DDR II 400 Embedded Address/Control Topology With Split Termination...............................119
60 Routing Termination Resistors (top view).................................................................................120
61 DDR VREF Circuit......................................................................................................................121
62 Data Width and Low Order Address Lines ...............................................................................124
63 Four MByte Flash Memory System ..........................................................................................125
64 Peripheral Bus Unlatched Bidirectional Single Load Topology.................................................127
65 Peripheral Bus Latched Bidirectional Single Load Topology....................................................128
66 Peripheral Bus Latched Bidirectional Two Load Topology.......................................................129
67 Power Failure Comparator Circuit ............................................................................................133
68 SCKE Circuit.............................................................................................................................134
69 Intel®IQ80331 Evaluation Platform Board CRB Block Diagram ..............................................137
70 Intel®80331 I/O Processor CRB Form Factor..........................................................................138
71 JTAG Header Pin Out...............................................................................................................140
72 JTAG Signals at Powerup.........................................................................................................141
73 JTAG Signals at Debug Startup................................................................................................141
74 Example Power-Up Circuit for nTRST......................................................................................142

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Intel® 80331 I/O Processor Design Guide
Contents
Tables
1 Terminology and Definitions.......................................................................................................12
2 FC-style, H-PBGA Package Dimensions....................................................................................17
3 Terminations: Pull-up/Pull-down.................................................................................................23
4 Decoupling Recommendations...................................................................................................34
5 Motherboard Stack Up, Stripline and Microstrip.........................................................................37
6 Adapter Card Stack Up, Microstrip and Stripline........................................................................39
7 PCI-X Slot Guidelines.................................................................................................................43
8 PCI-X Clock Layout Requirements Summary ............................................................................46
9 PCI-X 133 MHz Single Slot Routing Recommendations............................................................48
10 Embedded PCI-X 133 MHz Routing Recommendations............................................................49
11 Embedded PCI-X 133 MHz Alternate Topology Routing Recommendations.............................50
12 Embedded and Slot PCI-X 133 MHz Routing Recommendations..............................................51
13 Embedded and Slot PCI-X 133 MHz Routing Recommendations..............................................52
14 PCI-X 100 MHz Slot Topology Routing Recommendations .......................................................53
15 PCI-X 100 MHz Embedded Routing Recommendations............................................................54
16 Combination of Slot and Embedded PCI-X 100 MHz Routing Recommendations ....................55
17 Combination of Slot and Embedded PCI-X 100 MHz Routing 2 Recommendations .................56
18 PCI-X 66 MHz Slot Routing Recommendations.........................................................................57
19 PCI-X 66 MHz Embedded Routing Recommendations..............................................................58
20 PCI-X 66 MHz Mixed Mode Routing Recommendations............................................................59
21 PCI 66 MHz Slot Table...............................................................................................................60
22 PCI 66 MHz Embedded Table....................................................................................................61
23 PCI 66 MHz Mixed Mode Table..................................................................................................62
24 PCI 33 MHz Slot Routing Recommendations.............................................................................63
25 PCI 33 MHz Embedded Routing Recommendations .................................................................64
26 PCI 33 MHz Mixed Mode Routing Recommendations ...............................................................65
27 DDR Bias Voltages.....................................................................................................................67
28 DDR II Bias Voltage....................................................................................................................67
29 Core Speed and Memory Configuration.....................................................................................68
30 Simulated DDR 333 Topologies.................................................................................................69
31 Example Topologies for DDR Trace...........................................................................................71
32 x64 DDR Memory Configuration.................................................................................................72
33 x72 DDR Memory Configuration.................................................................................................72
34 Source Synchronous Termination Requirements.......................................................................73
35 Source Synchronous Routing Recommendations......................................................................74
36 DIMM DQ/DQS Topology Lengths.............................................................................................75
37 Die to Ball Internal Lengths ........................................................................................................75
38 DIMM DQ/DQS Split Termination Topology Lengths .................................................................80
39 DIMM Clocked Signal Group Termination..................................................................................81
40 Clock Signal Group Registered/Unbuffered DIMM Routing Requirements................................82
41 Registered DIMM Clock Topology Lengths................................................................................83
42 DDR 333 Unbuffered DIMM Clock Topology Lengths................................................................84
43 Source Clocked Signal Routing..................................................................................................85
44 Control Signals Routing Guidelines............................................................................................86
45 Control Signal DIMM Topology Lengths.....................................................................................88
46 DDR 333 Embedded Source Synchronous Routing Recommendations....................................89
47 Embedded DDR 333 DQ/DQS Topology Lengths......................................................................91
48 DDR 333 Embedded Registered/Unbuffered Clock Routing Recommendations.......................93

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Intel® 80331 I/O Processor Design Guide
Contents
49 Embedded DDR 333 Buffered Clock Topology Lengths ............................................................94
50 Embedded DDR 333 Unbuffered Clock Topology Lengths........................................................95
51 DDR 333 Embedded Address/Command Routing Recommendations ......................................96
52 Embedded DDR 333 Unbuffered Address/CMD Topology Lengths...........................................98
53 Embedded DDR 333 Registered Address/CMD Topology Lengths...........................................99
54 x64 DDR Memory Configuration...............................................................................................101
55 x72 DDR Memory Configuration...............................................................................................101
56 DDR II Topologies Simulated ...................................................................................................102
57 Example Topology for DDRII Trace Width/Impedance Requirements .....................................103
58 DDRII 400 DIMM Source Synchronous Routing Recommendations........................................105
60 DDR II 400 DIMM DQS Lengths...............................................................................................106
59 DDR II 400 DIMM DQ Lengths.................................................................................................106
61 DDRII 400 DIMM Clock Routing Recommendations................................................................107
62 DDR II 400 DIMM Clock Lengths..............................................................................................107
63 DDRII 400 DIMM Address/Command/Control Routing Recommendation ...............................108
64 DDR II 400 DIMM Address/CMD Lengths................................................................................109
65 DDRII 400 Embedded Source Synchronous Routing Recommendations................................110
66 DDR II 400 Embedded DQ Lengths .........................................................................................111
67 DDR II 400 Embedded DQS Lengths.......................................................................................112
68 DDRII 400 Embedded Clock Routing Recommendations........................................................113
69 DDR II 400 Embedded Clock (PLL) Lengths............................................................................114
70 DDRII 400 Embedded Address/Command/Control Routing Recommendations......................116
71 DDR II 400 Embedded Address/CMD Lengths ........................................................................117
72 Flash Wait State Profile Programming .....................................................................................125
73 Routing Guideline Bidirectional Single Load.............................................................................127
74 Routing Guideline Latched Bidirectional Latch Single Load.....................................................128
75 Routing Guideline Latch Bidirectional Two Loads....................................................................129
76 Intel®80331 I/O Processor Bias Voltages...............................................................................131
77 Four Peaks Customer Reference Board Features ...................................................................138
78 Logic Analyzer Pod 1................................................................................................................143
80 Logic Analyzer Pod 3................................................................................................................144
79 Logic Analyzer Pod 2................................................................................................................144
82 Logic Analyzer Pod 5................................................................................................................145
81 Logic Analyzer Pod 4................................................................................................................145
83 Logic Analyzer Pod 6................................................................................................................146
84 Design References...................................................................................................................147
85 Intel Related Documentation ....................................................................................................147
86 Electronic Information...............................................................................................................148

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Intel® 80331 I/O Processor Design Guide
Contents
Revision History
TaTa
Date Revision Description
March 2005 003 Updated Figure 27, Figure 33, and Figure 49.
October 2004 002
In Chapter 6:
Table 8: added row Preferred Topology: stripline
Table 8: changed Clock Layout Requirements Add-in card
impedance from 60 ohms to 57 ohms.
Changed topology information in Figure 24 and Table 16.
Table 17 Added alternate PCI-X 100MHz Slot and Embedded
Topology Figure 25 and Table 16.
Table 18 Changed Add-in card impedance from 60 ohms +/-
15% to 57 ohms +/- 15%.
In Chapter 7:
DDR 333 Source Synchronous recommendations removed the
requirement for length matching for DQS groups based on
simulations
Removed row in Table 48 “Length Matching Requirements:
between clock groups”. This is required only for unbuffered
clocks and was already mentioned in the previous row.
Table 51: removed row in “Trace Length: 80331 signal Ball to
Series Termination” because the series termination is no
longer needed.
Table 52: Removed Routing Guideline 4 because unbuffered
and registered DIMM’s have the same topology.
Deleted Figure 57 because simulations showed that series
resistors is no longer needed for DDR 333 DIMM control
signals
Table 53: Removed Length Matching within DQS group
recommendation now because length matching will happen
when matching to M_CK.
Changed Embedded DDR 333 DQ/DQS Topology Figure 44
resistor listed as 50 ohms +/- 5% to 51 ohms +/- 5% because
this is a standard value resistor.
In Chapter 9
Removed VCC25/VCC18 from the power up sequence order
and added a note stating that there is no sequence order
requirements for the VCC25 or VCC18 rail.
Other:
Moved the decoupling guidelines from Chapter 3 to Chapter 4.
Removed reference to the Hot Plug controller. This feature is
not part of the 80331 product.
September 2003 001 Initial Release.

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Intel® 80331 I/O Processor Design Guide
Introduction
Introduction 1
1.1 About This Document
This document provides layout information and guidelines for designing platform or add-in board
applications with the Intel®80331 I/O processor (80331), which is ARM* architecture compliant.
It is recommended that this document be used as a guideline. Intel recommends employing
best-known design practices with board level simulation, signal integrity testing and validation for
a robust design.
Designers please note that this guide focuses upon specific design considerations for the 80331 and
is not intended to be an all-inclusive list of all good design practices. Use this guide as a starting
point and use empirical data to optimize your particular design.
Intel Corporation assumes no responsibility for any errors which may appear in this document nor
does it make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice. In
particular, descriptions of features, timings, packaging, and pin-outs does not imply a commitment
to implement them. In fact, this specification does not imply a commitment by Intel to design,
manufacture, or sell the product described herein.

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Intel® 80331 I/O Processor Design Guide
Introduction
1.1.1 Terminology and Definitions
Table 1. Terminology and Definitions (Sheet 1 of 2)
Term Definition
80331 Intel®80331 I/O processor
Stripline
Stripline in a PCB is composed of the
conductor inserted in a dielectric with GND
planes to the top and bottom.
NOTE: An easy way to distinguish stripline
from microstrip is that you need to
strip away layers of the board to view
the trace on stripline.
Microstrip Microstrip in a PCB is composed of the conductor on the top layer above the dielectric
with a ground plane below
Prepreg Material used for the lamination process of manufacturing PCBs. It consists of a layer of epoxy material that is placed between two cores. This layer melts into epoxy when heated and
forms around adjacent traces.
Core Material used for the lamination process of manufacturing PCBs. This material is two sided
laminate with copper on each side. The core is an internal layer that is etched.
PCB
Printed circuit board.
Example manufacturing process consists of
the following steps:
• Consists of alternating layers of core and
prepreg stacked
• The finished PCB is heated and cured.
• The via holes are drilled
• Plating covers holes and outer surfaces
• Etching removes unwanted copper
• Board is tinned, coated with solder mask
and silk screened
DDR Double Data Rate Synchronous DRAM. Data is clocked on both rising and falling edges of the
clock.
DDR II
DDR II is backward compatible with DDR I. However, it has an increased DDR data rate to
3.2 GBytes/sec with a clock rate of 200 MHz for multiple DIMM configurations. It allows data
rate of 6.4 Gbytes/sec with a clock rate of 400 MHz for a single DIMM point to point
configuration.
DIMM Dual Inline Memory Module
Source
Synchronous
DDR
• For reads data leaves the DDR or memory controller with a data strobe. The memory
controller delays the data strobe internally to line it up with the data valid window.
• For writes the memory controller places the data strobe in the middle of the data valid
window to ensure that the correct data gets clocked into the DRAM.
SSTL_2 Series Stub Terminated Logic for 2.5 V
JEDEC Provides standards for the semiconductor industry.
DLL Delay Lock Loop - refers to the DDR feature used to provide appropriate strobe delay to clock
in data.
Layer 1: copper
Prepreg
Layer 2: GND
Core
Layer 3: VCC
Layer 4: copper
Prepreg
Example of a Four-Layer Stack

13
Intel® 80331 I/O Processor Design Guide
Introduction
Aggressor
A network that transmits a coupled signal to another network is aggressor network.
Victim A network that receives a coupled cross-talk signal from another network is a victim network.
Network The trace of a PCB that completes an electrical connection between two or more components.
Stub Branch from a trunk terminating at the pad of an agent.
ISI
Intersymbol Interference (ISI). This occurs when a transition that has not been completely
dissipated, interferes with a signal being transmitted down a transmission line. ISI can impact
both the timing and signal integrity. It is dependent on frequency, time delay of the line and the
refection coefficient at the driver and receiver. Examples of ISI patterns that could be used in
testing at the maximum allowable frequencies are the sequences shown below:
0101010101010101
0011001100110011
0001110001110001111
CRB Customer Reference Board
PC1600 JEDEC Names for DDR based on peak data rates.
PC1600= clock of 100 MHz * 2 data words/clock * 8 bytes = 1600 MB/sec
PC2100 JEDEC Names for DDR based on peak data rates.
PC2100= clock of 133 MHz * 2 data words/clock * 8 bytes = 2128 MB/sec
PC2700 JEDEC Names for DDR II based on peak data rates.
PC2700= clock of 167 MHz * 2 data words/clock * 8 bytes = 2672 MB/sec
PC3200 JEDEC Names for DDR II based on peak data rates.
PC3200= clock of 200 MHz * 2 data words/clock * 8 bytes = 3200 MB/sec
Downstream At or toward the Primary PCI interface from the Secondary PCI interface
Local memory Memory subsystem on the Intel XScale®core DDR SDRAM or Peripheral Bus Interface
busses.
DWORD 32-bit data word.
Local bus 80331 Internal Bus.
Outbound At or toward the PCI interface of the 80331 ATU from the Internal Bus.
Inbound At or toward the Internal Bus of the 80331 from the PCI interface of the ATU.
Local processor Intel XScale®core within the 80331.
Core processor Intel XScale®core within the 80331.
Flip Chip FC-BGA (flip chip-ball grid array) chip packages are designed with core flipped up on the back of
the chip, facing away from the PCB. This allows more efficient cooling of the package.
Mode
Conversion Mode Conversions are due to imperfections on the interconnect which transform differential mode voltage to common mode voltage and common mode voltage to differential voltage.
ROMB Raid on motherboard
ODT On Die Termination - eliminates the need for termination resistors by placing the termination at
the chip.
Table 1. Terminology and Definitions (Sheet 2 of 2)
Term Definition
Aggressor Network
Victim Network
Zo Zo Zo Zo

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Intel® 80331 I/O Processor Design Guide
Introduction
1.1.2 Other Relevant Documents
1. Intel® 80331 I/O Processor Specification Update (273930), Intel Corporation
2. Intel®80331 I/O Processor Datasheet (273943), Intel Corporation
3. Intel®80331 I/O Processor Developer’s Manual (273942), Intel Corporation
4. Intel XScale®80200 Processor based on Intel®Microarchitecture Developer’s Manual
(273411), Intel Corporation
5. PCI Local Bus Specification, Revision 2.3 - PCI Special Interest Group
6. PCI-X Specification, Revision 1.0b - PCI Special Interest Group
7. PCI Bus Power Management Interface Specification, Revision 1.1 - PCI Special Interest
Group
8. IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE JTAG-1149.1-1990)

15
Intel® 80331 I/O Processor Design Guide
Introduction
1.2 About the Intel®80331 I/O Processor
The 80331 is a multi-function device that integrates the Intel XScale®core (ARM* architecture
compliant) with intelligent peripherals and PCI-to-PCI Bridge. The 80331 consolidates the
following into a single system:
•Intel XScale®core
•PCI-to-PCI Bridge supporting PCI-X interfaces on the Primary and Secondary bus.
•Address Translation Unit (PCI-to-Internal Bus Application Bridge) interfaced to the
Secondary Bus
•High-Performance Memory Controller
•Interrupt Controller with up to 13 external interrupt inputs
•Two Direct Memory Access (DMA) Controllers
•Application Accelerator
•Messaging Unit
•Peripheral Bus Interface Unit
•Performance Monitor
•Two I2C Bus Interface Units
•Two 16550 compatible UARTs with flow control (four pins)
•Eight General Purpose Input Output (GPIO) ports
It is an integrated processor that addresses the needs of intelligent I/O applications and helps
reduce intelligent I/O system costs.

16
Intel® 80331 I/O Processor Design Guide
Introduction
Figure 1 provides a block diagram of the 80331.
Figure 1. Intel®80331 I/O Processor Functional Block Diagram
B2472-01
Internal Bus
Primary PCI Bus Secondary PCI Bus
PCI-to-PCI
Bridge
ATU
Message
Unit
2 Channel
DMA
Controller
Interrupt
Controller
&Timers
Application
Accelerator
Arbiter
Intel®XScale™
Core
Bus Interface
Unit
32/64-bit DDR
Interface
Memory
Controller
16-bit
PBI
BRG
UART
Units
GPIO
2 - 1²C
Units

17
Intel® 80331 I/O Processor Design Guide
Package Information
Package Information 2
The 80331 is offered in a Flip Chip Ball Grid Array (FCBGA) package. This is a full-array package
with 829 ball connections. The mechanical dimensions for this package are provided in the figure
below and Table 2. Figure 3 and Figure 4 show the 829 pins of the Flip Chip Ball Grid Array
(FCBGA), mapped by pin function. This diagram is helpful in placing components around the
80331 for the layout of a PCB. To simplify routing and minimize the number of cross traces, keep
this layout in mind when placing components on your board. The signals, by design, are located on
the FCBGA package to simplify signal routing and system implementation.
Table 2. FC-style, H-PBGA Package Dimensions
829-Pin BGA
Symbol Minimum Maximum
A2.392 2.942
A1 0.50 0.70
A3 0.742 0.872
b0.61 Ref.
C1.15 1.37
D37.45 37.55
E37.45 37.55
F1 9.88 Ref.
F2 10.16 Ref.
e1.27 Ref.
S1 0.97 Ref.
S2 0.97 Ref.
NOTE: Measurement in millimeters.

18
Intel® 80331 I/O Processor Design Guide
Package Information
Figure 2. Intel®80331 I/O Processor 829-Ball FCBGA Package Diagram
B1230-03
E
D
F1
F2
Die
S2
S1
Pin #1
Corner øb
e
A3 A
A1 C
Top View Bottom View
Side View
Seating Plane
A
1234
B
C
D
E
F
G
H
J
K
L
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
M
5 6 7 8 9 10111213141516171819 20212223242526272829

19
Intel® 80331 I/O Processor Design Guide
Package Information
Figure 3. Intel®80331 I/O Processor Preliminary Ballout (Top View)
B1758-01
DDR/DDRII/SDRAM
JTAG
GPIO
PBI
VCC/VSS
Secondary
PCI-X Bus Primary PCI-X Bus
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
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H
G
F
E
D
C
B
A
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21
2223242526272829
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21
2223242526272829

20
Intel® 80331 I/O Processor Design Guide
Package Information
Figure 4. Intel®80331 I/O Processor Preliminary Ballout (Bottom View)
B1210-01
DDRII/SDRAM
JTAG GPIO
PBI
VCC/VSS
Primary
PCI-X Bus Secondary
PCI-X Bus
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 101112131415161718192021 22 23 24 25 26 27 28 29
1 2 3 4 5 6 7 8 9 101112131415161718192021 22 23 24 25 26 27 28 29