Intel 500 - DATASHEET REV 003 User manual

Intel® Celeron® Processor 500Δ
Series
Datasheet
For Platforms Based on Mobile Intel® 965 Express Chipset Family
January 2008
Revision 003
Document Number: 317665-003

2Datasheet
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absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future
definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The
information here is subject to change without notice. Do not finalize a design with this information.
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Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
ΔIntel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor
family, not across different processor families. See http://www.intel.com/products/processor_number for details.
Φ64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device
drivers and applications enabled for Intel® 64 architecture. Performance will vary depending on your hardware and software
configurations. Consult with your system vendor for more information.
Intel, Celeron, Pentium, Intel Core, Intel Core 2, MMX and the Intel logo are trademarks or registered trademarks of Intel
Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2007, Intel Corporation. All rights reserved.

Datasheet 3
Contents
1Introduction..............................................................................................................7
1.1 Terminology .......................................................................................................8
1.2 References .........................................................................................................9
2 Low Power Features ................................................................................................11
2.1 Clock Control and Low Power States .................................................................... 11
2.1.1 Core Low-Power States ........................................................................... 12
2.1.1.1 C0 State..................................................................................12
2.1.1.2 C1/AutoHALT Powerdown State ..................................................12
2.1.1.3 C1/MWAIT Powerdown State ...................................................... 13
2.1.1.4 Core C2 State...........................................................................13
2.1.1.5 Core C3 State...........................................................................13
2.1.2 Package Low-Power States ......................................................................13
2.1.2.1 Normal State............................................................................ 13
2.1.2.2 Stop-Grant State ...................................................................... 13
2.1.2.3 Stop Grant Snoop State.............................................................14
2.1.2.4 Sleep State.............................................................................. 14
2.1.2.5 Deep Sleep State......................................................................15
2.2 Low-Power FSB Features....................................................................................15
2.3 Processor Power Status Indicator (PSI#) Signal..................................................... 15
3 Electrical Specifications...........................................................................................17
3.1 Power and Ground Pins ...................................................................................... 17
3.2 FSB Clock (BCLK[1:0]) and Processor Clocking......................................................17
3.3 Voltage Identification.........................................................................................17
3.4 Catastrophic Thermal Protection..........................................................................21
3.5 Reserved and Unused Pins..................................................................................21
3.6 FSB Frequency Select Signals (BSEL[2:0])............................................................22
3.7 FSB Signal Groups............................................................................................. 22
3.8 CMOS Signals ...................................................................................................23
3.9 Maximum Ratings..............................................................................................23
3.10 Processor DC Specifications ................................................................................24
4 Package Mechanical Specifications and Pin Information ..........................................29
4.1 Package Mechanical Specifications....................................................................... 29
4.2 Processor Pinout and Pin List .............................................................................. 34
4.3 Alphabetical Signals Reference........................................................................... 53
5 Thermal Specifications ............................................................................................61
5.1 Thermal Diode .................................................................................................. 62
5.1.1 Thermal Diode Offset..............................................................................62
5.2 Intel® Thermal Monitor...................................................................................... 64
5.3 Digital Thermal Sensor.......................................................................................66
5.4 Out of Specification Detection .............................................................................66
5.5 PROCHOT# Signal Pin........................................................................................67

4Datasheet
Figures
1 Package-Level Low-Power States................................................................................11
2 Core Low-Power States .............................................................................................12
3 Active VCC and ICC Loadline Standard Voltage.............................................................26
4 1-MB Fused Micro-FCPGA Processor Package Drawing (1 of 2)........................................30
5 1-MB Fused Micro-FCPGA Processor Package Drawing (2 of 2)........................................31
6 1-MB Micro-FCPGA Processor Package Drawing (1 of 2).................................................32
7 1-MB Micro-FCPGA Processor Package Drawing (2 of 2).................................................33
Tables
1 Coordination of Core-Level Low-Power States at the Package Level .................................11
2 Voltage Identification Definition..................................................................................18
3 BSEL[2:0] Encoding for BCLK Frequency......................................................................22
4 FSB Pin Groups ........................................................................................................22
5 Processor Absolute Maximum Ratings..........................................................................24
6 DC Voltage and Current Specifications.........................................................................24
7 FSB Differential BCLK Specifications............................................................................26
8 AGTL+ Signal Group DC Specifications ........................................................................27
9 CMOS Signal Group DC Specifications..........................................................................28
10 Open Drain Signal Group DC Specifications ..................................................................28
11 The Coordinates of the Processor Pins as Viewed from the Top of the Package
(Sheet 1 of 2)..........................................................................................................34
12 The Coordinates of the Processor Pins as Viewed from the Top of the Package
(Sheet 2 of 2)..........................................................................................................35
13 Pin Listing by Pin Name.............................................................................................37
14 Pin Listing by Pin Number..........................................................................................44
15 Signal Description.....................................................................................................53
16 Standard Voltage Power Specifications ........................................................................61
17 Thermal Diode ntrim and Diode Correction Toffset ........................................................63
18 Thermal Diode Interface............................................................................................63
19 Thermal Diode Parameters using Diode Mode ...............................................................63
20 Thermal Diode Parameters using Transistor Model ........................................................64

Datasheet 5
Revision History
§
Document
Number Revision Number Description Date
317666 -001 Initial Release June 2007
317666 -002 Corrected Figures 4, 5, 6, & 7 November 2007
317665 -003 Added the Intel Celeron processor 560 January 2008

6Datasheet

Datasheet 7
Introduction
1 Introduction
This document covers the Intel® Celeron® processor 500 series for platforms based on
Mobile Intel® 965 Express Chipset family. It is based on the new Intel® Core™
microarchitecture.
In this document the Celeron processor 500 series is referred to as the processor.
The following list provides some of the key features of this processor:
•Singlecore
• On-die, primary 32-KB instruction cache and 32-KB write-back data cache
• On-die, 1-MB second level shared cache with advanced transfer cache architecture
• 533-MHz source-synchronous front side bus (FSB)
• Supports Intel® architecture with dynamic execution
• Data prefetch logic
• Micro-FCPGA packaging technology
• MMX™ technology, Streaming SIMD Extensions (SSE), Streaming SIMD Extensions
2 (SSE2), Streaming SIMD Extensions 3 (SSE3), and Supplemental Streaming
SIMD Extensions 3 (SSSE 3)
• Digital Thermal Sensor (DTS)
• Execute Disable Bit support for enhanced security
• Intel® 64 architecture (formerly Intel® EM64T)Φ
• Architectural and performance enhancements of the Core microarchitecture.
Note: Unless specified otherwise, all references to the processor in this document are
references to the Celeron processor 500 series with a 533-MHz FSB on Mobile Intel 965
Express Chipset family-based systems.

Introduction
8Datasheet
1.1 Terminology
Term Definition
#
A “#” symbol after a signal name refers to an active low signal, indicating a
signal is in the active state when driven to a low level. For example, when
RESET# is low, a reset has been requested. Conversely, when NMI is high,
a nonmaskable interrupt has occurred. In the case of signals where the
name does not imply an active state but describes part of a binary
sequence (such as address or data), the “#” symbol implies that the signal
is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]#
= “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).
XXXX means that the specification or value is yet to be determined.
AGTL+ Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+
signaling technology on some Intel processors.
Front Side Bus
(FSB) Refers to the interface between the processor and system core logic (also known as the chipset components).
Intel® 64
Technology 64-bit memory extensions to the IA-32 architecture.
Processor Core Processor core die with integrated L1 and L2 cache. All AC timing and
signal integrity specifications are at the pads of the processor core.
Storage
Conditions
Refers to a non-operational state. The processor may be installed in a
platform, in a tray, or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor lands should not be
connected to any supply voltages, have any I/Os biased or receive any
clocks. Upon exposure to “free air” (unsealed packaging or a device
removed from packaging material) the processor must be handled in
accordance with moisture sensitivity labeling (MSL) as indicated on the
packaging material.
VCC The processor core power supply.
VSS The processor ground.

Datasheet 9
Introduction
1.2 References
Material and concepts in the following documents may be beneficial when reading this
document.
§
Document Document
Number1
Intel® Celeron® M 500 Series Processor Specification Update 317667
Mobile Intel® 965 Express Chipset Family Datasheet 316273
Mobile Intel® 965 Express Chipset Family Specification Update 316274
Intel® I/O Controller Hub 8(ICH8) Family Datasheet 313056
Intel® I/O Controller Hub 8(ICH8) Family Specification Update 313057
Intel® 64 and IA-32 Intel® Architectures Software Developer's Manual
Volume 1: Basic Architecture 253665
Volume 2A: Instruction Set Reference, A-M 253666
Volume 2B: Instruction Set Reference, N-Z 253667
Volume 3A: System Programming Guide, Part 1 253668
Volume 3B: System Programming Guide, Part 2 253669

Introduction
10 Datasheet

Datasheet 11
Low Power Features
2 Low Power Features
2.1 Clock Control and Low Power States
The processor supports the C1/AutoHALT, C1/MWAIT, C2, and C3 core low-power
states, along with their corresponding package-level states for power management.
These package states include Normal, Stop Grant, Stop Grant Snoop, Sleep, and Deep
Sleep. The processor’s central power management logic enters a package low-power
state by initiating a P_LVLx (P_LVL2, P_LVL3) I/O read to the Intel 965 Express Chipset
family. Figure 1 shows the package-level low-power states and Figure 2 shows the core
low-power states. Refer to Table 1 for a mapping of core low-power states to package
low-power states.
The processor implements two software interfaces for requesting low-power states:
MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI P_BLK
register block mapped in the processor’s I/O address space. The P_LVLx I/O reads are
converted to equivalent MWAIT C-state requests inside the processor and do not
directly result in I/O reads on the processor FSB. The monitor address does not need to
be setup before using the P_LVLx I/O read interface. The sub-state hints used for each
P_LVLx read can be configured through the IA32_MISC_ENABLES Model Specific
Register (MSR).
If the processor encounters a chipset break event while STPCLK# is asserted, it asserts
the PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to
system logic that the processor should return to the Normal state.
NOTE: AutoHALT or MWAIT/C1
Table 1. Coordination of Core-Level Low-Power States at the Package Level
Core States Package States
C0 Normal
C1(1) Normal
C2 Stop Grant
C3 Deep Sleep
Figure 1. Package-Level Low-Power States
Stop
Grant
Snoop
Normal Stop
Grant Deep Sleep
STPCLK# asserted
Snoop
serviced Snoop occurs
Sleep
SLP# asserted
SLP# de-asserted
DPSLP# asserted
DPSLP# de-asserted
STPCLK# de-asserted

Low Power Features
12 Datasheet
2.1.1 Core Low-Power States
2.1.1.1 C0 State
This is the normal operating state of the processor.
2.1.1.2 C1/AutoHALT Powerdown State
C1/AutoHALT is a low-power state entered when the processor core executes the HALT
instruction. The processor core transitions to the C0 state upon the occurrence of
SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# causes the
processor to immediately initialize itself.
A System Management Interrupt (SMI) A System Management Interrupt (SMI) handler
returns execution to either Normal state or the C1/AutoHALT Powerdown state. See the
Intel®64 and IA-32 Intel®Architecture Software Developer's Manual, Volume 3A/3B:
System Programmer's Guide for more information.
The system can generate a STPCLK# while the processor is in the C1/AutoHALT
Powerdown state. When the system deasserts the STPCLK# interrupt, the processor
returns execution to the HALT state.
The processor in C1/AutoHALT powerdown state process only the bus snoops. The
processor enters a snoopable sub-state (not shown in Figure 2) to process the snoop
and then return to the C1/AutoHALT Powerdown state.
Figure 2. Core Low-Power States
C2†
C0
Stop
Grant
Core state
break
P_LVL2 or
MWAIT(C2)
C3†
Core
state
break
P_LVL3 or
MWAIT(C3)
C1/
MWAIT Core state
break
MWAIT(C1)
C1/
Auto
Halt
Halt break
HLT instruction
STPCLK#
de-asserted
STPCLK#
asserted
STPCLK#
de-asserted
STPCLK#
asserted
STPCLK#
de-asserted
STPCLK#
asserted
halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt
core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted)
† — STPCLK# assertion and de-assertion have no affect if a core is in C2, or C3.

Datasheet 13
Low Power Features
2.1.1.3 C1/MWAIT Powerdown State
C1/MWAIT is a low-power state entered when the processor core executes the MWAIT
instruction. Processor behavior in the C1/MWAIT state is identical to the C1/AutoHALT
state except that there is an additional event that can cause the processor core to
return to the C0 state: the Monitor event. See the Intel®64 and IA-32 Intel®
Architecture Software Developer's Manual, Volume 2A/2B: Instruction Set Reference
for more information.
2.1.1.4 Core C2 State
The core of the processor can enter the C2 state by initiating a P_LVL2 I/O read to the
P_BLK or an MWAIT(C2) instruction, but the processor does not issue a Stop Grant
Acknowledge special bus cycle unless the STPCLK# pin is also asserted.
The processor in C2 state processes only the bus snoops. The processor enters a
snoopable sub-state (not shown in Figure 2) to process the snoop and then return to
the C2 state.
2.1.1.5 Core C3 State
Core C3 state is a very low-power state the processor core can enter while maintaining
context. The core of the processor can enter the C3 state by initiating a P_LVL3 I/O
read to the P_BLK or an MWAIT(C3) instruction. Before entering the C3 state, the
processor core flushes the contents of its L1 cache into the processor’s L2 cache.
Except for the caches, the processor core maintains all its architectural state in the C3
state. The Monitor remains armed if it is configured. All of the clocks in the processor
core are stopped in the C3 state.
Because the core’s caches are flushed, the processor keeps the core in the C3 state
when the processor detects a snoop on the FSB. The processor core transitions to the
C0 state upon the occurrence of a Monitor event, SMI#, INIT#, LINT[1:0] (NMI, INTR),
or FSB interrupt message. RESET# causes the processor core to immediately initialize
itself.
2.1.2 Package Low-Power States
Package level low-power states are applicable to the processor.
2.1.2.1 Normal State
This is the normal operating state for the processor. The processor enters the Normal
state when the core is in the C0, C1/AutoHALT, or C1/MWAIT state.
2.1.2.2 Stop-Grant State
When the STPCLK# pin is asserted the core of the processor enters the Stop-Grant
state within 20 bus clocks after the response phase of the processor-issued Stop Grant
Acknowledge special bus cycle. When the STPCLK# pin is deasserted the core returns
to the previous core low-power state.
Since the AGTL+ signal pins receive power from the FSB, these pins should not be
driven (allowing the level to return to VCCP) for minimum power drawn by the
termination resistors in this state. In addition, all other input pins on the FSB should be
driven to the inactive state.
RESET# causes the processor to immediately initialize itself, but the processor stays in
Stop-Grant state. When RESET# is asserted by the system the STPCLK#, SLP#, and
DPSLP# pins must be deasserted more than 480 µs prior to RESET# deassertion (AC

Low Power Features
14 Datasheet
Specification T45). When re-entering the Stop-Grant state from the Sleep state,
STPCLK# should be deasserted ten or more bus clocks after the deassertion of SLP#
(AC Specification T75).
While in the Stop-Grant state, the processor services snoops and latch interrupts
delivered on the FSB. The processor latches SMI#, INIT# and LINT[1:0] interrupts and
services only upon return to the Normal state.
The PBE# signal may be driven when the processor is in Stop-Grant state. PBE# is
asserted if there is any pending interrupt or monitor event latched within the processor.
Pending interrupts that are blocked by the EFLAGS.IF bit being clear still cause
assertion of PBE#. Assertion of PBE# indicates to system logic that the processor
should return to the Normal state.
A transition to the Stop Grant Snoop state occurs when the processor detects a snoop
on the FSB (see Section 2.1.2.3). A transition to the Sleep state (see Section 2.1.2.4)
occurs with the assertion of the SLP# signal.
2.1.2.3 Stop Grant Snoop State
The processor responds to snoop or interrupt transactions on the FSB while in Stop-
Grant state by entering the Stop-Grant Snoop state. The processor stays in this state
until the snoop on the FSB has been serviced (whether by the processor or another
agent on the FSB) or the interrupt has been latched. The processor returns to the Stop-
Grant state once the snoop has been serviced or the interrupt has been latched.
2.1.2.4 Sleep State
The Sleep state is a low-power state in which the processor maintains its context,
maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is
entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP#
pin should only be asserted when the processor is in the Stop-Grant state. SLP#
assertions while the processor is not in the Stop-Grant state is out of specification and
may result in unapproved operation.
In the Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions or assertions of signals (with the exception of
SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep
state. Snoop events that occur while in Sleep state or during a transition into or out of
Sleep state causes unpredictable behavior. Any transition on an input signal before the
processor has returned to the Stop-Grant state results in unpredictable behavior.
If RESET# is driven active while the processor is in the Sleep state, and held active as
specified in the RESET# pin specification, then the processor resets itself, ignoring the
transition through Stop-Grant state. If RESET# is driven active while the processor is in
the Sleep state, the SLP# and STPCLK# signals should be deasserted immediately after
RESET# is asserted to ensure the processor correctly executes the Reset sequence.
While in the Sleep state, the processor is capable of entering an even lower power
state, the Deep Sleep state, by asserting the DPSLP# pin. (See Section 2.1.2.5.) While
the processor is in the Sleep state, the SLP# pin must be deasserted if another
asynchronous FSB event needs to occur.

Datasheet 15
Low Power Features
2.1.2.5 Deep Sleep State
Deep Sleep state is a very low-power state the processor can enter while maintaining
context. Deep Sleep state is entered by asserting the DPSLP# pin while in the Sleep
state. BCLK may be stopped during the Deep Sleep state for additional platform level
power savings. BCLK stop/restart timings on appropriate chipset based platforms with
the CK505 clock chip are as follows:
• Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs of
DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.
• Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels
within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK
periods.
To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be re-
started after DPSLP# deassertion as described above. A period of 15 microseconds (to
allow for PLL stabilization) must occur before the processor can be considered to be in
the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter
the Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop
transactions or latching interrupt signals. No transitions of signals are allowed on the
FSB while the processor is in Deep Sleep state. Any transition on an input signal before
the processor has returned to Stop-Grant state results in unpredictable behavior.
2.2 Low-Power FSB Features
The processor incorporates FSB low-power enhancements:
• Dynamic On Die Termination disabling
•LowV
CCP (I/O termination voltage)
The On Die Termination on the processor FSB buffers is disabled when the signals are
driven low, resulting in power savings. The low I/O termination voltage is on a
dedicated voltage plane independent of the core voltage, enabling low I/O switching
power at all times.
2.3 Processor Power Status Indicator (PSI#) Signal
The PSI# signal is asserted when the processor is in a reduced power consumption
state. PSI# can be used to improve light load efficiency of the voltage regulator,
resulting in platform power savings and extended battery life. The algorithm that the
processor uses for determining when to assert PSI# is different from the algorithm
used in previous processors.
§

Low Power Features
16 Datasheet

Datasheet 17
Electrical Specifications
3 Electrical Specifications
3.1 Power and Ground Pins
For clean, on-chip power distribution, the processor has many VCC (power) and VSS
(ground) inputs. All power pins must be connected to VCC power planes while all VSS
pins must be connected to system ground planes. Use of multiple power and ground
planes is recommended to reduce I*R drop. Please refer to the platform design guides
for more details. The processor VCC pins must be supplied the voltage determined by
the VID (Voltage ID) pins.
3.2 FSB Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous generation processors, the processor core frequency is a
multiple of the BCLK[1:0] frequency.
3.3 Voltage Identification
The processor uses seven voltage identification pins, VID[6:0], to support automatic
selection of power supply voltages. The VID pins for the processor are CMOS outputs
driven by the processor VID circuitry. Table 2 specifies the voltage level corresponding
to the state of VID[6:0]. A 1 in this refers to a high-voltage level and a 0 refers to low-
voltage level.

Electrical Specifications
18 Datasheet
Table 2. Voltage Identification Definition (Sheet 1 of 4)
VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V)
00 000 0 01.5000
00 000 0 11.4875
00 000 1 01.4750
00 000 1 11.4625
00 001 0 01.4500
00 001 0 11.4375
00 001 1 01.4250
00 001 1 11.4125
00 010 0 01.4000
00 010 0 11.3875
00 010 1 01.3750
00 010 1 11.3625
00 011 0 01.3500
00 011 0 11.3375
00 011 1 01.3250
00 011 1 11.3125
00 100 0 01.3000
00 100 0 11.2875
00 100 1 01.2750
00 100 1 11.2625
00 101 0 01.2500
00 101 0 11.2375
00 101 1 01.2250
00 101 1 11.2125
00 110 0 01.2000
00 110 0 11.1875
00 110 1 01.1750
00 110 1 11.1625
00 111 0 01.1500
00 111 0 11.1375
00 111 1 01.1250
00 111 1 11.1125
01 000 0 01.1000
01 000 0 11.0875
01 000 1 01.0750
01 000 1 11.0625
01 001 0 01.0500

Datasheet 19
Electrical Specifications
0 1 0 0 1 0 1 1.0375
0 1 0 0 1 1 0 1.0250
0 1 0 0 1 1 1 1.0125
0 1 0 1 0 0 0 1.0000
0 1 0 1 0 0 1 0.9875
0 1 0 1 0 1 0 0.9750
0 1 0 1 0 1 1 0.9625
0 1 0 1 1 0 0 0.9500
0 1 0 1 1 0 1 0.9375
0 1 0 1 1 1 0 0.9250
0 1 0 1 1 1 1 0.9125
0 1 1 0 0 0 0 0.9000
0 1 1 0 0 0 1 0.8875
0 1 1 0 0 1 0 0.8750
0 1 1 0 0 1 1 0.8625
0 1 1 0 1 0 0 0.8500
0 1 1 0 1 0 1 0.8375
0 1 1 0 1 1 0 0.8250
0 1 1 0 1 1 1 0.8125
0 1 1 1 0 0 0 0.8000
0 1 1 1 0 0 1 0.7875
0 1 1 1 0 1 0 0.7750
0 1 1 1 0 1 1 0.7625
0 1 1 1 1 0 0 0.7500
0 1 1 1 1 0 1 0.7375
0 1 1 1 1 1 0 0.7250
0 1 1 1 1 1 1 0.7125
1 0 0 0 0 0 0 0.7000
1 0 0 0 0 0 1 0.6875
1 0 0 0 0 1 0 0.6750
1 0 0 0 0 1 1 0.6625
1 0 0 0 1 0 0 0.6500
1 0 0 0 1 0 1 0.6375
1 0 0 0 1 1 0 0.6250
1 0 0 0 1 1 1 0.6125
1 0 0 1 0 0 0 0.6000
1 0 0 1 0 0 1 0.5875
1 0 0 1 0 1 0 0.5750
Table 2. Voltage Identification Definition (Sheet 2 of 4)
VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V)

Electrical Specifications
20 Datasheet
10 010 1 10.5625
10 011 0 00.5500
10 011 0 10.5375
10 011 1 00.5250
10 011 1 10.5125
10 100 0 00.5000
10 100 0 10.4875
10 100 1 00.4750
10 100 1 10.4625
10 101 0 00.4500
10 101 0 10.4375
10 101 1 00.4250
10 101 1 10.4125
10 110 0 00.4000
10 110 0 10.3875
10 110 1 00.3750
10 110 1 10.3625
10 111 0 00.3500
10 111 0 10.3375
10 111 1 00.3250
10 111 1 10.3125
11 000 0 00.3000
11 000 0 10.2875
11 000 1 00.2750
11 000 1 10.2625
11 001 0 00.2500
11 001 0 10.2375
11 001 1 00.2250
11 001 1 10.2125
11 010 0 00.2000
11 010 0 10.1875
11 010 1 00.1750
11 010 1 10.1625
11 011 0 00.1500
11 011 0 10.1375
11 011 1 00.1250
11 011 1 10.1125
11 100 0 00.1000
Table 2. Voltage Identification Definition (Sheet 3 of 4)
VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V)