Intel T8300 - Core 2 Duo 2.4GHz 800MHz 3MB Socket P Mobile... Operator's manual

Intel®Core™2 Extreme Quad-Core Mobile
Processor,
Intel®Core™2 Quad Mobile Processor,
Intel®Core™2 Extreme Mobile Processor,
Intel®Core™2 Duo Mobile Processor,
Intel®Core™2 Solo Mobile Processor and
Intel®Celeron®Processor
on 45-nm Process
Specification Update
December 2011
Document Number: 320121-008

2Specification Update
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BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED
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DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR
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COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
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APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH
MAY OCCUR.
Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the
absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition
and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information
here is subject to change without notice. Do not finalize a design with this information.
The products described in this document may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Intel® processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family,
not across different processor families. See www.intel.com/products/processor_number/ for details.
45nm products are manufactured on a lead-free process. Lead-free per EU RoHS directive July, 2006. Some E.U. RoHS exemptions
may apply to other components used in the product package. Residual amounts of halogens are below November, 2007 proposed
IPC/JEDEC J-STD-709 standards.
Intel® Active Management Technology requires the platform to have an Intel® AMT-enabled chipset, network hardware and
software, connection with a power source and a network connection.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Intel, Intel Core, Intel Centrino, Intel SpeedStep, Intel386, Intel486, Pentium, Pentium Pro, Pentium 4, MMX, and the Intel logo are
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*Other names and brands may be claimed as the property of others.
Copyright © 2007 - 2011, Intel Corporation. All rights reserved.

Specification Update 3
Contents
Preface..................................................................................................................................5
Identification Information ........................................................................................................7
Summary Tables of Changes ..................................................................................................13
Errata .................................................................................................................................21
Specification Changes ...........................................................................................................53
Specification Clarifications .....................................................................................................54
Documentation Changes ........................................................................................................56

4Specification Update
Revision History
Document
Number
Revision
Version
Description
Date
320121
001
1.0
Initial release
July 2008
320121
002
1.0
Updated Title
Updated Identification Information
Updated Affected Documents
Added Erratum AZ62, AZ63, AZ64,AZ65,
AZ66
August 2008
320121
003
1.0
Added Erratum AZ66-74
October 2008
320121
004
1.0
Added Erratum AZ75
Added Specification Clarification AZ2
November 2008
320121
005
1.0
Table 1 added new skus and updated E and
R step information
Errata table added R step information
March 2009
320121
006
1.0
S-SPEC updated for new E and R step in
Table 1
April 2009
320121
007
1.0
Added Erratum AZ76
December 2010
320121
008
1.0
Added Erratum AZ77
December 2011

Preface
Specification Update 5
Preface
This document is an update to the specifications contained in the documents listed in the
following Affected Documents/Related Documents table. It is a compilation of device and
document errata, and specification clarifications and changes. This document is intended
for hardware system manufacturers and for software developers of applications,
operating system, and tools.
Information types defined in the Nomenclature section of this document are consolidated
into this update document and are no longer published in other documents. This
document may also contain information that has not been previously published.
Affected Documents
Document Title
Document
Number/Location
Intel® Core™2 Duo Processors and Intel® Core™2 Extreme
Processors on 45-nm Process for Platforms based on Mobile Intel®
965 Express Chipset family Datasheet
316745
Intel® Core™2 Extreme Quad-Core Mobile Processor, Intel® Core™2
Quad Mobile Processor, Intel® Core™2 Extreme Mobile Processor,
Intel® Core™2 Duo Mobile Processor, Intel® Core™2 Solo Mobile
Processor and Intel® Celeron® Processor on 45-nm Process for
Platforms based on Mobile Intel® 4 Series Express Chipset family
Datasheet
320120
Intel® Core™2 Extreme Quad-Core Processor Processors and Intel®
Core™2 Quad Processor on 45-nm Process for Platforms based on
Mobile Intel® 4 Series Express Chipset family Datasheet
320390
Intel® Celeron Processor Low Voltage and Ultra Low Voltage o 700
Series for Platforms based on Mobile Intel® GS45 Express Chipset
320389
Related Documents
Document Title
Document
Number/Location
Intel® 64 and IA-32 Architecture Software Developer's Manual
Documentation Changes
252046
Intel® 64 and IA-32 Architecture Software Developer’s Manual,
Volume 1: Basic Architecture
253665
Intel® 64 and IA-32 Architecture Software Developer’s Manual,
Volume 2A: Instruction Set Reference, A-M
253666
Intel® 64 and IA-32 Architecture Software Developer’s Manual,
Volume 2B: Instruction Set Reference, N-Z
253667
Intel® 64 and IA-32 Architecture Software Developer’s Manual,
253668

Preface
6Specification Update
Document Title
Document
Number/Location
Volume 3A: System Programming Guide
Intel® 64 and IA-32 Architecture Software Developer’s Manual,
Volume 3B: System Programming Guide
253669
IA-32 Intel® Architecture Optimization Reference Manual
248966
Intel Processor Identification and the CPUID Instruction Application
Note (AP-485)
241618
Intel® 64 and IA-32 Architectures Application Note TLBs, Paging-
Structure Caches, and Their Invalidation
317080
NOTE: Contact your Intel representative for the latest revision.
Nomenclature
Errata are design defects or errors. These may cause the processor behavior to deviate
from published specifications. Hardware and software designed to be used with any given
stepping must assume that all errata documented for that stepping are present on all
devices.
S-Spec Number is a five-digit code used to identify products. Products are differentiated
by their unique characteristics, e.g., core speed, L2 cache size, package type, etc. as
described in the processor identification information table. Read all notes associated with
each S-Spec number.
Specification Changes are modifications to the current published specifications. These
changes will be incorporated in any new release of the specification.
Specification Clarifications describe a specification in greater detail or further highlight
a specification‟s impact to a complex design situation. These clarifications will be
incorporated in any new release of the specification.
Documentation Changes include typos, errors, or omissions from the current published
specifications. These will be incorporated in any new release of the specification.
Note: Errata remain in the specification update throughout the product‟s lifecycle, or until a
particular stepping is no longer commercially available. Under these circumstances,
errata removed from the specification update are archived and available upon request.
Specification changes, specification clarifications and documentation changes are
removed from the specification update when the appropriate changes are made to the
appropriate product specification or user documentation (datasheets, manuals, etc.).

Identification Information
Specification Update 7
Identification Information
Component Identification via Programming Interface
Intel® Core™2 Extreme Quad-Core Mobile Processor, Intel® Core™2 Quad Mobile
Processor, Intel® Core™2 Extreme Mobile Processor, Intel® Core™2 Duo Mobile
Processor, Intel® Core™2 Solo Mobile Processor and Intel® Celeron® Processor on 45-
nm Process stepping can be identified by the following register contents:
Reserved
Extended
Family1
Extended
Model2
Reserved
Processor
Type3
Family
Code4
Model
Number5
Stepping
ID6
31:28
27:20
19:16
15:14
13:12
11:8
7:4
3:0
0000000b
0001b
00b
0110b
0111b
XXXXb
When EAX is initialized to a value of 1, the CPUID instruction returns the Extended
Family, Extended Model, Type, Family, Model and Stepping value in the EAX register.
Note that the EDX processor signature value after reset is equivalent to the processor
signature output value in the EAX register.
NOTES:
1. The Extended Family, bits [27:20] are used in conjunction with the Family Code, specified in
bits [11:8], to indicate whether the processor belongs to the Intel386®, Intel486®,
Pentium®, Pentium Pro, Pentium 4, or Intel Core processor family.
2. The Extended Model, bits [19:16] in conjunction with the Model Number, specified in bits
[7:4], are used to identify the model of the processor within the processor‟s family.
3. The Processor Type, specified in bits [13:12] indicates whether the processor is an original
OEM processor, an OverDrive processor, or a dual processor (capable of being used in a dual
processor system).
4. The Family Code corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the
EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the
generation field of the Device ID register accessible through Boundary Scan.
5. The Model Number corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the
EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the
model field of the Device ID register accessible through Boundary Scan.
6. The Stepping ID in bits [3:0] indicates the revision number of that model. See Table 2 for the
processor stepping ID number in the CPUID information.
Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX
registers after the CPUID instruction is executed with a 2 in the EAX register.

Identification Information
8Specification Update
Component Marking Information
The processor stepping can be identified by the following component markings:
Figure 1. Processor S-Spec Top-side Markings (Example)
MARK EXAMPLE: Group
1 Line 1: Unit Identifier Processor #
Group 1 Line 2: FPO SSPEC#
Group 2 Line 1: Frequency/L2 Cache/FSB Speed
Group 2 Line 2: INTEL (m) © ’07

Identification Information
Specification Update 9
Table 1. Processor Identification Information
S-
Spec#
Processor
#
Package
Processor
Stepping
CPUID
Core Frequency
HFM/LFM/ SLFM
(GHz)
FSB Freq.
(MHz)
IDAT
Freq.(GHz)
HFM TDP
(W)
L2
Cache(MB)
Notes
SLAQH
T9500
m-FCPGA
C-0
000010676h
2.6/1.2/0.8
800
2.8
35
6
2,3,4
SLAPW
T9500
m-FCBGA
C-0
000010676h
2.6/1.2/0.8
800
2.8
35
6
2,3,4
SLAQG
T9300
m-FCPGA
C-0
000010676h
2.5/1.2/0.8
800
2.7
35
6
2,3,4
SLAPV
T9300
m-FCBGA
C-0
000010676h
2.5/1.2/0.8
800
2.7
35
6
2,3,4
SLAPU
T8300
m-FCBGA
C-0
000010676h
2.4/1.2/0.8
800
2.6
35
3
2,3,4
SLAUU
T8100
m-FCPGA
C-0
000010676h
2.1/1.2/0.8
800
2.3
35
3
2,3,4
SLAPT
T8100
m-FCBGA
C-0
000010676h
2.1/1.2/0.8
800
2.3
35
3
2,3,4
SLAPA
T8300
m-FCPGA
M-0
000010676h
2.4/1.2/0.8
800
2.6
35
3
2,3,4
SLAPR
T8300
m-FCBGA
M-0
000010676h
2.4/1.2/0.8
800
2.6
35
3
2,3,4
SLAP9
T8100
m-FCPGA
M-0
000010676h
2.1/1.2/0.8
800
2.3
35
3
2,3,4
SLAPS
T8100
m-FCBGA
M-0
000010676h
2.1/1.2/0.8
800
2.3
35
3
2,3,4
SLAVJ
T8100
m-FCPGA
M-0
000010676h
2.1/1.2/0.8
800
2.3
35
3
2,3,4
SLAXG
T8100
m-FCPGA
M-0
000010676h
2.1/1.2/0.8
800
2.3
35
3
2,3,4
SLAZD
T8100
m-FCPGA
M-0
000010676h
2.1/1.2/0.8
800
2.3
35
3
2,3,4,7
SLAYZ
T8100
m-FCPGA
M-0
000010676h
2.1/1.2/0.8
800
2.3
35
3
2,3,4,7
SLAZC
T8300
m-FCPGA
M-0
000010676h
2.4/1.2/0.8
800
2.6
35
3
2,3,4,7
SLAZB
T9300
m-FCPGA
C-0
000010676h
2.5/1.2/0.8
800
2.7
35
6
2,3,4,7
SLAYY
T9300
m-FCPGA
C-0
000010676h
2.5/1.2/0.8
800
2.7
35
6
2,3,4,7
SLAZA
T9500
m-FCPGA
C-0
000010676h
2.6/1.2/0.8
800
2.8
35
6
2,3,4,7
SLAYX
T9500
m-FCPGA
C-0
000010676h
2.6/1.2/0.8
800
2.8
35
6
2,3,4,7
SLAQJ
X9000
m-FCPGA
C-0
000010676h
2.8/1.2/0.8
800
N/A
44
6
1,5,6
SLAZ3
X9000
m-FCPGA
C-0
000010676h
2.8/1.2/0.8
800
N/A
44
6
1,5,6,7
SLB47
T9600
m-FCPGA
C-0
000010676h
2.80/1.6/0.8
1066
2.93
35
6
4,6,10
SLB43
T9600
m-FCBGA
C-0
000010676h
2.80/1.6/0.8
1066
2.93
35
6
4,6,10
SLB46
T9400
m-FCPGA
C-0
000010676h
2.53/1.6/0.8
1066
2.66
35
6
4,6,10
SL3BX
T9400
m-FCBGA
C-0
000010676h
2.53/1.6/0.8
1066
2.66
35
6
4,6,10
SLB4E
P9500
m-FCPGA
C-0
000010676h
2.53/1.6/0.8
1066
2.66
25
6
6,11,12
SL3BW
P9500
m-FCBGA
C-0
000010676h
2.53/1.6/0.8
1066
2.66
25
6
6,11,12
SLB3S
P8600
m-FCPGA
M-0
000010676h
2.40/1.6/0.8
1066
2.53
25
3
6,11,12
SLB4N
P8600
m-FCBGA
M-0
000010676h
2.40/1.6/0.8
1066
2.53
25
3
6,11,12
SLB3R
P8400
m-FCPGA
M-0
000010676h
2.26/1.6/0.8
1066
2.40
25
3
6,11,12

Identification Information
10 Specification Update
S-
Spec#
Processor
#
Package
Processor
Stepping
CPUID
Core Frequency
HFM/LFM/ SLFM
(GHz)
FSB Freq.
(MHz)
IDAT
Freq.(GHz)
HFM TDP
(W)
L2
Cache(MB)
Notes
SLB4M
P8400
m-FCBGA
M-0
000010676h
2.26/1.6/0.8
1066
2.40
25
3
6,11,12
SLB3Q
P8400
m-FCPGA
M-0
000010676h
2.26/1.6/0.8
1066
2.40
25
3
26,8,9
SL3BV
P8600
m-FCBGA
C-0
000010676h
2.40/1.6/0.8
1066
2.53
25
3
6,11,12
SL3BU
P8400
m-FCBGA
C-0
000010676h
2.26/1.6/0.8
1066
2.40
25
3
6,11,12
SLB48
X9100
m-FCPGA
C-0
000010676h
3.06/1.6/0.8
1066
N/A
44
6
1,5,6
SLAYS
T8300
m-FCPGA
M-0
000010676h
2.4/1.2/0.8
800
2.6
35
3
2,3,4,7
SLAYU
T8100
m-FCPGA
M-0
000010676h
2.1/1.2/0.8
800
2.3
35
3
2,3,4,7
SLAYP
T8100
m-FCPGA
M-0
000010676h
2.1/1.2/0.8
800
2.3
35
3
2,3,4,7
SLAYQ
T8300
m-FCPGA
M-0
000010676h
2.4/1.2/0.8
800
2.6
35
3
2,3,4,7
SLG8E
P7350
m-FCBGA
C-0
000010676h
2.00/1.6/0.8
1066
N/A
25
3
17,6,18
SLB45
P7450
m-FCPGA
C-0
000010676h
2.13/1.6/0.8
1066
N/A
25
3
17,6,18
SLB44
P7350
m-FCPGA
C-0
000010676h
2.00/1.6/0.8
1066
N/A
25
3
17,6,18
SLB54
P7450
m-FCPGA
M-0
000010676h
2.13/1.6/0.8
1066
N/A
25
3
17,6,18
SLB53
P7350
m-FCPGA
M-0
000010676h
2.00/1.6/0.8
1066
N/A
25
3
17,6,18
SLB5J
QX9300
m-FCPGA
E-0
00001067Ah
2.53/1.6/(n/a)
1066
2.8
45
12
14,15,16
SLB5G
Q9100
m-FCPGA
E-0
00001067Ah
2.26/1.6/(n/a)
1066
2.53
45
12
14,15,16
SLB64
SP9400
m-FCBGA
C-0
000010676h
2.40/1.6/0.8
1066
2.53
25
6
17,6,18
SLB63
SP9300
m-FCBGA
C-0
000010676h
2.26/1.6/0.8
1066
2.40
25
6
17,6,18
SLB66
SL9400
m-FCBGA
C-0
000010676h
1.86/1.6/0.8
1066
2.13
17
6
19,6,20
SLB65
SL9300
m-FCBGA
C-0
000010676h
1.60/0.8/0.8
1066
1.86
17
6
19,6,20
SLB5V
SU9400
m-FCBGA
M-0
000010676h
1.40/0.8/0.8
800
1.60
10
3
21,22,23
SLB5Q
SU9300
m-FCBGA
M-0
000010676h
1.20/0.8/0.8
800
1.40
10
3
21,22,23
SLGAR
SU3300
m-FCBGA
M-0
000010676h
1.20/0.8/(n/a)
800
N/A
5.5
3
24,13
SLGAS
723
m-FCBGA
M-0
000010676h
1.20/(n/a)/(n/a)
800
N/A
10
1
25,13
QJPQ
SU9600
m-FCBGA
R-0
00001067Ah
1.6/1.2/0.8
800
1.8
10
3
31,32,33
QJPM
SU9400
m-FCBGA
R-0
00001067Ah
1.4/1.2/0.8
800
1.6
10
3
31,32,33
QJPF
SU9300
m-FCBGA
R-0
00001067Ah
1.2/1.2/0.8
800
1.4
10
3
31,32,33
QJNG
SL9600
m-FCBGA
E-0
00001067Ah
2.13/1.6/0.8
1066
2.4
17
6
29,11,30
QJND
SL9400
m-FCBGA
E-0
00001067Ah
1.86/1.6/0.8
1066
2.13
17
6
29,11,30
QJNA
SL9300
m-FCBGA
E-0
00001067Ah
1.6/1.6/0.8
1066
1.86
17
6
29,11,30
QJNR
SP9600
m-FCBGA
E-0
00001067Ah
2.53/1.6/0.8
1066
2.66
25
6
27,11,28
QJNN
SP9400
m-FCBGA
E-0
00001067Ah
2.4/1.6/0.8
1066
2.53
25
6
27,11,28
QJNK
SP9300
m-FCBGA
E-0
00001067Ah
2.26/1.6/0.8
1066
2.4
25
6
27,11,28

Identification Information
Specification Update 11
S-
Spec#
Processor
#
Package
Processor
Stepping
CPUID
Core Frequency
HFM/LFM/ SLFM
(GHz)
FSB Freq.
(MHz)
IDAT
Freq.(GHz)
HFM TDP
(W)
L2
Cache(MB)
Notes
QJNW
723
m-FCBGA
R-0
00001067Ah
1.2/(n/a)/(n/a)
800
N/A
10
1
35,13
QJPT
SU3300
m-FCBGA
R-0
00001067Ah
1.2/1.2/0.8
800
N/A
5.5
3
34,13
QJRU
743
m-FCBGA
R-0
00001067Ah
1.3/(n/a)/(n/a)
800
N/A
10
1
35,13
QKUS
SU3500
m-FCBGA
R-0
00001067Ah
1.4/1.2/0.8
800
N/A
5.5
3
34,13
SLGFN
SU9600
m-FCBGA
R-0
00001067Ah
1.6/1.2/0.8
800
1.8
10
3
31,32,33
SLGAK
SU9400
m-FCBGA
R-0
00001067Ah
1.4/1.2/0.8
800
1.6
10
3
31,32,33
SLGAL
SU9300
m-FCBGA
R-0
00001067Ah
1.2/1.2/0.8
800
1.4
10
3
31,32,33
SLGEQ
SL9600
m-FCBGA
E-0
00001067Ah
2.13/1.6/0.8
1066
2.4
17
6
29,6,30
SLGAB
SL9400
m-FCBGA
E-0
00001067Ah
1.86/1.6/0.8
1066
2.13
17
6
29,6,30
SLGAG
SL9300
m-FCBGA
E-0
00001067Ah
1.6/1.6/0.8
1066
1.86
17
6
29,6,30
SLGER
SP9600
m-FCBGA
E-0
00001067Ah
2.53/1.6/0.8
1066
2.66
25
6
27,6,28
SLGAA
SP9400
m-FCBGA
E-0
00001067Ah
2.4/1.6/0.8
1066
2.53
25
6
27,6,28
SLGAF
SP9300
m-FCBGA
E-0
00001067Ah
2.26/1.6/0.8
1066
2.4
25
6
27,6,28
SLGAM
723
m-FCBGA
R-0
00001067Ah
1.2/(n/a)/(n/a)
800
N/A
10
1
35,13
SLGAJ
SU3300
m-FCBGA
R-0
00001067Ah
1.2/1.2/0.8
800
N/A
5.5
3
34,13
SLGEV
743
m-FCBGA
R-0
00001067Ah
1.3/(n/a)/(n/a)
800
N/A
10
1
35,13
SLGQQ
SU3500
m-FCBGA
R-0
00001067Ah
1.4/1.2/0.8
800
N/A
5.5
3
34,13
NOTES:
1. Does not support Intel® Dynamic Acceleration Technology
2. Vcc core VID=1.000-1.250/0.850-1.250 V [HFM/LFM]; 0.750-0.925 V [S-LFM]
3. Vcc core VID=0.650-0.859/0.600-0.850/0.350-0.700 V [C4/DC4/C6]
4. Vcc core VID=1.000-1.300 [IDAT]
5. Vcc core VID=1.000-1.275/0.850-1.100 V [HFM/LFM]; 0.800-1.000 V [S-LFM]
6. Vcc core VID=0.650-0.850/0.600-0.850/0.35-0.70 V [C4/DC4/C6]
7. This part is screened to avoid Erratum AZ52
8. Vcc core VID=1.050-1.1625/1.000 V [HFM/LFM]; 0.825-0.950 V [S-LFM]
9. Vcc core VID=1.050-1.2125 [IDAT]
10. Vcc core VID=1.000-1.250/0.850-1.100 V [HFM/LFM]; 0.750-0.950 V [S-LFM]
11. Vcc core VID=0.900-1.250/0.850-1.025 V [HFM/LFM]; 0.750-0.950 V [S-LFM]
12. Vcc core VID=0.900-1.300 [IDAT]
13. Intel® Celeron® M processor
14. Vcc core VID=0.90-1.25/0.850-1.100 V [HFM/LFM]
15. Vcc core VID=0.65-0.85 [C4]
16. Vcc core VID=0.90-1.30 [IDAT]
17. Vcc core VID=0.900-1.2125/0.850-1.025 V [HFM/LFM]; 0.75-0.95 V [S-LFM]
18. Vcc core VID=0.900-1.275 [IDAT]
19. Vcc core VID=0.900-1.175/0.850-1.025 V [HFM/LFM]; 0.75-0.95 V [S-LFM]
20. Vcc core VID=0.90-1.25 [IDAT]
21. Vcc core VID=0.775-1.100/0.80-0.975 V [HFM/LFM]; 0.750-0.925 V [S-LFM]
22. Vcc core VID=0.65-0.80/0.60-0.80/0.35-0.60 V [C4/DC4/C6]
23. Vcc core VID=0.80-1.1625 [IDAT]
24. Vcc core VID=0.80-1.25 [VID]
25. Vcc core VID=0.775-1.10 [VID]

Identification Information
12 Specification Update
26. Vcc core VID=0.725-0.775/0.725-0.750/0.400-0.700 V [C4/DC4/C6]
27. Vcc core VID=0.900-1.2125/0.850-1.025 V [HFM/LFM]; 0.75-0.95 V [S-LFM]
28. Vcc core VID=0.900-1.275 [IDAT]
29. Vcc core VID=0.900-1.175/0.850-1.025 V [HFM/LFM]; 0.75-0.95 V [S-LFM]
30. Vcc core VID=0.90-1.25 [IDAT]
31. Vcc core VID=0.775-1.100/0.80-0.975 V [HFM/LFM]; 0.750-0.925 V [S-LFM]
32. Vcc core VID=0.65-0.80/0.60-0.80/0.35-0.60 V [C4/DC4/C6]
33. Vcc core VID=0.80-1.1625 [IDAT]
34. Vcc core VID=0.80-1.25 [VID]
35. Vcc core VID=0.775-1.10 [VID]
36. Vcc core VID=0.900-1.2125/0.850-1.025 V [HFM/LFM]; 0.75-0.95 V [S-LFM]
37. Vcc core VID=0.900-1.2125/0.850-1.025 V [HFM/LFM]; 0.75-0.95 V [S-LFM]
38. Vcc core VID=0.900-1.175/0.850-1.025 V [HFM/LFM]; 0.75-0.95 V [S-LFM]
§

Summary Tables of Changes
Specification Update 13
Summary Tables of Changes
The following table indicates the Specification Changes, Errata, Specification
Clarifications or Documentation Changes, which apply to the listed CPU steppings. Intel
intends to fix some of the errata in a future stepping of the component, and to account
for the other outstanding issues through documentation or Specification Changes as
noted. This table uses the following notations:
Codes Used in Summary Table
Stepping
X: Erratum, Specification Change or Clarification that applies to
this stepping.
(No mark) or (Blank Box): This erratum is fixed in listed stepping or specification change
does not apply to listed stepping.
Status
Doc: Document change or update that will be implemented.
PlanFix: This erratum may be fixed in a future stepping of the
product.
Fixed: This erratum has been previously fixed.
NoFix: There are no plans to fix this erratum.
Row
Shaded: This item is either new or modified from the previous version
of the document.

Summary Tables of Changes
14 Specification Update
Note: Each Specification Update item is prefixed with a capital letter to distinguish the product.
The key below details the letters that are used in Intel‟s microprocessor Specification
Updates:
A = Dual-Core Intel® Xeon® processor 7000 sequence
C = Intel® Celeron® processor
D = Dual-Core Intel® Xeon® processor 2.80 GHz
E = Intel® Pentium® III processor
F = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor
I = Dual-Core Intel® Xeon® processor 5000 series
J = 64-bit Intel® Xeon® processor MP with 1-MB L2 Cache
K = Mobile Intel® Pentium® III processor
L = Intel® Celeron® D processor
M = Mobile Intel® Celeron® processor
N = Intel® Pentium® 4 processor
O = Intel® Xeon® processor MP
P = Intel® Xeon® processor
Q = Mobile Intel® Pentium® 4 processor supporting Hyper-Threading Technology on 90-
nm process technology
R = Intel® Pentium® 4 processor on 90 nm process
S = 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache
versions)
T = Mobile Intel® Pentium® 4 processor–M
U = 64-bit Intel® Xeon® processor MP with up to 8MB L3 Cache
V = Mobile Intel® Celeron® processor on .13 Micron Process in Micro-FCPGA Package
W= Intel® Celeron®-M processor
X = Intel® Pentium® M processor on 90-nm process with 2-MB L2 cache and Intel®
Processors A100 and A110 with 512-KB L2 cache
Y = Intel® Pentium® M processor
Z = Mobile Intel® Pentium® 4 processor with 533 MHz system bus
AA= Intel® Pentium® D Processor 900 Sequence and Intel® Pentium® processor
Extreme Edition 955, 965
AB= Intel® Pentium® 4 processor 6x1 Sequence
AC= Intel® Celeron® processor in 478 pin package
AD = Intel® Celeron® D processor on 65 nm process
AE = Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65nm process
AF = Dual-Core™ Intel® Xeon® processor LV
AG = Dual-Core Intel® Xeon® processor 5100 Series
AH= Intel® Core™2 Duo mobile processor
AI = Intel® Core™2 Extreme processor X6800Δand Intel®Core™2 Duo Desktop
processor E6000 and E4000 Sequence
AJ = Quad-Core Intel® Xeon® processor 5300 Series
AK = Intel® Core™2 Extreme quad-core processor QX6700 and Intel® Core™2 Quad
processor Q6600
AL = Dual-Core Intel® Xeon® processor 7100 Series

Summary Tables of Changes
Specification Update 15
AM = Intel® Celeron® processor 400 sequence
AN = Intel® Pentium® Dual-Core processor
AO = Quad-Core Intel® Xeon® processor 3200 Series
AP = Dual-Core Intel® Xeon® processor 3000 Series
AQ = Intel® Pentium® Dual-Core Desktop Processor E2000 Sequence
AR = Intel® Celeron® processor 500 series
AS = Intel® Xeon® processor 7200, 7300 series
AT = Intel® Celeron® processor 200 series
AU = Intel® Celeron® Dual Core processor T1400
AV = Intel® Core™2 Extreme processor QX9000 sequence and Intel® Core™2 Quad
processor Q9000 sequence processor
AW = Intel® Core™ 2 Duo
AX =Quad-Core Intel® Xeon® processor 5400 series
AY =Dual-Core Intel® Xeon® processor 5200 series
AZ = Intel® Core™2 Extreme Quad-Core Mobile Processor, Intel® Core™2 Quad Mobile
Processor, Intel® Core™2 Extreme Mobile Processor, Intel® Core™2 Duo Mobile
Processor, Intel® Core™2 Solo Mobile Processor and Intel® Celeron® Processor on 45-
nm Process
AAA = Quad-Core Intel® Xeon® processor 3300 series
AAB = Dual-Core Intel® Xeon® E3110 Processor
AAC = Intel® Celeron® dual-core processor E1000 series
AAD = Intel® CoreTM2 Extreme Processor QX9775
AAE = Intel® AtomTM processor Z5xx series
AAF = Intel® AtomTM processor 200 series
AAG = Intel® Atom™ processor N series
AAH = Intel® Atom™ processor 300 series
Note: Intel processor numbers are not a measure of performance. Processor numbers
differentiate features within each processor family, not across different processor
families. See http://www.intel.com/products/processor_number for details.

Summary Tables of Changes
16 Specification Update
Errata
Number
Steppings
Status
ERRATA
C-0
M-0
E-0
R-0
AZ1
X
X
X
X
No Fix
EFLAGS Discrepancy on a Page Fault After a Multiprocessor
TLB Shootdown
AZ2
X
X
X
X
No Fix
INVLPG Operation for Large (2M/4M) Pages May be
Incomplete under Certain Conditions
AZ3
X
X
X
X
No Fix
Store to WT Memory Data May be Seen in Wrong Order by
Two Subsequent Loads
AZ4
X
X
X
X
No Fix
Non-Temporal Data Store May be Observed in Wrong
Program Order
AZ5
X
X
X
X
No Fix
Page Access Bit May be Set Prior to Signaling a Code
Segment Limit Fault
AZ6
X
X
X
X
No Fix
Updating Code Page Directory Attributes without TLB
Invalidation May Result in Improper Handling of Code #PF
AZ7
X
X
X
X
No Fix
Storage of PEBS Record Delayed Following Execution of
MOV SS or STI
AZ8
X
X
X
X
No Fix
Performance Monitoring Event FP_MMX_TRANS_TO_MMX
May Not Count Some Transitions
AZ9
X
X
X
X
No Fix
A REP STOS/MOVS to a MONITOR/MWAIT Address Range
May Prevent Triggering of the Monitoring Hardware
AZ10
X
X
X
X
No Fix
Performance Monitoring Event MISALIGN_MEM_REF May
Over Count
AZ11
X
X
X
X
No Fix
The Processor May Report a #TS Instead of a #GP Fault
AZ12
X
X
X
X
No Fix
Code Segment Limit Violation May Occur on 4 Gigabyte
Limit Check
AZ13
X
X
X
X
No Fix
A Write to an APIC Register Sometimes May Appear to
Have Not Occurred
AZ14
X
X
X
X
No Fix
Last Branch Records (LBR) Updates May be Incorrect after
a Task Switch
AZ15
X
X
X
X
No Fix
REP MOVS/STOS Executing with Fast Strings Enabled and
Crossing Page Boundaries with Inconsistent Memory Types
may use an Incorrect Data Size or Lead to Memory-
Ordering Violations.
AZ16
X
X
X
X
No Fix
Upper 32 bits of 'From' Address Reported through BTMs or
BTSs May be Incorrect
AZ17
X
X
X
X
No Fix
Address Reported by Machine-Check Architecture (MCA) on
Single-bit L2 ECC Errors May be Incorrect
AZ18
X
X
X
X
No Fix
Code Segment Limit/Canonical Faults on RSM May be
Serviced before Higher Priority Interrupts/Exceptions
AZ19
X
X
X
X
No Fix
Store Ordering May be Incorrect between WC and WP
Memory Type

Summary Tables of Changes
Specification Update 17
Number
Steppings
Status
ERRATA
C-0
M-0
E-0
R-0
AZ20
X
X
X
X
No Fix
EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect
after Shutdown
AZ21
X
X
X
X
No Fix
Premature Execution of a Load Operation Prior to Exception
Handler Invocation
AZ22
X
X
X
X
No Fix
Performance Monitoring Events for Retired Instructions
(C0H) May Not Be Accurate
AZ23
X
X
X
X
No Fix
Returning to Real Mode from SMM with EFLAGS.VM Set May
Result in Unpredictable System Behavior
AZ24
X
X
X
X
No Fix
CMPSB, LODSB, or SCASB in 64-bit Mode with Count
Greater or Equal to 248 May Terminate Early
AZ25
X
X
X
X
No Fix
Writing the Local Vector Table (LVT) when an Interrupt is
Pending May Cause an Unexpected Interrupt
AZ26
X
X
X
X
No Fix
Pending x87 FPU Exceptions (#MF) Following STI May Be
Serviced Before Higher Priority Interrupts
AZ27
X
X
X
X
No Fix
VERW/VERR/LSL/LAR Instructions May Unexpectedly
Update the Last Exception Record (LER) MSR
AZ28
X
X
X
X
No Fix
INIT Does Not Clear Global Entries in the TLB
AZ29
X
X
X
X
No Fix
Split Locked Stores May not Trigger the Monitoring
Hardware
AZ30
X
X
X
X
No Fix
Programming the Digital Thermal Sensor (DTS) Threshold
May Cause Unexpected Thermal Interrupts
AZ31
X
X
X
X
No Fix
Writing Shared Unaligned Data that Crosses a Cache Line
without Proper Semaphores or Barriers May Expose a
Memory Ordering Issue
AZ32
X
X
X
X
No Fix
General Protection (#GP) Fault May Not Be Signaled on
Data Segment Limit Violation above 4-G Limit
AZ33
X
X
X
X
No Fix
An Asynchronous MCE During a Far Transfer May Corrupt
ESP
AZ34
X
X
X
X
Plan
Fix
CPUID Reports Architectural Performance Monitoring
Version 2 is Supported, When Only Version 1 Capabilities
are Available
AZ35
X
X
X
X
No Fix
B0-B3 Bits in DR6 May Not be Properly Cleared After Code
Breakpoint
AZ36
X
X
X
X
No Fix
An xTPR Update Transaction Cycle, if Enabled, May be
Issued to the FSB after the Processor has Issued a Stop-
Grant Special Cycle
AZ37
X
X
X
X
Plan
Fix
Performance Monitoring Event IA32_FIXED_CTR2 May Not
Function Properly when Max Ratio is a Non-Integer Core-
to-Bus Ratio
AZ38
X
X
X
X
No Fix
Instruction Fetch May Cause a Livelock During Snoops of
the L1 Data Cache
AZ39
X
X
X
X
No Fix
Use of Memory Aliasing with Inconsistent Memory Type
may Cause a System Hang or a Machine Check Exception

Summary Tables of Changes
18 Specification Update
Number
Steppings
Status
ERRATA
C-0
M-0
E-0
R-0
AZ40
X
X
X
X
No Fix
A WB Store Following a REP STOS/MOVS or FXSAVE May
Lead to Memory-Ordering Violations
AZ41
X
X
X
X
Plan
Fix
VM Exit with Exit Reason "TPR Below Threshold" Can Cause
the Blocking by MOV/POP SS and Blocking by STI Bits to be
Cleared in the Guest Interruptibility-State Field
AZ42
X
X
X
X
No Fix
Using Memory Type Aliasing with Cacheable and WC
Memory Types May Lead to Memory Ordering Violations
AZ43
X
X
X
X
No Fix
VM Exit Caused by a SIPI Results in Zero Being Saved to
the Guest RIP Field in the VMCS
AZ44
X
X
X
X
No Fix
NMIs May Not Be Blocked by a VM-Entry Failure
AZ45
X
X
X
X
Plan
Fix
Partial Streaming Load Instruction Sequence May Cause
the Processor to Hang
AZ46
X
X
X
X
Plan
Fix
Self/Cross Modifying Code May Not be Detected or May
Cause a Machine Check Exception
AZ47
X
X
X
X
Plan
Fix
Data TLB Eviction Condition in the Middle of a Cacheline
Split Load Operation May Cause the Processor to Hang
AZ48
X
X
X
X
Plan
Fix
Update of Read/Write (R/W) or User/Supervisor (U/S) or
Present (P) Bits without TLB Shootdown May Cause
Unexpected Processor Behavior
AZ49
X
X
X
X
Plan
Fix
RSM Instruction Execution under Certain Conditions May
Cause Processor Hang or Unexpected Instruction Execution
Results
AZ50
X
X
X
X
No Fix
Benign Exception after a Double Fault May Not Cause a
Triple Fault Shutdown
AZ51
X
X
X
X
No Fix
LER MSRs May Be Incorrectly Updated
AZ52
X
X
X
X
Plan
Fix
Processor May Unexpectedly Assert False THERMTRIP#
After Receiving a Warm Reset
AZ53
X
X
X
X
Plan
Fix
Short Nested Loops That Span Multiple 16-Byte Boundaries
May Cause a Machine Check Exception or a System Hang
AZ54
X
X
X
X
No Fix
IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine
Check Error Reporting Enable Correctly
AZ55
X
X
X
X
No Fix
An Enabled Debug Breakpoint or Single Step Trap May Be
Taken after MOV SS/POP SS Instruction if it is Followed by
an Instruction That Signals a Floating Point Exception
AZ56
X
X
X
X
No Fix
Code Segment Limit/Canonical Faults on RSM May be
Serviced before Higher Priority Interrupts/Exceptions and
May Push the Wrong Address Onto the Stack
AZ57
X
X
X
X
No Fix
A VM Exit Due to a Fault While Delivering a Software
Interrupt May Save Incorrect Data into the VMCS
AZ58
X
X
X
X
No Fix
A VM Exit Occurring in IA-32e Mode May Not Produce a
VMX Abort When Expected
AZ59
X
X
X
X
No Fix
IRET under Certain Conditions May Cause an Unexpected
Alignment Check Exception

Summary Tables of Changes
Specification Update 19
Number
Steppings
Status
ERRATA
C-0
M-0
E-0
R-0
AZ60
X
X
X
X
No Fix
Thermal Interrupts are Dropped During and While Exiting
Intel® Deep Power-Down State
AZ61
X
X
X
X
No Fix
VM Entry May Fail When Attempting to Set
IA32_DEBUGCTL.FREEZE_WHILE_SMM_EN
AZ62
X
X
No Fix
VM Entry May Use Wrong Address to Access Virtual-APIC
Page
AZ63
X
X
No Fix
INIT Incorrectly Resets IA32_LSTAR MSR
AZ64
X
X
No Fix
When a CPUID instruction is executed, the returned EAX,
EBX, ECX, and/or EDX may be incorrect.
AZ65
X
X
X
X
No Fix
Global Instruction TLB Entries May Not be Invalidated on a
VM Exit or VM Entry
AZ66
X
X
No Fix
XRSTOR Instruction May Cause Extra Memory Reads
AZ67
X
X
X
X
No Fix
LBR, BTS, BTM May Report a Wrong Address when an
Exception/Interrupt Occurs in 64-bit Mode
AZ68
X
X
No Fix
When Intel® Deep Power-Down State is Being Used,
IA32_FIXED_CTR2 May Return Incorrect Cycle Counts
AZ69
X
X
No Fix
Enabling PECI via the PECI_CTL MSR Incorrectly
Writes CPUID_FEATURE_MASK1 MSR
AZ70
X
X
X
X
No Fix
Corruption of CS Segment Register During RSM While
Transitioning From Real Mode to Protected Mode
AZ71
X
X
No Fix
The XSAVE Instruction May Erroneously Set Reserved Bits
in the XSTATE_BV Field
AZ72
X
X
No Fix
Store Ordering Violation When Using XSAVE
AZ73
X
X
X
X
No Fix
Memory Ordering Violation With Stores/Loads Crossing a
Cacheline Boundary
AZ74
X
X
No Fix
The XRSTOR Instruction May Fail to Cause a General-
Protection Exception
AZ75
X
X
X
X
No Fix
B0-B3 Bits in DR6 For Non-Enabled Breakpoints May be
Incorrectly Set
AZ76
X
X
X
X
No Fix
A 64-bit Register IP-relative Instruction May Return
Unexpected Results
AZ77
X
X
X
X
No Fix
Intel® Trusted Execution Technology ACM Revocation
Number
SPECIFICATION CHANGES
There are no Specification Changes in this Specification Update revision

Summary Tables of Changes
20 Specification Update
Number
SPECIFICATION CLARIFICATIONS
AZ1
Clarification of Translation Lookaside Buffers (TLBS) Invalidation
AZ2
CPUID Instruction Will Return Brand String With a Missing Letter
Number
DOCUMENTATION CHANGES
There are no Documentation Changes in this Specification Update revision.
§