Intel Quark SoC X1000 Guide

Order Number: 330258-002US
Intel®Quark™ SoC X1000
Platform Design Guide (PDG)
Revision 002US
June 2014

Intel®Quark™ SoC X1000
PDG June 2014
2Order Number: 330258-002US
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Contents—Intel®Quark™ SoC X1000
Contents
1.0 Introduction ............................................................................................................ 15
1.1 Terminology ..................................................................................................... 16
2.0 Stack-Up and PCB Considerations ............................................................................ 17
2.1 Printed Circuit Board (PCB) Considerations ........................................................... 17
2.2 Low Halogen Flame Retardant Stack-Up Considerations .......................................... 19
2.2.1 Low Halogen Background ........................................................................ 19
2.2.2 Choosing a Low Halogen Material.............................................................. 19
2.2.3 Electrical Limits of Low Halogen Material Properties..................................... 19
2.3 Reference Planes............................................................................................... 20
2.4 Backward and Forward Coupling Coefficient Calculation .......................................... 20
2.5 Single-Ended and Differential-Impedance Transmission Line Specifications................ 22
2.6 Minimizing the Effect of Fiber Weave .................................................................... 23
2.6.1 Overview of Fiber Weave ......................................................................... 23
2.6.2 Fiber Weave Effect versus Transfer Rate and Trace Length........................... 25
2.6.3 Specific Routing Configurations ................................................................ 26
2.6.4 Offset Routing........................................................................................ 26
2.6.5 Zig-Zag or Slanted Routing...................................................................... 26
2.6.6 Image Rotation ...................................................................................... 27
2.6.7 Using Alternate PCB Materials .................................................................. 28
3.0 DDR3 Memory Design Guidelines ............................................................................. 29
3.1 Memory General Introduction.............................................................................. 29
3.1.1 Supported Memory Configurations ............................................................ 29
3.1.2 Memory Population Rules ........................................................................ 29
3.1.3 Reference Documents ............................................................................. 29
3.1.4 Design Constraints-based Routing ............................................................ 29
3.2 Memory Signal Description ................................................................................. 30
3.3 Memory Topology Guidelines............................................................................... 30
3.3.1 Single Rank Fly-by Topology with Active VTT Termination ............................ 31
3.3.2 Memory Stackup Guidelines ..................................................................... 36
3.3.3 Memory Configurations and Connectivity ................................................... 37
3.3.3.1 ODT Signal Connectivity and Support .......................................... 37
3.3.4 Memory Physical Layout Guidelines........................................................... 37
3.3.4.1 General Routing Guidelines ........................................................ 37
3.3.4.2 Byte Lane Placement ................................................................. 37
3.3.4.3 Via Stitching and Placement ....................................................... 38
3.3.5 Memory Bit and Byte Lane Swapping ........................................................ 38
3.3.6 Memory Length Matching Guidelines ......................................................... 38
3.3.6.1 Length Matching and Length Formulas ......................................... 38
3.3.6.2 Package Length Compensation ................................................... 38
3.3.7 Memory Decoupling Guidelines................................................................. 38
3.4 Memory Reference Voltage and Compensation Guidelines ....................................... 38
3.4.1 SoC DDR Reference Voltage..................................................................... 38
3.4.2 DRAM Reference Voltage ......................................................................... 39
3.4.3 DRAM ZQ Calibration .............................................................................. 39
3.4.4 Routing Guidelines for Compensation Signals ............................................. 39
3.5 DataMask Guidelines.......................................................................................... 39
4.0 PCI Express* Design Guidelines .............................................................................. 41
4.1 PCIe* General Introduction................................................................................. 41
4.1.1 Description............................................................................................ 41
4.1.2 Supported Configuration Options for PCIe* Ports ........................................ 41

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4.1.3 PCI Express* Lane Polarity Inversion.........................................................41
4.1.4 PCI Express* Port Lane Reversal...............................................................42
4.1.5 PCH PCIe* Disabling and Termination Guidelines.........................................42
4.1.6 Length Matching Guidelines......................................................................42
4.1.7 Impedance Compensation and Voltage Reference........................................42
4.1.8 Reference Documents..............................................................................43
4.2 PCIe* Signal Descriptions ...................................................................................43
4.2.1 Signal Groups ........................................................................................43
4.3 PCIe* Topology Guidelines ..................................................................................43
4.3.1 Expansion Card Connector Topology..........................................................44
5.0 Universal Serial Bus 2.0 Design Guidelines...............................................................47
5.1 USB 2.0 General Introduction ..............................................................................47
5.1.1 Description ............................................................................................47
5.1.2 Compliance Documents ...........................................................................47
5.2 USB 2.0 Signal Descriptions ................................................................................48
5.2.1 Signal Groups ........................................................................................48
5.2.2 Overcurrent Protection ............................................................................48
5.3 USB 2.0 Topology Guidelines...............................................................................49
5.3.1 External Topologies.................................................................................49
5.3.2 USB Connector Recommendations.............................................................52
5.3.2.1 External Connector Recommendations..........................................52
5.3.3 Daughter Card .......................................................................................53
5.3.3.1 Daughter Card Design Guidelines ................................................53
5.4 USB 2.0 Stackup Guidelines ................................................................................53
5.4.1 Stackup and Layer Utilization Guidelines ....................................................53
5.5 USB 2.0 Configuration, Connectivity, Block Diagram ...............................................53
5.5.1 Port Power Delivery.................................................................................54
5.6 USB 2.0 Length Matching Guidelines.....................................................................54
5.6.1 Length Matching and Length Formulas.......................................................54
5.7 USB 2.0 Additional Guidelines..............................................................................54
5.7.1 EMI and ESD Protection ...........................................................................54
5.8 USB 2.0 Disabling and Termination Guidelines .......................................................54
6.0 I2C* Interface Design Guidelines.............................................................................55
6.1 I2C* General Introduction...................................................................................55
6.1.1 Description ............................................................................................55
6.1.2 Reference Specifications ..........................................................................55
6.2 I2C* Signal Descriptions .....................................................................................55
6.2.1 Signal Groups ........................................................................................55
6.3 I2C* Topology Guidelines....................................................................................56
6.3.1 General Design Considerations .................................................................56
6.3.2 Detailed Routing Requirements.................................................................56
6.4 I2C* Connectivity ..............................................................................................57
6.5 I2C* Additional Guidelines ..................................................................................58
6.6 Terminating Unused I2C Signals...........................................................................58
7.0 SDIO Interface Design Guidelines ............................................................................59
7.1 SDIO General Introduction ..................................................................................59
7.1.1 Description ............................................................................................59
7.2 SDIO Signal Descriptions ....................................................................................59
7.2.1 Signal Groups ........................................................................................59
7.3 SDIO Topology Guidelines...................................................................................60
7.4 Terminating Unused SDIO Signals........................................................................60
8.0 UART Interface Design Guidelines............................................................................63

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Contents—Intel®Quark™ SoC X1000
8.1 General Introduction.......................................................................................... 63
8.1.1 Description............................................................................................ 63
8.2 General Purpose Signal Descriptions .................................................................... 63
8.2.1 Signal Groups ........................................................................................ 63
8.3 UART Topology Guidelines .................................................................................. 63
8.4 Additional Guidelines ......................................................................................... 64
8.5 Terminating Unused UART Signals ....................................................................... 64
9.0 General Purpose SPI Interface Design Guidelines.................................................... 67
9.1 General Introduction.......................................................................................... 67
9.1.1 Description............................................................................................ 67
9.2 General Purpose Signal Descriptions .................................................................... 67
9.2.1 Signal Groups ........................................................................................ 67
9.3 Topology Guidelines........................................................................................... 68
9.4 Terminating Unused SPI Signals .......................................................................... 71
10.0 Platform Clocks Design Guidelines........................................................................... 73
10.1 Platform Clock General Introduction..................................................................... 73
10.1.1 Description............................................................................................ 73
10.2 Platform Reference Clock Signal Descriptions ........................................................ 74
10.3 Platform Clocks Topology Guidelines .................................................................... 75
10.3.1 Differential Clock Routing Topology........................................................... 75
10.3.1.1 Differential Routing Considerations.............................................. 76
10.3.1.2 Stitching Via Usage and Placement.............................................. 76
10.3.2 Single Ended Clock Routing Topology ........................................................ 76
10.4 25 MHz Crystal and Associated RC Components..................................................... 77
10.4.1 Crystal External Load Capacitor Requirements............................................ 78
10.4.2 25 MHz Crystal Routing Considerations...................................................... 79
11.0 SPI Flash Design Guidelines .................................................................................... 81
11.1 Serial Peripheral Interface (SPI) General Introduction ............................................ 81
11.1.1 Description............................................................................................ 81
11.2 Serial Peripheral Interface (SPI) Signal Description ................................................ 81
11.3 Serial Peripheral Interface (SPI) Topology Guidelines ............................................. 82
11.3.1 SPI Single Flash Device Topology Guidelines .............................................. 82
11.3.1.1 SPI Single Flash Device Routing Guideline .................................... 82
11.3.1.2 SPI Single Flash Device Length Matching Requirement ................... 83
11.3.2 Boot BIOS Destination ............................................................................ 83
11.4 Serial Flash Vendors .......................................................................................... 83
12.0 RTC Design Guidelines ............................................................................................. 85
12.1 Real Time Clock General Introduction................................................................... 85
12.1.1 Description............................................................................................ 85
12.2 Real Time Clock Signal Descriptions ..................................................................... 85
12.2.1 Signal Groups ........................................................................................ 85
12.2.2 State Power Good Indicators.................................................................... 86
12.3 Real Time Clock Topology Guidelines.................................................................... 87
12.3.1 RTC External Example Circuit ................................................................... 87
12.3.2 General RTC Layout Considerations........................................................... 88
12.3.3 External Capacitors ................................................................................ 88
12.4 RTC External Battery Connection ......................................................................... 89
12.4.1 RTC Holdup Calculation ........................................................................... 90
12.5 RTC External RTCRST# Circuit ............................................................................ 91
12.6 RTC-Well Input Strap Requirements..................................................................... 92
13.0 Asynchronous Signals Design Guidelines ................................................................. 93
13.1 Asynchronous Signals General Introduction........................................................... 93

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13.1.1 Description ............................................................................................93
13.2 Asynchronous Signal Descriptions ........................................................................93
13.2.1 Signal Groups ........................................................................................93
13.3 Asynchronous Signals Topology Guidelines ............................................................93
13.4 General GPIO Topology Guidelines .......................................................................94
14.0 Platform Power Delivery Requirements....................................................................97
15.0 Platform Reset Considerations ............................................................................... 101
15.1 Platform Reset General Introduction................................................................... 101
15.1.1 Description .......................................................................................... 101
15.2 Signal Description ............................................................................................ 101
15.2.1 Signal Groups ...................................................................................... 101
15.3 Additional Guidelines ........................................................................................ 102
15.3.1 S0_3V3_EN Usage Model ....................................................................... 102
15.3.2 S0_1V5_EN Usage Model ....................................................................... 102
15.3.3 S0_1V0_EN Usage Model ....................................................................... 102
15.3.4 S3_3V3_EN Usage Model ....................................................................... 102
15.3.5 S3_1V5_EN Usage Model ....................................................................... 102
15.3.6 PWRBTN# Usage Model ......................................................................... 102
15.3.7 RSTBTN# Usage Model .......................................................................... 102
15.3.8 Power-well Isolation Control Signal Requirements .....................................103
15.3.9 platform_s5_pwrok Generation............................................................... 103
15.3.10platform_S3_pwrok Generation .............................................................. 103
15.3.11platform_S0_1P0_pwrok Generation ....................................................... 103
15.3.12platform_S0_1P5_pwrok Generation ....................................................... 103
15.3.13Glue Logic Device ................................................................................. 103
15.3.14Additional Power Sequencing Considerations ............................................ 104
15.3.15Power Sequence Timing Diagram ............................................................ 104
16.0 Critical Low Speed Signals Design Guidelines......................................................... 105
16.1 Critical Low Speed Signals General Introduction................................................... 105
16.1.1 Description .......................................................................................... 105
16.2 Critical Low Speed Signal Descriptions ................................................................105
16.2.1 Signals Group ...................................................................................... 105
16.3 Additional Guidelines ........................................................................................ 106
17.0 Electromagnetic Interference................................................................................. 107
17.1 Electromagnetic Interference (EMI) General Introduction ......................................107
17.1.1 Description .......................................................................................... 107
17.2 Exercising the System for EMC Testing ............................................................... 107
17.3 EMI Source ..................................................................................................... 109
17.3.1 Current Loop Radiation .......................................................................... 109
17.3.2 Voltage Regulator Module Current Loop Radiation .....................................110
17.3.3 Common Mode Radiation ....................................................................... 112
17.4 EMI Optimization Guideline ............................................................................... 113
17.4.1 Avoid Changing Referencing, Lack of Referencing, Void-crossing, and Split-
crossing .............................................................................................. 113
17.4.2 Avoid Signal Traces Too Close to the Edges of Planes................................. 114
17.4.3 Avoid Unnecessary Traces Too Close to IO and Other Connectors ................ 114
17.4.4 EMI Mitigation through Stitching and Decoupling Capacitors .......................115
17.4.4.1 Stitching Capacitors................................................................. 116
17.4.4.2 Decoupling Capacitors.............................................................. 118
17.4.5 Common Mode Filter ............................................................................. 120
17.4.5.1 USB Common Mode Choke Recommendation .............................. 120
17.4.6 USB 2.0 Common Mode Chokes .............................................................. 120
17.4.7 Spread Spectrum Clocking ..................................................................... 121

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Contents—Intel®Quark™ SoC X1000
17.4.8 Signal Scrambling ................................................................................ 122
17.4.9 Memory Down ..................................................................................... 123
17.4.9.1 Layer Transition...................................................................... 123
17.4.9.2 Clustered Signal Vias............................................................... 123
17.4.10Cable/Adaptor Shielding ........................................................................ 124
17.5 Design Checklist Items..................................................................................... 125
18.0 Electrostatic Discharge (ESD) ................................................................................ 127
18.1 Electrostatic Discharge (ESD) General Introduction .............................................. 127
18.1.1 Description.......................................................................................... 127
18.1.2 Reference Specifications........................................................................ 128
18.2 ESD Protection................................................................................................ 128
18.2.1 ESD Ground-Fill ................................................................................... 129
18.2.2 Ground-Fill Background......................................................................... 129
18.2.3 USB ESD Diode Recommendation ........................................................... 130
18.2.4 Series RC Filters................................................................................... 130
18.2.5 Sensitive Nets...................................................................................... 133
18.3 USB ESD Component Selection Guidelines .......................................................... 134
18.3.1 USB 2.0 ESD Protection......................................................................... 134
18.3.2 USB 2.0 ESD Protection Diode Vendors ................................................... 136
18.4 Design Checklist Items..................................................................................... 138
19.0 Platform Debug and Test Hooks............................................................................. 139
19.1 Platform Debug and Test Hooks General Introduction ........................................... 139
19.1.1 Description.......................................................................................... 139
19.2 Platform Debug Port ........................................................................................ 139
19.2.1 Signal Routing Guidelines ...................................................................... 139
19.3 JTAG Boundary Scan........................................................................................ 139
19.3.1 Terminating Unused JTAG Signals........................................................... 139
19.4 Additional Debug Support Guidelines.................................................................. 140
19.4.1 Test Points Requirements ...................................................................... 140
20.0 Design for Testability (DFT)................................................................................... 141
20.1 DFT General Introduction ................................................................................. 141
20.1.1 Description.......................................................................................... 141
20.1.2 Reference Documents ........................................................................... 141
20.2 DFT Configuration, Connectivity, Block Diagram .................................................. 141
21.0 LAN Design Considerations and Guidelines ............................................................ 145
21.1 PHY Overview ................................................................................................. 146
21.1.1 PHY Interconnects ................................................................................ 146
21.1.2 RMII Interface ..................................................................................... 147
21.1.2.1 RMII Interface Signals ............................................................. 147
21.1.2.2 RMII Reference Clock .............................................................. 147
21.1.3 MDIO Interface .................................................................................... 147
21.1.3.1 MDIO Connectivity .................................................................. 147
21.2 Platform LAN Design Guidelines......................................................................... 147
21.2.1 General Design Considerations for PHYs .................................................. 147
21.2.1.1 Clock Source .......................................................................... 148
21.2.1.2 Magnetics Module ................................................................... 148
21.2.1.3 Criteria for Integrated Magnetics Electrical Qualification ............... 148
21.2.2 NVM Configuration for PHY Implementations ............................................ 149
21.2.3 LED Example ....................................................................................... 149
21.2.3.1 RBIAS ................................................................................... 150
21.3 Intel®Quark™ SoC X1000 – MDIO/RMII LOM Design Guidelines............................ 151
21.4 General Layout Guidelines ................................................................................ 152
21.5 Layout Considerations...................................................................................... 152

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21.6 Guidelines for Component Placement.................................................................. 152
21.6.1 PHY Placement Recommendations........................................................... 152
21.7 MDI Differential-Pair Trace Routing for LAN Design ............................................... 154
21.8 Signal Trace Geometry ..................................................................................... 154
21.9 Trace Length and Symmetry ............................................................................. 157
21.10 Impedance Discontinuities ................................................................................ 157
21.11 Reducing Circuit Inductance .............................................................................. 158
21.12 Signal Isolation ............................................................................................... 158
21.13 Power and Ground Planes ................................................................................. 158
21.14 Traces for Decoupling Capacitors ....................................................................... 161
21.15 Ground Planes under a Magnetics Module............................................................ 161
21.16 Light Emitting Diodes ....................................................................................... 163
21.17 Vibrational Mode.............................................................................................. 163
21.18 Nominal Frequency .......................................................................................... 163
21.19 Frequency Tolerance ........................................................................................ 163
21.20 Troubleshooting Common Physical Layout Issues ................................................. 163
21.21 Power Delivery ................................................................................................ 165
21.22 Routing Guidelines ........................................................................................... 165
22.0 Wireless Modules and Antenna Design Guidelines .................................................. 167
22.1 Introduction .................................................................................................... 167
22.2 WLAN System Integration Considerations............................................................ 167
22.2.1 Antenna Integration into the Platform......................................................167
22.2.2 Antenna Coexistence............................................................................. 168
22.2.3 WiFi Module ......................................................................................... 168
22.2.4 WiFi Module Connector Types ................................................................. 169
22.2.5 WiFi Antenna Placement ........................................................................ 169
22.2.6 Antenna Placement ............................................................................... 169
22.2.7 Antenna Cabling ................................................................................... 170
22.2.8 Platform Noise Mitigation ....................................................................... 170
22.2.9 Antenna Material Choices ....................................................................... 170
22.3 ZigBee System Integration Considerations .......................................................... 170
22.3.1 ZigBee Antenna Placement..................................................................... 170
A General Differential Signals Design Guidelines ....................................................... 171
A.1 Introduction .................................................................................................... 171
A.2 General Differential Routing Guidelines ............................................................... 171
A.3 General Differential Length Matching Guidelines ................................................... 171
A.3.1 Length Matching and Length Formulas.....................................................171
A.4 General Differential Optimization Guidelines ........................................................ 174
A.4.1 Breakout Example and Guidelines ........................................................... 174
A.4.2 Via Placement and Via Usage Optimization ...............................................175
A.4.3 Bend Optimization Guidelines ................................................................. 177
A.5 General Differential Reference Planes Guidelines .................................................. 178
B Exposed Pad* (e-Pad*) Design and SMT Assembly Guide....................................... 181
B.1 Overview ........................................................................................................ 181
B.2 PCB Design Requirements ................................................................................. 181
B.3 Board Mounting Guidelines................................................................................ 183
B.4 Stencil Design ................................................................................................. 183
B.5 Assembly Process Flow ..................................................................................... 184
B.6 Reflow Guidelines ............................................................................................ 185

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Contents—Intel®Quark™ SoC X1000
Figures
1Intel
®Quark™ SoC X1000 Block Diagram ................................................................... 16
2 Single-Ended Microstrip Diagram................................................................................ 18
3 Differential-Microstrip Diagram .................................................................................. 18
4 Backward Coupling Coefficient ................................................................................... 21
5 Forward Coupling Coefficient ..................................................................................... 21
6 Single-ended Kb Diagram.......................................................................................... 22
7 Differential Kb Diagram............................................................................................. 22
8 Common Glass Cloths Used in PCB Manufacture ........................................................... 24
9 Inhomogeneous Nature of a PCB as Shown in this Cross-Section .................................... 24
10 Effect of Skew on Differential and Common Mode Signals .............................................. 25
11 Cross-Section of PCB Indicating Effect of PCB Fiber Weave ............................................ 25
12 An Example of Offset Routing .................................................................................... 26
13 An Example of Zig-Zag Routing.................................................................................. 27
14 An Example of Slanted Routing .................................................................................. 27
15 An Example of a PCB Cut Such That Its Edges are Rotated Relative to the Fiber
Weave Pattern......................................................................................................... 28
16 DQ/DM - Data Routing Topology for a Single Rank 4L Fly-by Design - PCB Type 3............. 31
17 DQS - Data Strobes Routing Topology for a Single Rank 4L Fly-by Design - PCB Type 3..... 31
18 ODT/CKE/CS - Control Routing Topology for a Single Rank 4L Fly-by Design - PCB Type 3 . 33
19 MA/BS/CAS/RAS/ WE - Command Routing Topology for a Single Rank 4L Fly–by
Design—PCB Type 3 ................................................................................................. 34
20 Clock Routing Topology for a Single Rank 4L Fly-by Design—PCB Type 3 ......................... 35
21 DDR3 Memory Down Block Diagram ........................................................................... 37
22 Polarity Inversion on a TX to RX Interconnect .............................................................. 42
23 PCI Express* Expansion Card Connector Topology ........................................................ 44
24 USB Port Mapping .................................................................................................... 47
25 Sample Over Current Protection Circuit ....................................................................... 49
26 USB 2.0 MicroUSB Topology ...................................................................................... 49
27 USB 2.0 Mini PCIe Topology ...................................................................................... 51
28 Example of Internal Connector Pin Assignment and Description ..................................... 52
29 Daughter Card......................................................................................................... 53
30 Example of Devices on I2C* Bus ................................................................................ 57
31 SDIO Topology with Connector .................................................................................. 60
32 UART Topology ........................................................................................................ 64
33 SPI0 Topology ......................................................................................................... 68
34 SPI1 Topology ......................................................................................................... 69
35 Clock Integration Distribution Diagram........................................................................ 73
36 Differential Clock Topology for SoC to Clock Receiver .................................................... 75
37 Single Ended Clock Topology for SoC .......................................................................... 76
38 25 MHz Crystal External Load Capacitor Parameters..................................................... 79
39 Legacy SPI Topology (Single Device) .......................................................................... 82
40 SPI Single Flash Device Routing Guidelines for LSPI0_MOSI, LSPI0_MISO,
LSPI0_CS_N,LSPI0_SCK ........................................................................................... 82
41 RTCX1 and RTCX2 Relationship in SoC ........................................................................ 85
42 Example External Circuitry for the SoC RTC ................................................................. 87
43 A Schottky Diode Circuit to Connect RTC External Battery.............................................. 90
44 RTCRST# External Circuit for the SoC RTC................................................................... 91
45 Example GPIO[7:0] Topology level shifted Guideline ..................................................... 94
46 Generic GPIO[7:0] Topology Guideline ........................................................................ 94
47 Intel® Galileo Platform Power Delivery ....................................................................... 98
48 Intel®Quark™ SoC X1000 Power-up Sequence............................................................ 99
49 platform_s5_pwrok generation................................................................................. 103
50 Power Sequence Timing .......................................................................................... 104
51 Time Domain Capture of Exerciser Operation ............................................................. 108

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52 Current Loop Radiation of a Transmission Line............................................................ 109
53 Radiation Cancellation of a Differential Line................................................................ 110
54 An Example of VR EMI Noise .................................................................................... 111
55 VR Noise Can Result In Both SI and EMI Issues ..........................................................111
56 Simplified Voltage Regulator Module Circuit and VRM EMI Noise.................................... 111
57 The Vx Ripples with/without Gate Resistors (Left: without gate resistor/ Right: with gate
resistor) ................................................................................................................ 112
58 Emission from a Differential line with Various Skews ................................................... 113
59 Changing Referencing, Lack of Referencing, Void-crossing, and Split-crossing are Not
Recommended ....................................................................................................... 114
60 Signal Traces Should be away from Plane Edges ......................................................... 114
61 Keep-out Zone Determined Around IO and Other Connectors ....................................... 115
62 Simple Capacitor Model and an Example of Capacitor Impedance .................................. 115
63 Stitching Capacitors Could Create Low Impedance Path for Return Currents ...................116
64 Stitching Capacitors Mitigate EMI (Simulated Results).................................................. 117
65 Stitching Capacitors Should be Close to Traces ........................................................... 118
66 Decoupling Capacitors Locations ............................................................................... 118
67 Decoupling Capacitors with Vias ............................................................................... 119
68 Decoupling Capacitors Around the Edges of Power Plane .............................................. 119
69 USB 2.0 Common Mode Choke .................................................................................120
70 Demonstration of Spread Spectrum Clocking (SSC)..................................................... 121
71 Spectral Comparison of a Clock Scrambled vs. Unscrambled......................................... 122
72 Ground Vias Placement ........................................................................................... 123
73 Cable/Adaptor Shielding Impacts EMI Significantly ...................................................... 124
74 IEC 61000-4-2 ESD Waveform ................................................................................. 128
75 Mutual L and C (Lm, Cm) Coupling............................................................................129
76 Ground Shape Along the I/O Edge of the Board ..........................................................130
77 Series RC Filter for ESD Mitigation on Asynchronous Nets............................................. 131
78 Frequency Response of The Series RC Filter ............................................................... 131
79 ESD Noise Suppression Using Series RC Filters ........................................................... 132
80 Signal Integrity Analysis With Series RC Filters ........................................................... 133
81 Circuit Diagram of Direct Injection Method ................................................................. 134
82 USB 2.0 ESD Protection Devices ...............................................................................135
83 Typical Integrated Diode Array Package..................................................................... 135
84 Layout Example of USB 2.0 with ESD Diode Array.......................................................136
85 Differential S-parameters from Ceramic 1-line, Si 4-line and Si 6-line
ESD Protection Devices. .......................................................................................... 137
86 Example of Test Bead on a Stub (Not Preferred) ......................................................... 142
87 Example of Differential Test Bead with Matched Placement........................................... 142
88 Bead Formed Over Solder-Mask Opening ...................................................................143
89 Bead Placed on Existing Via ..................................................................................... 144
90 SOC/PHY Interface Connections................................................................................ 145
91 LED Hardware Configuration .................................................................................... 150
92 Single PHY Solution Interconnect .............................................................................. 151
93 PLC Placement: At Least One Inch from I/O Backplane ................................................ 153
94 Effect of LAN Device Placed Too Close To a RJ-45 Connector or Chassis Opening .............153
95 MDI Trace Geometry............................................................................................... 156
96 MDI Differential Trace Geometry............................................................................... 157
97 Trace Transitioning Layers and Crossing Plane Splits ................................................... 159
98 Via Connecting GND to GND.....................................................................................160
99 Stitching Capacitor between Vias Connecting GND to GND ........................................... 160
100 Ideal Ground Split Implementation ........................................................................... 161
101 Ground Layout with USB.......................................................................................... 162
102 Typical ePAD* Land Pattern .....................................................................................182
103 Typical Thermal Pad and Via Recommendations .......................................................... 182

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Contents—Intel®Quark™ SoC X1000
104 Recommended Thermal Via Patterns......................................................................... 183
105 Stencil Design Recommendation .............................................................................. 184
106 Assembly Flow....................................................................................................... 184
107 Typical Profile Band ................................................................................................ 185

Intel®Quark™ SoC X1000—Contents
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Tables
1 Platform Stack-up Parameter Values (Microstrip) ..........................................................18
2 Electrical Limits of LH Material Properties .....................................................................20
3 Breakout Geometries for Various I/O Interfaces............................................................23
4 Max Root Square Sum (RSS) Length vs. Transfer Speed ................................................25
5 This Guideline Supports the Following Configurations.....................................................29
6 DDR3 Channel Signal Groups .....................................................................................30
7 Memory Channel Signals Groups Routing .....................................................................30
8 DQ/DQS Routing Guidelines and Settings for a Single Rank 4L Fly-by Design—PCB Type 3 .31
9 Control - Routing Guidelines and Settings for a Single Rank 4L Fly-by Design—PCB Type 3.33
10 Command Routing Guidelines and Settings for a Single Rank 4L Fly-by Design—PCB Type
3............................................................................................................................34
11 Clock Routing Guidelines and settings for a Single Rank 4L Fly-by Design—PCB Type 3 ......36
12 Precision Resistor Value for DDR3_xxxPU Compensation Inputs ......................................39
13 PCI Express* Root Ports Speed Support.......................................................................41
14 PCIe* Root Ports 1 and2 Supported Configurations .......................................................41
15 SoC PCI Express* Compensation and Voltage Reference Guidelines .................................43
16 PCI Express* Reference Documents ............................................................................43
17 PCI Express* Signal Groups (Standard Card)................................................................43
18 PCI Express* Card Topologies ....................................................................................43
19 PCI Express* Expansion Card Routing PET to Connector.................................................45
20 PCI Express* Expansion Card Routing PER to Connector ................................................46
21 Signal Groups ..........................................................................................................48
22 USB 2.0 External Routing Guidelines MicroUSB .............................................................50
23 USB 2.0 External Routing Guidelines Mini PCIe* ...........................................................51
24 I2C Signals ..............................................................................................................55
25 I2C* Signal Routing Summary....................................................................................56
26 Bus Capacitance Reference Chart................................................................................58
27 Example Bus Capacitance/Pull-Up Resistor Relationship .................................................58
28 SDIO Signals ...........................................................................................................59
29 SDIO Layout Guideline ..............................................................................................60
30 SOC SDIO Pull Up/Down............................................................................................61
31 UART Signals ...........................................................................................................63
32 UART Routing Guideline.............................................................................................64
33 UART Internal Pull Up/Down.......................................................................................64
34 SPI Signals ..............................................................................................................67
35 SPI0_MOSI, SPI0_SCK ..............................................................................................68
36 SPI0_MISO..............................................................................................................68
37 SPI1_MOSI, SPI1_SCK ..............................................................................................69
38 SPI1_MISO..............................................................................................................70
39 SOC SPI Internal Pull Up/ Pull Down............................................................................71
40 Signal Groups ..........................................................................................................74
41 Differential Clock Routing Guidelines ...........................................................................75
42 iClock (Single-ended Clocks) ......................................................................................77
43 SPI Signals ..............................................................................................................81
44 LSPI0_MOSI, LSPI0_MISO, LSPI_SS_B, LSPI0_SCK ......................................................82
45 RTC Signals .............................................................................................................85
46 RTC Routing Guidelines .............................................................................................87
47 RTC External RTCRST# Routing Guidelines...................................................................91
48 Asynchronous Legacy Signal Group.............................................................................93
49 Asynchronous Signal General Routing Guideline ...........................................................93
50 GPIO[7:0]l General Routing Guideline .........................................................................94
51 Recommended Platform Power Delivery.......................................................................97
52 Platform Reset Signals ............................................................................................ 101

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Contents—Intel®Quark™ SoC X1000
53 Critical Signals....................................................................................................... 105
54 Critical Signals Routing Summary............................................................................. 106
55 Frequency Sensitivity ............................................................................................. 106
56 Component Placement Review Checklist.................................................................... 125
57 General Routing Review Checklist............................................................................. 125
58 I/O Routing Review Checklist................................................................................... 126
59 Decoupling/Filtering Review Checklist ....................................................................... 126
60 Tested Sensitive Nets ............................................................................................. 134
61 ESD Checklist ........................................................................................................ 138
62 JTAG PullUp / PullDown Requirements....................................................................... 140
63 Bead Parameters ................................................................................................... 142
64 MDIO Data Signals on the Intel®Quark™ SoC X1000 ................................................. 146
65 RMII Signals.......................................................................................................... 146
66 Clock and Reset Signals .......................................................................................... 146
67 Integrated Magnetics Recommended Qualification Criteria ........................................... 148
68 MDI Routing Summary............................................................................................ 154
69 Maximum Trace Lengths Based on Trace Geometry and Board Stack-Up........................ 155
70 Capacitor Stuffing Option Recommended Values......................................................... 162
71 MAC0_TXDATA<1:0>; MAC0_TXEN; MAC0_MDC; MAC0_MDIO .................................... 165
72 MAC0_RXDATA<1:0>; MAC0_RXDV ......................................................................... 165
§ §

Intel®Quark™ SoC X1000—Revision History
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Revision History
§ §
Revision Description Date
002 Removed Section 4.1.7 Difference Between PCIe Ports and Lanes
Updated Figure 35 Clock Integration Distribution Diagram
Removed Section 11.3.2 Dual SPI Devices + Bootflash Topology Guidelines
Removed Section 21.17 Considerations for Layout
Removed Figure A-5 Example of Poor Length Matching
Removed Section A.4 General Differential Stackup Guidelines
Removed Section A.7 General Docking Connector Recommendations for Differential
Interfaces
Other changes are marked with change bars
June 2014
001 Initial Public Release March 2014

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Introduction—Intel®Quark™ SoC X1000
1.0 Introduction
This Design Guide provides motherboard implementation recommendations for a
platform based on the Intel®Quark™ SoC X1000 processor. The Intel®Quark™ SoC
X1000 Platform Design Guide has been developed to ensure maximum flexibility for
board designers while reducing the risk of board related issues. Design
recommendations are based on Intel’s simulations and lab experience and are strongly
recommended, if not necessary, to meet the timing and signal quality specifications.
Design recommendations are based on the reference platforms designed by Intel. They
should be used as an example but may not be applicable to particular designs.
The guidelines recommended in this document are based on experience, simulation,
and preliminary validation work done at Intel while developing the Intel®Quark™ SoC
X1000-based platform. This work is ongoing, and these recommendations are subject
to change. Metric units are used in some sections in addition to the standard use of
U.S. customary system of units (USCS). If there is a discrepancy between the metric
and USCS units, assume the USCS unit is most accurate. The conversion factor used is
1 inch (1000 mils) = 25.4 mm.

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1.1 Terminology
§ §
Figure 1. Intel®Quark™ SoC X1000 Block Diagram
Term Description
DPFT Dynamic Platform & Thermal Framework; includes configurable TDP and
Low Power Mode.
Intel® QuarkTM
Core
Host Bridge
Clock
eSRAM
DDR3
Memory
Controller
JTAG
Legacy Bridge
AMBA Fabric
PMC
GPIO
RTC
8254 8259
HPET
APIC
SPI
ROM
SDIO
UART
USB 2.0
I2C*/GPIO
PCIe*
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
I/O
10/100 ETH
I/O
SPI

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Stack-Up and PCB Considerations—Intel®Quark™ SoC X1000
2.0 Stack-Up and PCB Considerations
Note: Metric units are used in some sections in addition to the standard use of U.S.
customary system of units (USCS). If there is a discrepancy between the metric and
USCS units, assume the USCS unit is most accurate. The conversion factor used is 1
inch (1000 mils) = 25.4 mm.
2.1 Printed Circuit Board (PCB) Considerations
Several layer count configurations may be implemented on the platform, provided the
trace geometries of the individual microstrip and stripline routing layers fall within the
parameter value ranges and the impedance specifications are met. It is important to
note that variations in the stack-up of a motherboard, such as changes in the dielectric
height, trace widths, and spacing, can impact the impedance, loss, and jitter
characteristics of all the interfaces. Such changes may either be intentional or the
result of variations encountered during the PCB manufacturing process. In either case,
they must be properly considered when designing interconnects.
The following figures depict the set of geometry metrics associated with the external
(microstrip) routing and dual-stripline routing layers for both single-ended and
differential signals. The typical values and simulation sweep ranges for each parameter
are defined in the following tables. If motherboard parameters (including
manufacturing variances) fall outside of the boundaries shown, perform additional
simulations to ensure proper signal integrity and specification compliance.
• Design tolerances account for adjustments intentionally included in their design.
• Material tolerances account for any natural variation in the materials being used.
• Manufacturing tolerance considers variations that may occur during the
manufacturing process.
• Use the design tolerance to recenter stack-up impedance, but consider the
manufacturing tolerance impact when comparing the chosen stack-up to the given
recommendation.
The typical values, including the design and material tolerances, are centered around a
nominal single line impedance specification of 50 ±15% for microstrip. Many
interfaces specify a different nominal single-ended impedance. For more details on the
nominal trace width to hit those impedance targets, refer to the individual interface
section.
The following general stack-up recommendations should be followed:
• Microstrip layers are assumed to be built from ½ oz. foil, plated up nominally
another 1 oz., however, the trace thickness range defined allows for significant
process variance around this nominal.
•BasedonIntel
®Galileo layout layers 3/4 dual stripline assumed to be built from
1oz. copper.
• All high-speed signals should reference solid planes over the length of their routing
and should not cross plane splits. Ground referencing is preferred.

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• Reference plane stitching vias must be used in conjunction with high-speed signal
layer transitions that include a reference plane change. Refer to each signal group
section for more specification.
• The parameter values for internal and external traces are the final thickness and
width after the motherboard materials are laminated, conductors plated, and
etched. Intel uses these exact values to generate the associated electrical models
for simulation.
Figure 2. Single-Ended Microstrip Diagram
Figure 3. Differential-Microstrip Diagram
Table 1. Platform Stack-up Parameter Values (Microstrip) (Sheet 1 of 2)
Microstrip Units Min
Value
- Manufac-
turing
Tolerance
- Design/
Material
Tolerance
Typical
Value
+ Design/
Material
Tolerance
+ Manufac-
turing
Tolerance
Max
Value
D1 mils 2.05 0.3 0.4 2.75 0.2 0.3 3.25
D2 mils 0.1 0.3 0.25 0.65 0.25 0.30 1.20
r1 NA 3.45 0.15 0.3 3.9 0.3 0.15 4.35
r2 NA 3.20 0.2 0 3.40 0 0.2 3.60
Trace Thickness
(0.5 oz. Plated) mils 1.30 0.28 0.32 1.90 0.32 0.28 2.50
Microstrip
Power/GND Plane
WD1
T
Pair to pair pitch
r2
r1
Pitch D2

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Stack-Up and PCB Considerations—Intel®Quark™ SoC X1000
2.2 Low Halogen Flame Retardant Stack-Up Considerations
2.2.1 Low Halogen Background
FR4 epoxy has been used in the construction of PCBs for decades. Consequently, its
electrical properties, which are influenced by brominated flame retardants integrated
into the molecular structure of the resin, have been studied extensively. As an
environmentally friendly alternative to the halogenated flame retardants in FR4,
several new low halogen (LH) formulations were developed by different material
suppliers. Unfortunately, each new formulation has a unique electrical performance that
differs from FR4. This leads to the current problem: The critical electrical properties of
many LH dielectrics currently on the market make it difficult to design high-speed
buses without increasing the cost of the system. The range of supported Er values
therefore limits the amount of cost added.
The most apparent problem lies with the increased permittivity of the LH dielectric
materials compared to FR4. Measurements show that several LH PCB materials on the
market can have permittivity values around 5 at 1 GHz (using 1080 glass), while FR4
has permittivity values in the 3.6 - 3.9 range. Increased permittivity requires thicker
dielectric layers to achieve the equivalent impedance as FR4. In turn, the thicker
dielectric layers lead to an increase in crosstalk which reduces bus performance. If the
trace-trace spacing and line widths remain constant (consequently board area
consumed remains constant), and the dielectric thickness is adjusted to maintain
constant characteristic impedance, the bus performance is reduced for high permittivity
values due to increased crosstalk.
Conventional means of reducing crosstalk is to isolate traces as much as practical to
reduce the electromagnetic coupling of energy. Unfortunately, modern motherboard
designs are often real-estate constrained, requiring extra layers (and therefore cost) to
provide additional space for crosstalk compensation when using high permittivity
dielectrics.
2.2.2 Choosing a Low Halogen Material
Choosing an LH dielectric material for a specific design requires a compromise between
performance and cost, especially when a single design is required to work with both LH
and FR4 PCB materials. Consequently, it is impossible to define universal requirements
for LH dielectrics that will be adequate for all products on the market. Generally
speaking however, the dielectric materials used to design printed circuit boards (PCBs)
with high-speed digital interfaces perform better with low permittivity and low losses.
Low permittivity tends to reduce crosstalk noise for given impedance and low loss
tangents reduce signal attenuation.
2.2.3 Electrical Limits of Low Halogen Material Properties
Although it is impossible to define electrical limits to universally select “good” materials
versus “bad” materials because each design is unique in its implementation, general
limits can be chosen that will be adequate for most applications. Simulations were
Trace Width
(Bottom) mils 3.1 0.40 0.5 4.00 0.25 0.40 4.65
Trace Width
(Top) mils 2.1 0.40 0.5 3.00 0.25 0.40 3.65
Table 1. Platform Stack-up Parameter Values (Microstrip) (Sheet 2 of 2)
Microstrip Units Min
Value
- Manufac-
turing
Tolerance
- Design/
Material
Tolerance
Typical
Value
+ Design/
Material
Tolerance
+ Manufac-
turing
Tolerance
Max
Value

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performed on several high-speed buses and validation platforms were built to help
identify electrical limits of LH materials that will help ensure 1) adequate bus
performance and 2) interchangeability between FR4 and LH material. The layout
constraints listed in this document have been designed to function with both standard
FR4 and LH materials if the electrical properties of the LH materials fall within the
envelope defined by Ta b l e 2 .
Note: Approximate limits of desired electrical performance of LH dielectric materials; RC =% Resin Content,
RH = Relative Humidity; 1080 stackups have between ~ 60-65% resin content depending on the layer
thickness; Limits established using buses implemented on 1080 material. 2116 (RC=45%) and
RC=50% limits extrapolated from the 1080 data points using the volume ratio of resin to glass and
average values of resin density, glass density, glass permittivity, glass tan and glass weight basis.
Although the limits listed in Ta b l e 2 are generally lower performance than standard
FR4, simulated and measured data indicate that they are sufficient to ensure proper
functionality of the buses listed in this design guide. Since the volume of LH materials
on the market is small compared to FR4, the performance envelope was made as large
as practical to maximize the number of LH materials that comply without significantly
sacrificing signal integrity. Ta b l e 2 does not guarantee equal performance to FR4.
However, if the limits are adhered to, then the risk of signal integrity problems due to
the LH material is greatly reduced. Intel bases signal integrity analysis and validation
on these ranges.
Designers should also ensure the LH dielectric materials chosen meet all applicable
thermal, mechanical and UL flammability requirements.
2.3 Reference Planes
• Reference all signal routing layers to a solid ground plane that is continuous over
the length of the interconnect. Specific requirements may be defined within the
interface design guideline chapters.
• Using a power layer as a reference plane is allowed if the power layer is low noise
and there is proper decoupling stitching at reference planes transitions to
guarantee high frequency return path continuity. However, this should only be
considered as the secondary reference plane on internal layers where a solid
continuous ground reference is already present. Even in this case the power plane
must be low noise due to the possibility of noise being coupled into the associated
signal planes.
• Route noisy power planes, such as VBAT, on the same layers as signals to minimize
fringe coupling by proper spacing separation.
2.4 Backward and Forward Coupling Coefficient Calculation
Some designs require a stack-up build that is outside of the ranges provided. In this
case, compare the routing electrical characteristics versus the Intel recommendation.
Table 2. Electrical Limits of LH Material Properties
Parameter Approximate LH Electrical Limits Environmental Condition
Permittivity (Er)
<4.2 (1080, RC~61%)
<4.3 (RC~50%)
<4.5 (2116, RC~45%)
Any environmental conditions
Loss Tangent (tan)
<0.018 (1080, RC~61%)
<0.014 (1080, RC~50%)
<0.013 (2116, RC~45%)
50% RH & 75oF
Moisture Impact on Loss (tan)
<0.024(1080, RC~61%)
<0.019(RC=50%)
<0.017 (2116, RC~45%)
95% RH & 95oF