Intel E5345 - Xeon 2.33 GHz 8M L2 Cache 1333MHz FSB LGA771 Active Quad-Core... User manual

Order Number: 315338-020
Notice: The Intel® Xeon® Processor 5300 Series may contain design defects or errors known as errata which
may cause the product to deviate from published specifications. Current characterized errata are available on
request.
Intel® Xeon® Processor 5300 Series
Specification Update
December 2010

2Intel® Xeon® Processor 5300 Series
Specification Update, December 2010
Legal Lines and Disclaimers
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL®PRODUCTS. EXCEPT AS PROVIDED IN INTEL'S
TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR
WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT,
COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT.
Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility
applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them.
The Intel®Xeon® Processor 5300 Series may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor
(VMM). Functionality, performance or other benefits will vary depending on hardware and software configurations. Software
applications may not be compatible with all operating systems. Consult your PC manufacturer. For more information, visit http://
www.intel.com/go/virtualization
Requires an Intel® HT Technology enabled system, check with your PC manufacturer. Performance will vary depending on the
specific hardware and software used. Not available on Intel® Core™ i5-750. For more information including details on which
processors support HT Technology, visit http://www.intel.com/info/hyperthreading
64-bit Intel®Xeon®processors with Intel®64 requires a computer system with a processor, chipset, BIOS, OS, device drivers and
applications enabled for Intel®64. Processor will not operate (including 32-bit operation) without an Intel®64-enabled BIOS.
Performance will vary depending on your hardware and software configurations. Intel®64-enabled OS, BIOS, device drivers and
applications may not be available. Check with your vendor for more information
See the Processor Spec Finder at http://ark.intel.com or contact your Intel representative for more information.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be
obtained by calling 1-800-548-4725 or by visiting Intel's website at http://developer.intel.com/products/index.htm.
Intel, Pentium, Pentium III, Xeon, Celeron, the Intel logo and Intel NetBurst are trademarks of Intel Corporation in the U. S. and
other countries.
Copyright © 2010, Intel Corporation. All rights reserved.
*Other names and brands may be claimed as the property of others.

Contents
Intel® Xeon® Processor 5300 Series 3
Specification Update, December 2010
Contents
Revision History ........................................................................................................4
Preface......................................................................................................................5
Summary Tables of Changes......................................................................................7
Identification Information.......................................................................................17
Errata...................................................................................................................... 19
Specification Changes.............................................................................................. 53
Specification Clarifications ...................................................................................... 54
Documentation Changes..........................................................................................55

4Intel® Xeon® Processor 5300 Series
Specification Update, December 2010
Revision History
Revision Version Description Date
-001 1.0 Initial Release November 2006
-002 1.0 Deleted AJ83 and AJ87. Added AJ86 through AJ89. December 2006
-003 1.0 Updated AJ67. Added AJ90 through AJ93. January 2006
-004 1.0 Updated AJ46. Added AJ94 through AJ100. Deleted AJ82 and
AJ84. March 2007
-005 1.0 Added AJ101 through AJ103. April 2007
-006 1.0 Added AJ104 and Specification Clarification AJ1 April 2007
Out of Cycle
-007 1.0 Updated AJ14, AJ25 and AJ26 May 2007
-008 1.0 Added AJ105 and AJ106 June 2007
-009 1.0 Added AJ107 and AJ108 July 2007
-010 1.0 Added AJ109 through AJ111
Added G-0 Information August 2007
-011 1.0 Added AJ112 through AJ117, Updated AJ108 October 2007
-012 1.0 Added AJ118 November 2007
-013 1.0 Added AJ119. Updated AJ8
Added L5318 Information December 2007
-014 1.0 Added AJ120 January 2008
-015 1.0 Added AJ121
Updated AJ10 and AJ51 February 2008
-016 1.0 Added AJ122 through AJ123 April 2008
-017 1.0 Update errata AJ56 and AJ61 March 2009
-018 1.0 Added errata AJ124 and AJ125
Added Specification Change AJ1 July 2009
-019 1.0 Added errata AJ126 March 2010
-020 1.0 Added errata AJ127, deleted AJ1 December 2010

Intel® Xeon® Processor 5300 Series 5
Specification Update, December 2010
Preface
This document is an update to the specifications contained in the Affected Documents
table below. This document is a compilation of device and documentation errata,
specification clarifications and changes. It is intended for hardware system
manufacturers and software developers of applications, operating systems, or tools.
Information types defined in Nomenclature are consolidated into the specification
update and are no longer published in other documents.
This document may also contain information that was not previously published.
Affected Documents
Note: Contact your Intel representative for the latest revision and document number of this document.
Related Documents
Note: Contact your Intel representative for the latest revision and document number of this document.
Nomenclature
Errata are design defects or errors. These may cause the Intel® Xeon® Processor
5300 Series behavior to deviate from published specifications. Hardware and software
designed to be used with any given stepping must assume that all errata documented
for that stepping are present on all devices.
S-Spec Number is a five-digit code used to identify products. Products are
differentiated by their unique characteristics,e.g., core speed, L2 cache size, package
type, etc. as described in the processor identification information table. Read all notes
associated with each S-Spec number.
Document Title Document Number/
Location
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 315569
Document Title Document Number/
Location
AP-485, Intel® Processor Identification and the CPUID Instruction 241618
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1:
Basic Architecture
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A:
Instruction Set Reference Manual A-M
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B:
Instruction Set Reference Manual N-Z
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A:
System Programming Guide
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B:
System Programming Guide
Intel® 64 and IA-32 Intel Architecture Optimization Reference Manual
http://www.intel.com/
products/processor/
manuals/index.htm
Intel® 64 and IA-32 Architectures Software Developer’s Manual
Documentation Changes
http://www.intel.com/
design/processor/specupdt/
252046.htm
Intel® Virtualization Technology Specification for the IA-32 Intel® Architecture C97063

6Intel® Xeon® Processor 5300 Series
Specification Update, December 2010
Specification Changes are modifications to the current published specifications.
These changes will be incorporated in any new release of the specification.
Specification Clarifications describe a specification in greater detail or further
highlight a specification’s impact to a complex design situation. These clarifications will
be incorporated in any new release of the specification.
Documentation Changes include typos, errors, or omissions from the current
published specifications. These will be incorporated in any new release of the
specification.
Note: Errata remain in the specification update throughout the product’s lifecycle, or until a
particular stepping is no longer commercially available. Under these circumstances,
errata removed from the specification update are archived and available upon request.
Specification changes, specification clarifications and documentation changes are
removed from the specification update when the appropriate changes are made to the
appropriate product specification or user documentation (datasheets, manuals, and so
forth).

Intel® Xeon® Processor 5300 Series 7
Specification Update, December 2010
Summary Tables of Changes
The following tables indicate the errata, specification changes, specification
clarifications, or documentation changes which apply to the Intel® Xeon® Processor
5300 Series product. Intel may fix some of the errata in a future stepping of the
component, and account for the other outstanding issues through documentation or
specification changes as noted. These tables uses the following notations:
Codes Used in Summary Tables
Stepping
X: Errata exists in the stepping indicated. Specification Change or
Clarification that applies to this stepping.
(No mark)
or (Blank box): This erratum is fixed in listed stepping or specification change
does not apply to listed stepping.
Page
(Page): Page location of item in this document.
Status
Doc: Document change or update will be implemented.
Plan Fix: This erratum may be fixed in a future stepping of the product.
Fixed: This erratum has been previously fixed.
No Fix: There are no plans to fix this erratum.
Row
Each Specification Update item is prefixed with a capital letter to distinguish the
product. The key below details the letters that are used in Intel’s microprocessor
Specification Updates:
A = Intel® Xeon® processor 7000 sequence
C = Intel® Celeron® processor
D = Intel® Xeon® processor 2.80 GHz
E = Intel® Pentium® III processor
F = Intel® Pentium® processor Extreme Edition and Intel® Pentium®D processor
I = Intel® Xeon® processor 5000 series
J = 64-bit Intel® Xeon® processor MP with 1MB L2 cache
K = Mobile Intel® Pentium® III processor

8Intel® Xeon® Processor 5300 Series
Specification Update, December 2010
L = Intel® Celeron® D processor
M = Mobile Intel® Celeron® processor
N = Intel® Pentium® 4 processor
O = Intel® Xeon® processor MP
P = Intel ® Xeon® processor
Q = Mobile Intel® Pentium® 4 processor supporting Intel® Hyper-Threading Technology
on 90-nm process technology
R = Intel® Pentium® 4 processor on 90 nm process
S = 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache
versions)
T = Mobile Intel® Pentium® 4 processor-M
U = 64-bit Intel® Xeon® processor MP with up to 8MB L3 cache
V = Mobile Intel® Celeron® processor on .13 micron process in Micro-FCPGA package
W= Intel® Celeron® M processor
X = Intel® Pentium® M processor on 90nm process with 2-MB L2 cache and Intel®
processor A100 and A110 with 512-KB L2 cache
Y = Intel® Pentium® M processor
Z = Mobile Intel® Pentium® 4 processor with 533 MHz system bus
AA = Intel® Pentium® D processor 900 sequence and Intel® Pentium® processor
Extreme Edition 955, 965
AB = Intel® Pentium® 4 processor 6x1 sequence
AC = Intel® Celeron® processor in 478 pin package
AD = Intel® Celeron® D processor on 65nm_process
AE = Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65nm process
AF = Intel® Xeon® processor LV
AG = Intel® Xeon® processor 5100 series
AH = Intel® Core™2 Duo/Solo Processor for Intel® Centrino® Duo Processor Technology
AI = Intel® Core™2 Extreme processor X6800? and Intel® Core™2 Duo desktop proces-
sor E6000 and E4000? sequence
AJ = Intel® Xeon® processor 5300 series

Intel® Xeon® Processor 5300 Series 9
Specification Update, December 2010
AK = Intel® Core™2 Extreme quad-core processor QX6000? sequence and Intel® Core™2
Quad processor Q6000 sequence
AL = Intel® Xeon® processor 7100 series
AM = Intel® Celeron® processor 400 sequence
AN = Intel® Pentium® dual-core processor
AO = Intel® Xeon® processor 3200 series
AP = Intel® Xeon® processor 3000 series
AQ = Intel® Pentium® dual-core desktop processor E2000 sequence
AR = Intel® Celeron processor 500 series
AS = Intel® Xeon® processor 7200, 7300 series
AT = Intel® Celeron® processor 200 series
AV = Intel® Core™2 Extreme processor QX9000 series and Intel® Core™2 Quad proces-
sor Q9000 series
AX = Intel® Xeon® processor 5400 series
AY = Intel® Xeon® processor 5200 series
AZ = Intel® Core™2 Duo Processor and Intel® Core™2 Extreme Processor on 45-nm Pro-
cess
AAA= Intel® Xeon® processor 3300 series
AAB= Intel® Xeon® E3110 Processor
AAC= Intel® Celeron® dual-core processor E1000 series
AAD= Intel® Core™2 Extreme Processor QX9775
AAE= Intel® Atom™ processor Z5xx series
AAF= Intel® Atom™ processor 200 series

10 Intel® Xeon® Processor 5300 Series
Specification Update, December 2010
Errata (Sheet 1 of 6)
Number Steppings Status ERRATA
B-3 G-0
AJ1 Deleted
AJ2 X X No Fix LOCK# Asserted During a Special Cycle Shutdown Transaction May
Unexpectedly De-assert
AJ3 X X No Fix Address Reported by Machine-Check Architecture (MCA) on Single-
bit L2 ECC Errors May be Incorrect
AJ4 X X No Fix VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the
Last Exception Record (LER) MSR
AJ5 X X No Fix DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store
Instruction May Incorrectly Increment Performance Monitoring Count
for Saturating SIMD Instructions Retired (Event CFH)
AJ6 X Plan Fix SYSRET May Incorrectly Clear RF (Resume Flag) in the RFLAGS
Register
AJ7 X X No Fix General Protection Fault (#GP) for Instructions Greater than 15 Bytes
May be Preempted
AJ8 X X No Fix Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced
Before Higher Priority Interrupts
AJ9 X X No Fix The Processor May Report a #TS Instead of a #GP Fault
AJ10 X X No Fix Code Segment Limit/Canonical Faults on RSM May be Serviced
before Higher Priority Interrupts/Exceptions
AJ11 X X No Fix A Write to an APIC Register Sometimes May Appear to Have Not
Occurred
AJ12 X X No Fix Programming the Digital Thermal Sensor (DTS) Threshold May Cause
Unexpected Thermal Interrupts
AJ13 X X No Fix Count Value for Performance-Monitoring Counter PMH_PAGE_WALK
May be Incorrect
AJ14 X X No Fix LER MSRs May be Incorrectly Updated
AJ15 X X No Fix Performance Monitoring Events for Retired Instructions (C0H) May
Not Be Accurate
AJ16 X X No Fix Performance Monitoring Event For Number Of Reference Cycles
When The Processor Is Not Halted (3CH) Does Not Count According
To The Specification
AJ17 X X No Fix Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect
Address Translations
AJ18 X X No Fix Writing Shared Unaligned Data that Crosses a Cache Line without
Proper Semaphores or Barriers May Expose a Memory Ordering
Issue
AJ19 X X No Fix Code Segment limit violation may occur on 4-Gbyte limit check
AJ20 X Plan Fix FP Inexact-Result Exception Flag May Not Be Set
AJ21 X Plan Fix Global Pages in the Data Translation Look-Aside Buffer (DTLB) May
Not Be Flushed by RSM instruction before Restoring the Architectural
State from SMRAM
AJ22 X Plan Fix Sequential Code Fetch to Non-canonical Address May have Non-
deterministic Results

Intel® Xeon® Processor 5300 Series 11
Specification Update, December 2010
AJ23 X Plan Fix VMCALL to Activate Dual-monitor Treatment of SMIs and SMM
Ignores Reserved Bit settings in VM-exit Control Field
AJ24 X X No Fix The PECI Controller Resets to the Idle State
AJ25 X X No Fix Some Bus Performance Monitoring Events May Not Count Local
Events under Certain Conditions
AJ26 X X No Fix Premature Execution of a Load Operation Prior to Exception Handler
Invocation
AJ27 X X No Fix General Protection (#GP) Fault May Not Be Signaled on Data
Segment Limit Violation above 4-G Limit
AJ28 X X No Fix EIP May be Incorrect after Shutdown in IA-32e Mode
AJ29 X X No Fix #GP Fault is Not Generated on Writing IA32_MISC_ENABLE [34]
When Execute Disable Bit is Not Supported
AJ30 X Plan Fix (E)CX May Get Incorrectly Updated When Performing Fast String
REP MOVS or Fast String REP STOS With Large Data Structures
AJ31 X Plan Fix Performance Monitoring Events for Retired Loads (CBH) and
Instructions Retired (C0H) May Not Be Accurate
AJ32 X X No Fix Upper 32 bits of 'From' Address Reported through BTMs or BTSs May
be Incorrect
AJ33 X Plan Fix Unsynchronized Cross-Modifying Code Operations Can Cause
Unexpected Instruction Execution Results
AJ34 X X No Fix MSRs Actual Frequency Clock Count (IA32_APERF) or Maximum
Frequency Clock Count (IA32_MPERF) May Contain Incorrect Data
after a Machine Check Exception (MCE)
AJ35 X X No Fix Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR
Image Leads to Partial Memory Update
AJ36 X X No Fix Split Locked Stores May not Trigger the Monitoring Hardware
AJ37 X Plan Fix REP CMPS/SCAS Operations May Terminate Early in 64-bit Mode
when RCX >= 0X100000000
AJ38 X Plan Fix FXSAVE/FXRSTOR Instructions which Store to the End of the
Segment and Cause a Wrap to a Misaligned Base Address (Alignment
<= 0x10h) May Cause FPU Instruction or Operand Pointer Corruption
AJ39 X Plan Fix Cache Data Access Request from One Core Hitting a Modified Line in
the L1 Data Cache of the Other Core May Cause Unpredictable
System Behavior
AJ40 X Plan Fix PREFETCHh Instruction Execution under Some Conditions May Lead
to Processor Livelock
AJ41 X Plan Fix PREFETCHh Instructions May Not be Executed when Alignment
Check (AC) is Enabled
AJ42 X Plan Fix Upper 32 Bits of the FPU Data (Operand) Pointer in the FXSAVE
Memory Image May Be Unexpectedly All 1's after FXSAVE
AJ43 X Plan Fix Concurrent Multi-processor Writes to Non-dirty Page May Result in
Unpredictable Behavior
AJ44 X Plan Fix Performance Monitor IDLE_DURING_DIV (18h) Count May Not be
Accurate
AJ45 X X No Fix Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM
AJ46 X X No Fix ShutdownCondition May Disable Non-Bootstrap Processors
Errata (Sheet 2 of 6)
Number Steppings Status ERRATA
B-3 G-0

12 Intel® Xeon® Processor 5300 Series
Specification Update, December 2010
AJ47 X Plan Fix SYSCALL Immediately after Changing EFLAGS.TF May Not Behave
According to the New EFLAGS.TF
AJ48 X Plan Fix Debug Register May Contain Incorrect Information on a MOVSS or
POPSS Instruction Followed by SYSRET
AJ49 X X No Fix VM Bit is Cleared on Second Fault Handled by Task Switch from
Virtual-8086 (VM86)
AJ50 X Plan Fix IA32_FMASK is Reset during an INIT
AJ51 X X No Fix Code Breakpoint May Be Taken after POP SS Instruction if it is
followed by an Instruction that Faults
AJ52 X X No Fix Last Branch Records (LBR) Updates May be Incorrect after a Task
Switch
AJ53 X X No Fix IO_SMI Indication in SMRAM State Save Area May Be Set Incorrectly
AJ54 X X No Fix INIT Does Not Clear Global Entries in the TLB
AJ55 X Plan Fix Using Memory Type Aliasing with Memory Types WB/WT May Lead to
Unpredictable Behavior
AJ56 X No Fix Update of Read/Write (R/W) or User/Supervisor (U/S) or Present (P)
Bits without TLB Shootdown May Cause Unexpected Processor
Behavior
AJ57 X No Fix BTS Message May Be Lost When the STPCLK# Signal is Active.
AJ58 X X No Fix CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or
Equal to 248 May Terminate Early
AJ59 X X No Fix REP MOVS/STOS Executing with Fast Strings Enabled and Crossing
Page Boundaries with Inconsistent Memory Types may use an
Incorrect Data Size or Lead to Memory-Ordering Violations
AJ60 X X No Fix MOV To/From Debug Registers Causes Debug Exception
AJ61 X X No Fix EFLAGS Discrepancy on Page Faults after a Translation Change
AJ62 X X No Fix LBR, BTS, BTM May Report a Wrong Address when an Exception/
Interrupt Occurs in 64-bit Mode
AJ63 X X No Fix Returning to Real Mode from SMM with EFLAGS.VM Set May Result
in Unpredictable System Behavior
AJ64 X X No Fix A Thermal Interrupt is Not Generated when the Current Temperature
is Invalid
AJ65 X X No Fix Performance Monitoring Event FP_ASSIST May Not be Accurate
AJ66 X Plan Fix CPL-Qualified BTS May Report Incorrect Branch-From Instruction
Record From Address
AJ67 X Plan Fix PEBS Does Not Always Differentiate Between CPL-Qualified Events
AJ68 X X No Fix PMI May be Delayed to Next PEBS Event
AJ69 X Plan Fix PEBS Buffer Overflow Status Will Not be Indicated Unless
IA32_DEBUGCTL[12] is Set
AJ70 X X No Fix The BS Flag in DR6 May be Set for Non-Single-Step #DB Exception
AJ71 X X No Fix An Asynchronous MCE During a Far Transfer May Corrupt ESP
AJ72 X Plan Fix In Single-Stepping on Branches Mode, the BS Bit in the Pending-
Debug-Exceptions Field of the Guest State Area will be Incorrectly Set
by VM-Exit on a MOV to CR8 Instruction
Errata (Sheet 3 of 6)
Number Steppings Status ERRATA
B-3 G-0

Intel® Xeon® Processor 5300 Series 13
Specification Update, December 2010
AJ73 X X No Fix B0-B3 Bits in DR6 May Not be Properly Cleared After Code
Breakpoint
AJ74 X X No Fix Performance Monitoring Events for L1 and L2 Miss May Not be
Accurate
AJ75 X X No Fix BTM/BTS Branch-From Instruction Address May be Incorrect for
Software Interrupts
AJ76 X Plan Fix VMLAUNCH/VMRESUME May Not Fail when VMCS is Programmed
to Cause VM Exit to Return to a Different Mode
AJ77 X X No Fix Performance Monitor SSE Retired Instructions May Return Incorrect
Values
AJ78 X Plan Fix REP Store Instructions in a Specific Situation may cause the
Processor to Hang
AJ79 X X No Fix A MOV Instruction from CR8 Register with 16 Bit Operand Size Will
Leave Bits 63:16 of the Destination Register Unmodified
AJ80 X X No Fix Store to WT Memory Data May be Seen in Wrong Order by Two
Subsequent Loads
AJ81 X X No Fix IRET under Certain Conditions May Cause an Unexpected Alignment
Check Exception
AJ82 Removed - Not Applicable
AJ83 X X No Fix Non-Temporal Data Store May be Observed in Wrong Program Order
AJ84 Removed - Not Applicable
AJ85 X Plan Fix CPUID Reports Architectural Performance Monitoring Version 2 is
Supported, When Only Version 1 Capabilities are Available
AJ86 X X No Fix Unaligned Accesses to Paging Structures May Cause the Processor
to Hang
AJ87 X X No Fix Microcode Updates Performed During VMX Non-root Operation Could
Result in Unexpected Behavior
AJ88 X X No Fix INVLPG Operation for Large (2M/4M) Pages May be Incomplete
under Certain Conditions
AJ89 X X No Fix Page Access Bit May be Set Prior to Signaling a Code Segment Limit
Fault
AJ90 X Plan Fix Update of Attribute Bits on Page Directories without Immediate TLB
Shootdown May Cause Unexpected Processor Behavior
AJ91 X Plan Fix Invalid Instructions May Lead to Unexpected Behavior
AJ92 X X No Fix EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect after
Shutdown
AJ93 X Plan Fix Performance Monitoring Counter MACRO_INSTS.DECODED May
Not Count Some Decoded Instructions
AJ94 X Plan Fix The Stack Size May be Incorrect as a Result of VIP/VIF Check on
SYSEXIT and SYSRET
AJ95 X X No Fix Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL is
Counted Incorrectly for PMULUDQ Instruction
AJ96 X X No Fix Storage of PEBS Record Delayed Following Execution of MOV SS or
STI
Errata (Sheet 4 of 6)
Number Steppings Status ERRATA
B-3 G-0

14 Intel® Xeon® Processor 5300 Series
Specification Update, December 2010
AJ97 X Plan Fix Processor On Die Termination of BR1# and LOCK# Signals are
Incorrect
AJ98 X X No Fix Store Ordering May be Incorrect between WC and WP Memory Types
AJ99 X X No Fix Updating Code Page Directory Attributes without TLB Invalidation May
Result in Improper Handling of Code #PF
AJ100 X X No Fix Performance Monitoring Event CPU_CLK_UNHALTED.REF May Not
Count Clock Cycles According to the Processors Operating Frequency
AJ101 X Plan Fix Performance Monitoring Event BR_INST_RETIRED May Count CPUID
Instructions as Branches
AJ102 X X No Fix Performance Monitoring Event MISALIGN_MEM_REF May Over Count
AJ103 X X No Fix A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent
Triggering of the Monitoring Hardware
AJ104 X Plan Fix False Level One Data Cache Parity Machine-Check Exceptions May be
Signaled
AJ105 X X No Fix A Memory Access May Get a Wrong Memory Type Following a #GP due
to WRMSR to an MTRR Mask
AJ106 X X No Fix PMI While LBR Freeze Enabled May Result in Old/Out-of-date LBR
Information
AJ107 X Plan Fix Overlap of an Intel® VT APIC Access Page in a Guest with the DS
Save Area May Lead to Unpredictable Behavior
AJ108 X X No Fix Dual-Processor Incompatibility Between B-step and G-step
AJ109 X X No Fix VTPR Write Access During Event Delivery May Cause an APIC-Access
VM Exit
AJ110 X No Fix BIST Failure After Reset
AJ111 X X No Fix Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not
Count Some Transitions
AJ112 X X No Fix Instruction Fetch May Cause a Livelock During Snoops of the L1 Data
Cache
AJ113 X X No Fix Use of Memory Aliasing with Inconsistent Memory Type may Cause a
System Hang or a Machine Check Exception
AJ114 X X No Fix A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to
Memory-Ordering Violations
AJ115 X X No Fix VM Exit with Exit Reason “TPR Below Threshold” Can Cause the Blocking by MOV/POP SS and Blocking by STI Bits to be Cleared in the
Guest Interruptibility-State Field
AJ116 X X No Fix Using Memory Type Aliasing with cacheable and WC Memory Types
May Lead to Memory Ordering Violations
AJ117 X X No Fix VM Exit due to Virtual APIC-Access May Clear RF
AJ118 X X No Fix RSM Instruction Execution under Certain Conditions May Cause
Processor Hang or Unexpected Instruction Execution Results
AJ119 X Fixed NMIs May Not Be Blocked by a VM-Entry Failure
AJ120 X X No Fix Benign Exception after a Double Fault May Not Cause a Triple Fault
Shutdown
AJ121 X X No Fix IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine Check Error
Reporting Enable Correctly
AJ122 X X No Fix A VM Exit Due to a Fault While Delivering a Software Interrupt May
Save Incorrect Data into the VMCS
Errata (Sheet 5 of 6)
Number Steppings Status ERRATA
B-3 G-0

Intel® Xeon® Processor 5300 Series 15
Specification Update, December 2010
AJ123 X X No Fix A VM Exit Occurring in IA-32e Mode May Not Produce a VMX Abort
When Expected
AJ124 X X No Fix Not-Present Page Faults May Set the RSVD Flag in the Error Code
AJ125 X X No Fix VM Exits Due to “NMI-Window Exiting” May Be Delayed by One
Instruction
AJ126 X X No Fix FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit
Address Size in 64-bit Mode
AJ127 X X No Fix A 64-bit Register IP-relative Instruction May Return Unexpected
Results
Specification Changes
Number SPECIFICATION CHANGES
AJ1 Implementation of System Management Range Registers
Specification Clarifications
No. SPECIFICATION CLARIFICATIONS
AJ1 Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation
Documentation Changes
No. DOCUMENTATION CHANGES
None for this revision of this specification update.
Errata (Sheet 6 of 6)
Number Steppings Status ERRATA
B-3 G-0

16 Intel® Xeon® Processor 5300 Series
Specification Update, December 2010
Identification Information
Component Identification via Programming Interface
The Quad-Core Intel® Xeon® Processor 5300 Series stepping can be identified by the
following register contents:
Note:
1. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register
after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the
Device ID register accessible through Boundary Scan.
2. The Model corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX register after
the CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID
register accessible through Boundary Scan.
Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX
registers after the CPUID instruction is executed with a 2 in the EAX register.
Component Marking Information
The Quad-Core Intel® Xeon® Processor 5300 Series stepping can be identified by the
following component markings:
Family1Model2
0110 1111
Figure 1. Processor Top-side Markings (Example)
ATPO
S/N
ATPO
S/N
GROUP1LINE1
GROUP1LINE2
GROUP1LINE3
GROUP1LINE4
GROUP1LINE5
LOT NO
S/N
Legend:
GROUP1LINE1
GROUP1LINE2
GROUP1LINE3
GROUP1LINE4
GROUP1LINE5
Mark Text (Production Mark):
2.66GHZ/8M/1333
Intel ® Xeon®
SXXX XXXXX
i (M) © ’05 x53XX
(FPO)
Table 1. Intel® Xeon® Processor 5300 Series Identification Information (Sheet 1 of
2)
S-Spec Processor Number Core Stepping CPUID Core
Freq
(GHz)
Data Bus
Freq
(MHz)
L2
Cache
Size
Processor
Package
Revision Notes
SL9YM X5355 B-3 06F7 2.66 1333 8M 01 1,23,6,7,8,9
SLAC4 X5355 B-3 06F7 2.66 1333 8M 01 1,23,6,7,8,9
SL9YL E5345 B-3 06F7 2.33 1333 8M 01 1,24,6,7,8,9

Intel® Xeon® Processor 5300 Series 17
Specification Update, December 2010
Notes:
1. Intel® Xeon® Processor 5300 Series supports a Land Grid Array package with 771 lands in a 37.55 x
37.55 mm FC-LGA6 package
2. Refer to the Intel® Xeon® Processor 5300 Series Datasheet for the VID values for these processors.
3. This is a Intel® Xeon® Processor 5300 Series with a 120W TDP (Thermal Design Power)
4. This is a Intel® Xeon® Processor 5300 Series with a 80W TDP (Thermal Design Power)
5. This is a Intel® Xeon® Processor 5300 Series with a 50W TDP (Thermal Design Power)
6. These parts are enabled for Enhanced Intel SpeedStep® Technology.
7. These parts are enabled for Enhanced Halt State (C1E).
8. These parts have Execute Disable bit functionality.
9. These parts have Intel® Virtualization Technology (Intel® VT) enabled.
10. This is a Intel® Xeon® Processor 5300 Series with a 40W TDP (Thermal Design Power)
f
SLAC5 E5345 B-3 06F7 2.33 1333 8M 01 1,24,6,7,8,9
SL9YK E5335 B-3 06F7 2 1333 8M 01 1,24,6,7,8,9
SLAC7 E5335 B-3 06F7 2 1333 8M 01 1,24,6,7,8,9
SL9MV E5320 B-3 06F7 1.86 1066 8M 01 1,24,6,7,8,9
SLAC8 E5320 B-3 06F7 1.86 1066 8M 01 1,24,6,7,8,9
SL9XR E5310 B-3 06F7 1.60 1066 8M 01 1,24,7,8,9
SLACB E5310 B-3 06F7 1.60 1066 8M 01 1,24,7,8,9
SLA4Q L5320 B-3 06F7 1.86 1066 8M 01 1,25,7,8,9
SLAC9 L5320 B-3 06F7 1.86 1066 8M 01 1,25,7,8,9
SL9MT L5310 B-3 06F7 1.60 1066 8M 01 1,25,7,8,9
SLACA L5310 B-3 06F7 1.60 1066 8M 01 1,25,7,8,9
SLAEG X5355 G-0 06FB 2.66 1333 8M 01 1,23,6,7,8,9
SLAEJ E5345 G-0 06FB 2.33 1333 8M 01 1,24,6,7,8,9
SLAEK E5335 G-0 06FB 2.00 1333 8M 01 1,24,6,7,8,9
SLAEL E5320 G-0 06FB 1.86 1066 8M 01 1,24,6,7,8,9
SLAEM E5310 G-0 06FB 1.60 1066 8M 01 1,24,7,8,9
SLAEP L5320 G-0 06FB 1.86 1066 8M 01 1,25,7,8,9
SLAEQ L5310 G-0 06FB 1.60 1066 8M 01 1,25,7,8,9
Table 1. Intel® Xeon® Processor 5300 Series Identification Information (Sheet 2 of
2)
S-Spec Processor Number Core Stepping CPUID Core
Freq
(GHz)
Data Bus
Freq
(MHz)
L2
Cache
Size
Processor
Package
Revision Notes

18 Intel® Xeon® Processor 5300 Series
Specification Update, December 2010
Errata
AJ1. Deleted
Status:
AJ2. LOCK# Asserted During a Special Cycle Shutdown Transaction May
Unexpectedly De-assert
Problem: During a processor shutdown transaction, when LOCK# is asserted and if a DEFER# is
received during a snoop phase and the Locked transaction is pipelined on the front side
bus (FSB), LOCK# may unexpectedly de-assert.
Implication: When this erratum occurs, the system may hang during shutdown. Intel has not
observed this erratum with any commercially available systems or software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AJ3. Address Reported by Machine-Check Architecture (MCA) on Single-bit
L2 ECC Errors May be Incorrect
Problem: When correctable Single-bit ECC errors occur in the L2 cache, the address is logged in
the MCA address register (MCi_ADDR). Under some scenarios, the address reported
may be incorrect.
Implication: Software should not rely on the value reported in MCi_ADDR, for Single-bit L2 ECC
errors.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AJ4. VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last
Exception Record (LER) MSR
Problem: The LER MSR may be unexpectedly updated, if the resultant value of the Zero Flag (ZF)
is zero after executing the following instructions
1) VERR (ZF=0 indicates unsuccessful segment read verification)
2) VERW (ZF=0 indicates unsuccessful segment write verification)
3) LAR (ZF=0 indicates unsuccessful access rights load)
4) LSL (ZF=0 indicates unsuccessful segment limit load)
Implication: The value of the LER MSR may be inaccurate if VERW/VERR/LSL/LAR instructions are
executed after the occurrence of an exception.
Workaround: Software exception handlers that rely on the LER MSR value should read the LER MSR
before executing VERW/VERR/LSL/LAR instructions.
Status: For the steppings affected, see the Summary Tables of Changes.
AJ5. DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store
Instruction May Incorrectly Increment Performance Monitoring Count
for Saturating SIMD Instructions Retired (Event CFH)
Problem: Performance monitoring for Event CFH normally increments on saturating SIMD
instruction retired. Regardless of DR7 programming, if the linear address of a retiring
memory store MOVD/MOVQ/MOVNTQ instruction executed matches the address in
DR3, the CFH counter may be incorrectly incremented.

Intel® Xeon® Processor 5300 Series 19
Specification Update, December 2010
Implication: The value observed for performance monitoring count for saturating SIMD instructions
retired may be too high. The size of the error is dependent on the number of
occurrences of the conditions described above, while the counter is active.
Workaround: None Identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AJ6. SYSRET May Incorrectly Clear RF (Resume Flag) in the RFLAGS
Register
Problem: In normal operation, SYSRET will restore the value of RFLAGS from R11 (the value
previously saved upon execution of the SYSCALL instruction). Due to this erratum, the
RFLAGS.RF bit will be unconditionally cleared after execution of the SYSRET instruction.
Implication: The SYSRET instruction can not be used if the RF flag needs to be set after returning
from a system call. Intel has not observed this erratum with any commercially available
software.
Workaround: Use the IRET instruction to return from a system call, if RF flag has to be set after the
return.
Status: For the steppings affected, see the Summary Tables of Changes.
AJ7. General Protection Fault (#GP) for Instructions Greater than 15 Bytes
May be Preempted
Problem: When the processor encounters an instruction that is greater than 15 bytes in length, a
#GP is signaled when the instruction is decoded. Under some circumstances, the #GP
fault may be preempted by another lower priority fault (e.g. Page Fault (#PF)).
However, if the preempting lower priority faults are resolved by the operating system
and the instruction retried, a #GP fault will occur.
Implication: Software may observe a lower-priority fault occurring before or in lieu of a #GP fault.
Instructions of greater than 15 bytes in length can only occur if redundant prefixes are
placed before the instruction.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AJ8. Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced
Before Higher Priority Interrupts
Problem: Interrupts that are pending prior to the execution of the STI (Set Interrupt Flag)
instruction are serviced immediately after the STI instruction is executed. Because of
this erratum, if following STI, an instruction that triggers a #MF is executed while
STPCLK#, Enhanced Intel SpeedStep® Technology transitions or Thermal Monitor 1
events occur, the pending #MF may be serviced before higher priority interrupts.
Implication: Software may observe #MF being serviced before higher priority interrupts.
Workaround: None Identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AJ9. The Processor May Report a #TS Instead of a #GP Fault
Problem: A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception)
instead of a #GP fault (general protection exception).
Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP
fault. Intel has not observed this erratum with any commercially available software.
Workaround: None Identified.
Status: For the steppings affected, see the Summary Tables of Changes.

20 Intel® Xeon® Processor 5300 Series
Specification Update, December 2010
AJ10. Code Segment Limit/Canonical Faults on RSM May be Serviced before
Higher Priority Interrupts/Exceptions and May Push the Wrong
Address Onto the Stack
Problem: Normally, when the processor encounters a Segment Limit or Canonical Fault due to
code execution, a #GP (General Protection Exception) fault is generated after all higher
priority Interrupts and exceptions are serviced. Due to this erratum, if RSM (Resume
from System Management Mode) returns to execution flow that results in a Code
Segment Limit or Canonical Fault, the #GP fault may be serviced before a higher
priority Interrupt or Exception (e.g. NMI (Non-Maskable Interrupt), Debug break(#DB),
Machine Check (#MC), etc.). If the RSM attempts to return to a non-canonical address,
the address pushed onto the stack for this #GP fault may not match the non-canonical
address that caused the fault.
Implication: Operating systems may observe a #GP fault being serviced before higher priority
Interrupts and Exceptions. Intel has not observed this erratum on any commercially
available software.
Workaround: None Identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AJ11. A Write to an APIC Register Sometimes May Appear to Have Not
Occurred
Problem: With respect to the retirement of instructions, stores to the uncacheable memory-
based APIC register space are handled in a non-synchronized way. For example if an
instruction that masks the interrupt flag, e.g. CLI, is executed soon after an
uncacheable write to the Task Priority Register (TPR) that lowers the APIC priority, the
interrupt masking operation may take effect before the actual priority has been
lowered. This may cause interrupts whose priority is lower than the initial TPR, but
higher than the final TPR, to not be serviced until the interrupt enabled flag is finally
set, i.e. by STI instruction. Interrupts will remain pending and are not lost.
Implication: In this example the processor may allow interrupts to be accepted but may delay their
service.
Workaround: This non-synchronization can be avoided by issuing an APIC register read after the
APIC register write. This will force the store to the APIC register before any subsequent
instructions are executed. No commercial operating system is known to be impacted by
this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AJ12. Programming the Digital Thermal Sensor (DTS) Threshold May Cause
Unexpected Thermal Interrupts
Problem: Software can enable DTS thermal interrupts by programming the thermal threshold
and setting the respective thermal interrupt enable bit. When programming DTS value,
the previous DTS threshold may be crossed. This will generate an unexpected thermal
interrupt.
Implication: Software may observe an unexpected thermal interrupt occur after reprogramming the
thermal threshold.
Workaround: In the ACPI/OS implement a workaround by temporarily disabling the DTS threshold
interrupt before updating the DTS threshold value.
Status: For the steppings affected, see the Summary Tables of Changes.
AJ13. Count Value for Performance-Monitoring Counter PMH_PAGE_WALK
May be Incorrect
Problem: Performance-Monitoring Counter PMH_PAGE_WALK is used to count the number of
page walks resulting from Data Translation Look-Aside Buffer (DTLB) and Instruction
Translation Look-Aside (ITLB) misses. Under certain conditions, this counter may be
incorrect.