Intel Xeon E3-1125C User manual

Intel® Xeon® Processor E3-1125C
with Intel® Communications Chipset
8910 Development Kit
User Guide
October 2012
Order No.: 328009-001US

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Copyright © 2012, Intel Corporation. All rights reserved.
Intel® Xeon® Processor E3-1125C with Intel® Communications Chipset 8910 Development Kit
User Guide October 2012
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Contents
1.0 Introduction.................................................................................................................6
1.1 Warnings and Cautions............................................................................................7
1.2 Kit Contents...........................................................................................................7
1.3 Features Summary.................................................................................................8
1.4 Related Documents.................................................................................................9
1.5 Processors and Chipset.........................................................................................10
1.6 Memory Sub-System.............................................................................................10
1.6.1 Supported Memory....................................................................................11
1.6.1.1 Population Requirements................................................................11
1.6.1.2 DIMM Population for Two Slots per Channel......................................11
1.7 Thermal and Mechanical Components......................................................................12
1.8 Real Time Clock (RTC), CMOS SRAM, and Battery.....................................................13
1.9 On-Board Peripheral Components...........................................................................13
1.10 On-Board I/O Connectors.....................................................................................14
1.11 Expansion I/O Slots.............................................................................................14
1.12 PCH EndPoint PCIe Configuration...........................................................................15
1.13 Rear Panel I/O Connectors...................................................................................16
1.14 On-Board Power Connectors.................................................................................17
1.15 Watch Dog Timer (WDT)......................................................................................17
1.16 Sleep States and Soft Off.....................................................................................17
1.17 Wake Events......................................................................................................17
1.18 Fan Power Connections........................................................................................18
1.19 On-Board Switches..............................................................................................18
1.20 Supported Operating Systems..............................................................................18
1.21 BIOS Features....................................................................................................18
1.22 ACPI..................................................................................................................19
1.23 Debug Ports.......................................................................................................19
1.24 SMBus...............................................................................................................19
1.25 DDR3 VREF Control Circuit...................................................................................20
2.0 CRB Setup...................................................................................................................21
2.1 CRB Configuration Setting Notes.............................................................................21
2.2 Memory Module Plug-in.........................................................................................22
2.3 Peripheral Setup...................................................................................................22
2.3.1 Connect SATA Cables................................................................................22
2.3.2 Expansion Connectors...............................................................................22
2.3.3 Rear Panel Connectors...............................................................................23
2.3.4 SPI Boot Devices......................................................................................23
2.3.4.1 SPI Flash Memory Installation.........................................................23
2.3.4.2 SPI Flash Memory Removal............................................................27
2.3.4.3 Dediprog: SPI Flash Memory Programming.......................................28
2.3.4.4 GbE EEPROM Devices....................................................................31
2.3.5 Connect Power.........................................................................................31
2.4 Turning On and Resetting the Board........................................................................31
3.0 Overview of BIOS Features.........................................................................................32
3.1 Introduction.........................................................................................................32
3.1.1 PCI Auto-Configuration..............................................................................32
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3.2 System Management BIOS (SMBIOS)......................................................................32
3.3 Legacy USB Support..............................................................................................32
3.4 Language Support.................................................................................................33
3.5 Boot Options........................................................................................................33
3.5.1 CD-ROM Boot...........................................................................................33
3.5.2 Network Boot...........................................................................................33
3.5.3 USB Boot.................................................................................................33
3.5.4 Changing the Boot Device..........................................................................34
3.5.5 Serial Console Redirection..........................................................................34
3.6 BIOS Security Features..........................................................................................34
3.7 Boot Flow............................................................................................................35
Appendix A Technical Reference.......................................................................................36
A.1 CMOS Battery Replacement....................................................................................36
A.2 Clearing CMOS Memory.........................................................................................36
A.3 Processor Straps - Jumper Settings.........................................................................37
A.4 PCH Straps - Jumper Settings.................................................................................37
A.5 Miscellaneous Jumper Settings...............................................................................38
A.6 SMBus Headers....................................................................................................40
A.7 Voltage Measurement Headers...............................................................................41
A.8 LED Indicators......................................................................................................41
A.9 Power Supply Connectors.......................................................................................43
A.10 Front Panel Connector.........................................................................................43
A.11 Memory Resources..............................................................................................44
A.12 Interrupts..........................................................................................................44
Appendix B Error Messages and LED Codes.......................................................................53
B.1 Port 0x80 Progress Codes......................................................................................53
B.2 Port 0x80 Error Codes...........................................................................................55
B.3 Port 0x80 Error Debug...........................................................................................57
Appendix C Board Reference Diagrams.............................................................................58
Figures
1 Reference Board Overview .........................................................................................6
2 CRB 2 DIMM/CH DDR3 Topology................................................................................11
3 DIMM Population Within a Channel for Two Slots per Channel........................................12
4 Intel® Xeon® Processor E3-1125C with Intel® Communications Chipset 8910
Development Kit PCIe Headers..................................................................................16
5 SMBus Block Diagram..............................................................................................20
6 Memory Sockets......................................................................................................22
7 SPI In-Circuit Programming......................................................................................23
8 Dediprog: SPI Flash Offset........................................................................................30
9 Offset Setting.........................................................................................................30
10 Offset Verification....................................................................................................30
11 Top View................................................................................................................58
12 DDR3 Memory Components......................................................................................59
13 PCIe Slots..............................................................................................................60
14 PECI & Thermal Diode Components............................................................................60
15 LEDs and Power Button Switches...............................................................................61
16 Power Supply Headers..............................................................................................62
17 SMBus Headers.......................................................................................................63
18 Configuration Jumper Locations (1 of 2).....................................................................64
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19 Configuration Jumper Locations (2 of 2).....................................................................65
20 Intel® Communications Chipset 89xx Series Straps......................................................66
21 Intel® Xeon® and Intel® Core™ Processor For Communications Infrastructure Straps.......67
22 Front Panel.............................................................................................................67
Tables
1 Supported Processor and Chipset...............................................................................10
2 UDIMM Population Configurations Within a Channel for Two Slots per Channel.................12
3 Thermal and Mechanical Components.........................................................................12
4 On-Board Peripheral Components..............................................................................13
5 On-Board I/O Connectors.........................................................................................14
6 Expansion I/O Slots.................................................................................................14
7 Intel® Communications Chipset 89xx Series SKUs........................................................15
8 Intel® Xeon® Processor E3-1125C PCIe Port0 Configuration..........................................15
9 Intel® Xeon® Processor E3-1125C PCIe Lane Reversal..................................................15
10 Intel® Xeon® Processor E3-1125C with Intel® Communications Chipset 8910
Development Kit PCIe Configuration...........................................................................16
11 Intel® Xeon® Processor E3-1125C with Intel® Communications Chipset 8910
Development Kit Default Header Configuration............................................................16
12 Rear Panel I/O Connectors........................................................................................16
13 On-Board Power Connectors......................................................................................17
14 Supported BIOS Features.........................................................................................18
15 Effects of Pressing the Power Button..........................................................................19
16 Serial Console Redirection Default Settings.................................................................34
17 Processor Straps - Jumper Settings............................................................................37
18 PCH Straps - Jumper/Resistor Settings.......................................................................37
19 Miscellaneous Jumper/Resistor Settings......................................................................38
20 Reserved Headers....................................................................................................39
21 SMBus Headers.......................................................................................................40
22 Voltage Measurement Headers..................................................................................41
23 LED Indicators........................................................................................................41
24 24-pin Main Power Connector Pins (Top-View).............................................................43
25 8-pin Processor Power Connector Pins (Top-View)........................................................43
26 4-pin DDR Power Connector Pins (Top-View)...............................................................43
27 9-pin Front Panel Connector Pins (Top-View)...............................................................43
28 I/O xAPIC Interrupt Mapping 1...................................................................................44
29 PCH GPIO Mapping..................................................................................................45
30 Port 0x80 Progress Codes.........................................................................................53
31 Port 0x80 Error Codes..............................................................................................55
32 Port 0x80 Error Debug.............................................................................................57
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1.0 Introduction
The Intel® Xeon® Processor E3-1125C with Intel® Communications Chipset 8910
Development Kit (CRB) hardware design is based on the Intel® Xeon® and Intel®
Core™ Processor For Communications Infrastructure connected to the Intel®
Communications Chipset 89xx Series. The CRB design supports one Intel® Xeon® and
Intel® Core™ Processor For Communications Infrastructure using a device down
topology . The processor supports up to two DDR3 channels and up to 20 PCI
Express* Gen 2 lanes, as shown below.
Figure 1. Reference Board Overview
Unless otherwise stated references to the "CRB" or "customer reference board" refer
to the Intel® Xeon® Processor E3-1125C with Intel® Communications Chipset 8910
Development Kit. Unless otherwise stated references to the “processor” and "CPU"
throughout this document refer to the Intel® Xeon® and Intel® Core™ Processor For
Communications Infrastructure. Unless otherwise stated references to the “chipset,”
“Platform Controller Hub,” or “PCH” refer to the Intel® Communications Chipset 89xx
Series.
The CRB schematics are the primary source for details about the CRB. This user guide
is a supplement to the schematics. Component reference designators in this user's
guide are based on the CRB schematics and are defined by their type and board-
mapped location. They end with a numerical index. The board-mapped locations are
sectioned on a grid pattern: 1 through 9 horizontally, and A through K vertically. The
bottom side of the board has a similar grid pattern but with different call-outs. See the
grid call-outs along the edges of the board. U6D1, for example, is an IC (U), is on the
top of the board at cross section 6D, and is the first indexed component (1) of that
type in that area.
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1.1 Warnings and Cautions
Caution: Ensure a safe and static-free work environment before removing any components
from their anti-static packaging. The CRB is susceptible to electrostatic discharge,
which may cause failure or unpredictable operation.
Caution: Connecting the wrong cable or reversing a cable may damage the board and may
damage the device being connected. Since the board is not in a protective chassis, use
caution when connecting cables to the board.
Caution: The power supply cord is the main disconnect device to the main power (AC power).
The socket outlet should be installed near the equipment and should be readily
accessible. To avoid shock, ensure that the power cord is connected to a properly
wired and grounded receptacle. Do not connect/disconnect any cables or perform
installation/maintenance of the boards during an electrical storm. Ensure that any
equipment to which this CRB will be attached is also connected to properly wired and
grounded receptacles.
Ensure that setting up the power supply is the final step performed in the process of
assembly.
Once the board is set up, plug the power cable into the back of the power supply,
leaving the switch in the OFF position, then plug the cord into the power source and
switch on the power supply.
Caution: Items marked as "Reserved" in this users guide and in the CRB schematics are not
supported. Changing settings related to these items could lead to unknown behavior
on the CRB.
1.2 Kit Contents
Feature Description
CRB board PCB assembled with a BGA device down for the Intel® Xeon® and Intel®
Core™ Processor For Communications Infrastructure and device down for
Intel® Communications Chipset 89xx Series with a passive heatsink.
Processor Intel® Xeon® and Intel® Core™ Processor For Communications Infrastructure
Processor heatsink Active heatsink
Chipset Intel® Communications Chipset 8910
Memory Two Micron 1-GB DDR3, UDIMMs (ECC) (different DIMM type may be provided)
SPI flash Two-socketed SPI flash (4 MB each) for BIOS, PCH ME Ignition FW, and
platform data
Power supply 625 W ATX power supply
Video card x1 PCIe* graphics card
Hard drive Western Digital 3.5 inch-solid state drive: 160 GB SATA II
Disk drive LITE ON DVD-RW/CD-RW SATA disk
continued...
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Feature Description
GbE PHY plug-in cards • Intel® Ethernet Server Adapter X520-T2, Dual-port 10G Bast T NIC
•Intel® Ethernet Server Adapter X520-SR2, Dual-port SFP+ SR Optics
Stand Acrylic stand for board plus pads
Additional peripherals 8 x Standoffs and 16 x screws
1.3 Features Summary
Feature Description
Form factor 12-layer custom ATX (~12 x ~12 inches) board
Processor Supports Intel® Xeon® and Intel® Core™ Processor For Communications
Infrastructure.
Bus speed Intel® DMI2 2.5GT/s:
• Intel® Xeon® and Intel® Core™ Processor For Communications
Infrastructure: Gen2 protocol at Gen2 speed.
• Intel® Communications Chipset 89xx Series: Gen2 protocol at Gen1 speed.
Processor VR IMVP 7.0
Memory Total of four DIMM connectors:
• Up to two channels per processor
• Up to two DIMMs / channel
• Supports 1066/1333 MHz DDR3 Unregistered 240-pin DIMMs.
• Up to 32 GB of system memory
• Support for single-rank and dual-rank DIMMs
• Support for 1 Gb, 2 Gb, and 4 Gb technologies/densities
PCI Express Total of six slots:
• One x16 slot connected to processor Intel® Communications Chipset 89xx
Series Endpoint)
• One x8 slot on processor (4 active lanes)
• Four x8 slots from PCH (2.5 GT/s Max) (1 active lane in each)
Note: PCI Express* Base Specification, Rev. 1.0a
PCI Express hot-plug Not supported.
Chipset BGA soldered down Intel® Communications Chipset 89xx Series
Serial ATA Two SATA-II ports with AHCI support
Note: Windows XP should be booted in IDE mode only
USB* Total of six connections (USB 2.0 ports (RMH/EHCI configuration):
• 4x USB ports on rear panel
• 2x USB connector ports (10 pin header)
Video PCI Express* video controller.
Connected to PCH PCI Express x1 controller
LAN support PHY Card plug in cards over HMZD connection: One Acre Quad PHY Module
(I347)
LPC Low Pin Count (LPC) Bus I/O Controller: One (TPM) header
Other I/Os PS/2* keyboard and mouse ports
Two Serial ports (One dedicated to PCH, second is shared between PCH and SIO)
continued...
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Feature Description
Clocking CK420 for delivery of differential clocks to Intel® Xeon® and Intel® Core™
Processor For Communications Infrastructure and Intel® Communications
Chipset 89xx Series DB1900 clock buffer for additional 100-MHz differential
clocks
BIOS Two 16-pin SOIC SPI Socket for Flash support. Populated with 4-MB devices (one
device for BIOS and the other for ME FW, GbE etc.)
Support for Advanced Configuration and Power Interface (ACPI), plug-and-play,
SMBIOS
Hardware subsystem Supports S0, S3, S4, and S5 sleep states.
Fan support:
• CPU fan connector (full speed only)
• PCH fan connector (full speed only)
Debug:
• ITP-XDP0 connector for CPU
• ITP-XDP1 connector for PCH
1.4 Related Documents
Always use the latest versions as references for the CRB. Contact your field representative for publication
access.
Document URL (Document Number)
Intel® Xeon® and Intel® Core™ Processors For
Communications Infrastructure Datasheet
327405
Intel® Communications Chipset 89xx Series
Datasheet
327879
Intel® Communications Chipset 89xx Series
Specification Update
328000
Intel® Xeon® and Intel® Core™ Processors For
Communications Infrastructure Thermal/Mechanical
Design Guide
327397
Intel® Communications Chipset 89xx Series
Thermal/Mechanical Design Guide
328012
JEDEC Memory Specification http://www.jedec.org
PCI Express* Base Specification, Rev. 2.0 http://www.pcisig.com/specifications/
PCI Express* Base Specification, Revision 1.1 http://www.pcisig.com/specifications/
PCI Express* Card Electromechanical Specification,
Revision 1.1
http://www.pcisig.com/specifications/
PCI Local Bus Specification, Rev. 2.3 http://www.pcisig.com/specifications/
PCI Standard Hot Plug Controller and Subsystem
Specification, Revision 1.1
http://www.pcisig.com/specifications/
PCI Power Management Specification, Revision 1.1 http://www.pcisig.com/specifications/
System Management Bus Specification, Version 2.0
(SMBus)
http://www.smbus.org/specs/
Low Pin Count Interface Specification, Revision 1.1
(LPC)
Contact your Intel representative for the latest
version of this item.
Universal Serial Bus Revision 2.0 Specification (USB) http://www.usb.org
continued...
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Document URL (Document Number)
Advanced Configuration and Power Interface, Version
2.0 (ACPI)
http://www.acpi.info/spec.htm
Universal Host Controller Interface, revision 1.1
(UHCI)
Contact your Intel representative for the latest
version of this item.
Enhanced Host Controller Interface Specification for
Universal Serial Bus, Revision 1.0 (EHCI)
Contact your Intel representative for the latest
version of this item.
Serial ATA Specification, Revision 1.0a http://www.serialata.org
Serial ATA II: Extensions to Serial ATA 1.0, Revision
1.0a
http://www.serialata.org
IEEE 802.3 Fast Ethernet http://standards.ieee.org
AT Attachment - 6 with Packet Interface (ATA/ATAPI
- 6)
http://T13.org (T13 1410D)
IA-PC HPET (High Precision Event Timers)
Specification, Revision 0.98a
Contact your Intel representative for the latest
version of this item.
Intel® ICH Family Real Time Clock (RTC) Accuracy
and Considerations Under Test
Intel appnote AP-728
Front Panel I/O Connectivity Design Guide http://www.formfactors.org/DeveloperResources.asp
SSI Specification http://ssiforum.org/specifications.aspx
ATX Specification Rev 2.02 http://www.formfactors.org/formfactor.asp
Socket B Design Guidelines Contact your Intel representative for the latest
version of this item.
1.5 Processors and Chipset
The CRB is designed to support the following processor and chipset. Use only the
processor and chipset in the table. The use of unsupported components can damage
the CRB board, the processor, and the power supply.
In this document, "processor" and "CPU" refers to the processor in the following table.
Table 1. Supported Processor and Chipset
Ref Des
Location
Description
U6G1 CPU /
processor
Intel® Xeon® and Intel® Core™ Processor For Communications
Infrastructure
U2G1 Chipset Intel® Communications Chipset 8910
1.6 Memory Sub-System
The CRB supports a DDR3-based memory subsystem that includes support for up to
two channels per processor and two DIMMs per channel (2 DIMM/CH). See the
following figure.
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Figure 2. CRB 2 DIMM/CH DDR3 Topology
Processor
D
I
M
M
B1
D
I
M
M
B0
D
I
M
M
A1
D
I
M
M
A0
Channel A Channel B
1.6.1 Supported Memory
The CRB supports DDR3-1066 and DDR3-1333 memory technologies.
The processor has a two-channel memory interface. Each channel consists of 64 data
and 8 ECC bits. The CRB supports unbuffered ECC/non-ECC DDDR3 DIMMs.
1.6.1.1 Population Requirements
• All DIMMs must be DDR3 Unbuffered DIMMs.
•Unbuffered DIMMs can be ECC or non-ECC.
• Mixing of ECC and non-ECC DIMMs is not allowed.
• A maximum of 4 logical ranks per channel is allowed.
• DIMMs with different timing parameters can be installed on different slots within
the same channel, but only timings that support the slowest DIMM will be applied
to all. As a consequence, faster DIMMs will be operated at timings supported by
the slowest DIMM populated. The same interface frequency (DDR3-1066 or
DDR3-1333) will be applied to all DIMMs on all channels on the platform.
• When single and dual rank DIMMs are populated for 2DPC, always populate the
higher number rank DIMM first (starting from the farthest slot), for example, first
dual rank and last single rank.
1.6.1.2 DIMM Population for Two Slots per Channel
For two slot per channel configurations, the CRB requires DIMMs within a channel to
be populated starting with the DIMMs farthest from the processor in a “fill-farthest”
approach.
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Figure 3. DIMM Population Within a Channel for Two Slots per Channel
CLK_DP/DN:
Processor
D
I
M
M
0
0/1
0/1
D
I
M
M
1
1
2/3
2/3
Chip Select:
ODT:
0
0/21/3CKE:
Fill
Second Fill First
All allowed DIMM population configurations for two slots per channel are shown in the
following table.
Table 2. UDIMM Population Configurations Within a Channel for Two Slots per Channel
Configuratio
n Number
POR Speed 1N or
2N
DIMM0 DIMM1
1 DDR3-1333 & 1066 1N Empty Single-rank
2 DDR3-1333 & 1066 1N Empty Dual-rank
3 DDR3-1333 & 1066 2N Single-rank Single-rank
4 DDR3-1333 & 1066 2N Single-rank Dual-rank
5 DDR3-1333 & 1066 2N Dual-rank Dual-rank
1.7 Thermal and Mechanical Components
Table 3. Thermal and Mechanical Components
Name Description
Standard Processor Thermal
Solution Mounting
The CRB supports full power processor thermal solution mounting
provisions as delineated in the processor's Thermal/Mechanical Design
Guidelines.
Processor Fan The CRB provides fan headers for the processors that includes 12V.
Heatsink The CRB supports heatsink mounting requirements.
continued...
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Name Description
Active Heatsink The CRB provides mounting provisions and a fan header for an active
thermal solution.
Fan Headers The CRB provides one fan header.
Solder Down Anchors The CRB provides solder down anchors for the CRB and chipset. This
includes active heatsink mounting holes.
Heatsinks
The processor and CRB use an active heatsink design with a built-in fan, and the PCH
uses a passive heatsink. The active heatsink is powered by the platform. For details on
the processor and PCH heatsink, see the Thermal/Mechanical Design Guidelines. The
passive heatsink for the Intel® Communications Chipset 89xx Series requires no
power.
Physical and Mechanical Board Specifications
The CRB is approximately 12 inches long by 12 inches wide. It provides non-plated
mounting holes with top and bottom ground rings and requires users to use the acrylic
stand provided to avoid shorts.
1.8 Real Time Clock (RTC), CMOS SRAM, and Battery
A coin-cell battery (B1B1 type CR2032) powers the real-time clock (RTC) and CMOS
memory. The battery has an estimated life of three years when it is not plugged into a
wall socket. When the platform is plugged in, the standby current from the power
supply extends the life of the battery. The clock is accurate to ± 13 minutes/year at
25 ºC with 3.3 VSTBY applied.
If the battery and AC power fail, then at boot-up the system will prompt you to either
load optimized defaults or enter the BIOS and manually adjust the BIOS settings.
1.9 On-Board Peripheral Components
Table 4. On-Board Peripheral Components
Ref Des
Location
Description
U5F1/U3E1 Clock Generator / Clock
Buffer
CK420 Clock Generator/ DB1900 Clock Buffer
U3A2 SuperI/O* The SIO (WPCD376I) is driven by the PCH Low Pin Count
(LPC) bus.
U2K1/U2K2 SPI Flash 16 MB socket with footprint for 8-pin devices (primary boot,
Intel® Communications Chipset 89xx Series FW storage,
BIOS etc.)
S6A1 Power Button System power button
S7A1 Reset Button System reset button
U1K1 Port 80 Logic Device Altera* EPM570_100P
DS2K1/DS2K2 Port 80 Code Display Two digit, 7-segment LED character displays
continued...
Introduction—Crystal Forest
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Ref Des
Location
Description
B1B1 Battery 3 V Lithium CR2032 coin battery for real time clock (RTC)
and CMOS memory backup
U9A1 RS232 Transceiver Two 28-pin connectors to handle all modem control signals
U9A2
1.10 On-Board I/O Connectors
Table 5. On-Board I/O Connectors
Ref Des Location Description
J1D1, J1D2 PHY Card Connector HMZD connector for PHY add-in card
J1G1 Serial ATA Port 0 Two SATA 2 interface connectors. SATA ports 4 and 5 are
referenced as SATA ports 0 and 1 respectively.
J1F6 Serial ATA Port 1
J1E3 USB Port 4 and 5 Header 10-pin (pin 9 is omitted as a plug-in key), dual-row
header that routes two USB ports to an external USB
connector. In conjunction with the rear panel USB ports
there are a total of six USB ports.
J1A7 Front Panel Header 10-pin (pin 10 is omitted as a plug-in key), dual-row
header that provides connection for:
•Power Switch
• Reset Switch
• Power-on LED
• HD Status LED
J8D1 CPU Fan Header Four-wire CPU fan header.
J3J1 PCH Fan Header Three-wire PCH fan header.
J5B3 AUX Fan Header Three-wire header with no fan speed control.
J1H2 LPC Header 20-pin card header for the TPM / LPC bus.
J1J1 LCD Data 16-pin header, not populated, for LCD port 80 output
J2J2 PCH In-Circuit SPI
Programming Header
10-pin header for use with DediProg* SF100 in-circuit
program tool. Used to update PCH SPI device without
removing it from its socket.
J5A1 XDP0 Connector CPU Top-side 60-pin connector for ITP-XDP processor debug.
XDP is the Extended Debug Port used for component
debugging and testing.
J6D2 XDP1 Connector PCH Top-side 60-pin connector for the ITP-XDP PCH debug.
XDP is the Extended Debug Port used for component
debugging and testing.
1.11 Expansion I/O Slots
Table 6. Expansion I/O Slots
Ref Des
Location
Description Notes
J5B1 PCI Express* Slot
1
Processor The PCI Express ports comply with PCI
Express* Base Specification, Rev. 2.0a.
continued...
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Ref Des
Location
Description Notes
J4B1 PCI Express Slot 2
J4B2 PCI Express Slot 3 PCH Root Complex (2.5 GT/
s Max)
The PCI Express Ports comply with PCI
Express* Base Specification, Rev. 1.0a. All
PCI Express slots (3, 4, 5, 6) employ
physical x8 connectors regardless of
whether they are x1, x4, or x8. This
enables use of x8 cards even if the actual
bandwidth and functionality is less.
J3B1 PCI Express Slot 4
J2B2 PCI Express Slot 5
J2B1 PCI Express Slot 6
PCI Express Hot-Plug is not supported.
1.12 PCH EndPoint PCIe Configuration
This section provides details on how to configure the PCIe for the supported Intel®
Communications Chipset 89xx Series SKU.
Table 7. Intel® Communications Chipset 89xx Series SKUs
Intel® Communications Chipset 89xx Series
SKU
PCIe Width
#3 x8
The PCH EndPoint can operate as a x4, x8, or x16 depending on the SKU and
population of the headers below.
Table 8. Intel® Xeon® Processor E3-1125C PCIe Port0 Configuration
J6F6
CFG<6>
Bit
J6E4
CFG<5>
Bit
Intel® Xeon® Processor E3-1125C Port Bifurication
1 1 x16
1 0 x8 & x8
0 1 Reserved
0 0 x8, x4 & x4
The Intel® Communications Chipset 89xx Series EndPoint also supports lane reversal.
Lane Reversal and Polarity Inversion must be done at a port level on the processor
part (as outlined below).
Table 9. Intel® Xeon® Processor E3-1125C PCIe Lane Reversal
Jumper
PCIe x16 - Lane Reversal J6E5 - Closed
PCIe x16 - No Lane Reversal (Default) J6E5 - Open
PCIe x4 - Lane Reversal J6E6 - Closed
PCIe x4 - No Lane Reversal (Default) J6E6 - Open
In addition to the above headers, additional headers affect the PCIe training at boot-
up.
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Table 10. Intel® Xeon® Processor E3-1125C with Intel® Communications Chipset 8910
Development Kit PCIe Configuration
Header Description
J6E2 J6E2 must be Open for the PCH with BIOS V35 or later.
J3F2
Keep EP in Reset
Jumper must be Closed (inserted).
Removing the jumper (Open) will keep EP in Reset (Low-true signal forced Low).
Figure 4. Intel® Xeon® Processor E3-1125C with Intel® Communications Chipset 8910
Development Kit PCIe Headers
Table 11. Intel® Xeon® Processor E3-1125C with Intel® Communications Chipset 8910
Development Kit Default Header Configuration
SKU J6F6 J6E4 J6E2 J3F2 J6E5 J6E6 Description
#1 Closed Closed Open Closed Closed X Bifur = X4 (0,0), Lane Reverse
#2 Closed Closed Open Closed Closed X Bifur = X4 (0,0), Lane Reverse
#3 Closed Open Open Closed Closed X Bifur = X8 & X8 (1,0), Lane
Reverse
#4 Open Open Open Closed Closed X Bifur = X16 (1,1), Lane Reverse
1.13 Rear Panel I/O Connectors
Table 12. Rear Panel I/O Connectors
Ref Des Location Description
J8A1 USB Ports 0-3
Connector
The rear panel connector provides a quad-stacked USB
2.0 ports. Additionally, on board there is a header to
allow connection to a front panel header. There are three
USB modes:
•RMH
• UHCI
• EHCI
continued...
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Ref Des Location Description
See the Intel® Communications Chipset 89xx Series
Datasheet for details on USB operating modes.
J9A2 PS/2 Keyboard and
Mouse Connectors
The side panel provides two stacked circular DIN PS/2
connectors. Turn off power before a keyboard or mouse
is connected or disconnected.
• Keyboard connector on bottom (nearest board)
• Mouse connector on top
J9A3 Serial COM Port
Connector
The rear panel provides a dual-stack serial COM port.
• RS232E 9-pin male D-sub dual port connector
• Only outbound serial port traffic is available
1.14 On-Board Power Connectors
Table 13. On-Board Power Connectors
Ref Des
Location
Description
J4K4 SSI 24-pin power
connector
Provides 12 V (+12V2), -12 V, 5 V, 3.3 V, 5 VSB voltages from the
external power supply.
J5K2 SSI 8-pin power
connector
Provides 12 V (+12V1) voltages from the external power supply
that feed the CPU.
J9D1 SSI 8-pin power
connector
Provides 12 V (+12V1) voltages from the external power supply
that feed the DIMMs.
1.15 Watch Dog Timer (WDT)
The PCH has a safeguard watchdog timer to help prevent processor from thermal
overload. During the power-up sequence, the PCH asserts CPUPWRGD. If the
processor reset handshake is not completed within 10 ms of assertion, the PCH will
power cycle the system to re-attempt the boot. It is critical to avoid having the
processor powered and held in reset for an extended time.
The PCH watchdog timer will cause the CRB to power cycle if something does not allow
the processor reset handshake to be completed with 10 ms of CPUPWRGD assertion.
1.16 Sleep States and Soft Off
ACPI 1.0, 2.0, 3.0 APM compliant.
•S0, S3, S4, and S5 sleep states
• Soft off capability (S5)
— Operating system dependent
— Requires a complete OS boot when the system wakes
1.17 Wake Events
• Power switch
• Wake on LAN (WoL) from GbE (PCH EndPoint/connector) or PCIe port
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1.18 Fan Power Connections
• One processor fan connector
•One PCH fan connector
• One 3-wire auxiliary fan connector
1.19 On-Board Switches
The CRB has the following momentary push-button switches to provide state control:
• System power button (S6A1)
• System reset button (S7A1)
1.20 Supported Operating Systems
The CRB is validated with the following operating systems:
•Microsoft* Windows Embedded Standard 7 SP1 (32-bit and 64-bit)
• Windows Server 2008 R2 with SP1 (64-bit)
• FreeBSD* 8.2 (32-bit and 64-bit)
• Fedora* 16 (32-bitt and 64-bit)
Operating systems must be obtained by the customer. They are not distributed with
the CRB kit.
1.21 BIOS Features
The BIOS has an AMI* core with the following components:
Table 14. Supported BIOS Features
BIOS Component Description
PCI 2.3 The BIOS is compliant with the PCI Local Bus Specification, Rev. 2.3.
Serial ATA boot The BIOS supports booting from a Serial ATA hard drive.
CD-ROM boot The BIOS supports booting from a Serial ATA CD-ROM.
USB boot The BIOS supports booting from a USB boot device.
Floppy boot The BIOS supports booting from a floppy drive
PCI Express The BIOS initializes and supports PCI Express cards that are plugged into the CRB.
USB The BIOS supports the USB 1.1 and USB 2.0 interfaces.
CMOS Header The BIOS supports recognizing the clear CMOS header.
ECC support The BIOS detects and supports ECC memory.
Watchdog Timer
(WDT)
The BIOS provides watch dog timer support.
APIC and ACPI
Control
The ability to enable and disable APIC and ACPI is present in the BIOS. Control is
also required for OS plug-and-play features. The BIOS supports the following ACPI
states:
continued...
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BIOS Component Description
• G0 (S0) - Working
•G1 (S3) - Sleeping [Suspend to RAM]
• G2 (S5) - Soft Off
The BIOS supports C0, C1, C1E and C2 states.
Patch Update
Mechanism
The Patch Update Mechanism is used to upgrade and/or install micro-code patches
into BIOS is supported (BIOS Recovery Strap is located at J5A3 on the board).
1.22 ACPI
ACPI gives the OS direct control over the power management and plug-and-play
functions of the platform. ACPI requires an OS that provides full ACPI support.
Under ACPI, the OS directs all system and device power state transitions by managing
devices in and out of low-power states based on user preferences and knowledge of
how devices are being used by applications. Devices that are not being used can be
turned off. The OS uses information from applications and user settings to put the
system as a whole into a low-power state.
Table 15. Effects of Pressing the Power Button
If the system is in this
state...
...and the power switch is
pressed for
...the system enters this state
Off (ACPI G2/G5 - soft off) Less than four seconds Power-on (ACPI G0 - working state)
On (ACPI G0 - working state) Less than four seconds Soft-off/Standby (ACPI G1 - sleeping
state)
On (ACPI G0 - working state) More than four seconds Fail Safe Power-off (ACPI G2/G5 -
soft off)
Sleep (ACPI G1 - sleeping
state)
Less than four seconds Wake-up (ACPI G0 - working state)
Sleep (ACPI G1 - sleeping
state)
More than four seconds Power-off (ACPI G2/G5 - soft off)
1.23 Debug Ports
The CRB provides an XDP for the processor (XDP0 - J5A1) and an XDP for the PCH
(XDP1 - J6D2).
1.24 SMBus
The following figure provides a summary of the SMBus structure and address
information supplemental to the CRB schematics.
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Figure 5. SMBus Block Diagram
1.25 DDR3 VREF Control Circuit
The ISL90728 chip for Channel B responds to SMBus address 0x7C. the ISL90727 chip
for Channel A responds to SMBus address 0x5C. These digital potentiometer chips
both reside in the DIMM_VREF_SMB segment of the CRB SMBus.
The CRB schematics show the digital potentiometers connected in parallel with 12.1
KΩ / 12.1 KΩ 1% resistor voltage dividers. This must be considered if calculating the
resulting VREF voltage for particular settings of the potentiometer.
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