Intel CELERON 1.10 GHZ User manual

Intel®Celeron®Processor
up to 1.10 GHz Datasheet
The Intel®Celeron®processor is designed for uni-processor based Value PC desktops and is
binary compatible with previous generation Intel architecture processors. The Celeron processor
provides good performance for applications running on advanced operating systems such as
Microsoft* Windows*98, Windows NT*, Windows* 2000, Windows XP* and Linux*. This is
achieved by integrating the best attributes of Intel processors—the dynamic execution
performance of the P6 microarchitecture plus the capabilities of MMX™ technology—bringing
a balanced level of performance to the Value PC market segment. The Celeron processor offers
the dependability you would expect from Intel at an exceptional value. Systems based on
Celeron processors also include the latest features to simplify system management and lower the
cost of ownership for small business and home environments.
■Available at 1.10 GHz, 1 GHz, 950 MHz,
900 MHz, 850 MHz, 800 MHz, 766 MHz,
733 MHz, 700 MHz, 667 MHz, 633 MHz,
600 MHz, 566 MHz, 533 MHz,
533A MHz, 500 MHz, 466 MHz,
433 MHz, 400 MHz, 366 MHz, 333 MHz,
and 300A MHz core frequencies with
128 KB level-two cache (on die); 300 MHz
and 266 MHz core frequencies without
level-two cache.
■Intel’s latest Celeron®processors in the
FC-PGA/FC-PGA2 package are
manufactured using the advanced 0.18
micron technology.
■Binary compatible with applications
running on previous members of the Intel
microprocessor line.
■Dynamic execution microarchitecture.
■Operates on a 100/66 MHz, transaction-
oriented system bus.
■Specifically designed for uni-processor
based Value PC systems, with the
capabilities of MMX™ technology.
■Power Management capabilities.
■Optimized for 32-bit applications running
on advanced 32-bit operating systems.
■Uses cost-effective packaging technology.
—Single Edge Processor (S.E.P.) Package
to maintain compatibility with SC242
(processor core frequencies (MHz):
266, 300, 300A, 333, 366, 400, 433).
—Plastic Pin Grid Array (PPGA) Package
(processor core frequencies (MHz):
300A, 333, 366, 400, 433, 466, 500,
533).
—Flip-Chip Pin Grid Array (FC-PGA /
FC-PGA2) Package (processor core
frequencies (MHz); 533A, 566, 600,
633, 667, 700, 733, 766, 800, 850, 900,
950); (GHz); 1, 1.10
■Integrated high-performance 32 KB
instruction and data, nonblocking, level-
one cache: separate 16 KB instruction and
16 KB data caches.
■Integrated thermal diode.
S.E.P. PackageFC-PGA2 Package FC-PGA Package PPGA Package
Document Number: 243658-020
January 2002

Datasheet
Information in this document is provided in connection with Intel®products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel®Celeron®processor may contain design defects or errors known as errata which may cause the product to deviate from published specifi-
cations. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling
1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.
Intel, Celeron, Pentium, MMX and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States
and other countries.
*Other names and brands may be claimed as the property of others.
Copyright©1996–2002, Intel Corporation

Datasheet 3
Intel®Celeron®Processor up to 1.10 GHz
Contents
1.0 Introduction.......................................................................................................................11
1.1 Terminology.........................................................................................................11
1.1.1 Package Terminology.............................................................................12
1.1.2 Processor Naming Convention...............................................................13
1.2 References..........................................................................................................14
2.0 Electrical Specifications....................................................................................................15
2.1 System Bus and Vref...........................................................................................15
2.2 Clock Control and Low Power States..................................................................15
2.2.1 Normal State—State 1 ...........................................................................16
2.2.2 AutoHALT Power Down State—State 2.................................................16
2.2.3 Stop-Grant State—State 3 .....................................................................17
2.2.4 HALT/Grant Snoop State—State 4 ........................................................17
2.2.5 Sleep State—State 5..............................................................................17
2.2.6 Deep Sleep State—State 6....................................................................18
2.2.7 Clock Control..........................................................................................18
2.3 Power and Ground Pins......................................................................................18
2.3.1 Phase Lock Loop (PLL) Power...............................................................19
2.4 Processor Decoupling.........................................................................................19
2.4.1 System Bus AGTL+ Decoupling.............................................................19
2.5 Voltage Identification...........................................................................................20
2.6 System Bus Unused Pins....................................................................................21
2.7 Processor System Bus Signal Groups................................................................21
2.7.1 Asynchronous Vs. Synchronous for System Bus Signals......................23
2.7.2 System Bus Frequency Select Signal (BSEL[1:0]).................................23
2.8 Test Access Port (TAP) Connection....................................................................23
2.9 Maximum Ratings................................................................................................23
2.10 Processor DC Specifications...............................................................................24
2.11 AGTL+ System Bus Specifications .....................................................................33
2.12 System Bus AC Specifications............................................................................34
3.0 System Bus Signal Simulations........................................................................................52
3.1 System Bus Clock (BCLK) Signal Quality Specifications and
Measurement Guidelines ....................................................................................52
3.2 AGTL+ Signal Quality Specifications and Measurement Guidelines ..................55
3.3 Non-AGTL+ Signal Quality Specifications and Measurement Guidelines...........57
3.3.1 Overshoot/Undershoot Guidelines.........................................................57
3.3.2 Ringback Specification...........................................................................58
3.3.3 Settling Limit Guideline...........................................................................59
3.4 AGTL+ Signal Quality Specifications and Measurement Guidelines
(FC-PGA/FC-PGA2 Packages)...........................................................................59
3.4.1 Overshoot/Undershoot Guidelines (FC-PGA/FC-PGA2 Packages).......59
3.4.2 Overshoot/Undershoot Magnitude (FC-PGA/FC-PGA2 Packages).......59
3.4.3 Overshoot/Undershoot Pulse Duration (FC-PGA/FC-PGA2
Packages) ..............................................................................................60
3.4.4 Activity Factor (FC-PGA/FC-PGA2 Packages) ......................................60

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3.4.5 Reading Overshoot/Undershoot Specification Tables
(FC-PGA/FC-PGA2 Packages)..............................................................61
3.4.6 Determining if a System meets the Overshoot/Undershoot
Specifications (FC-PGA/FC-PGA2 Packages).......................................62
3.5 Non-AGTL+ Signal Quality Specifications and Measurement Guidelines...........64
4.0 Thermal Specifications and Design Considerations.........................................................65
4.1 Thermal Specifications........................................................................................65
4.1.1 Thermal Diode........................................................................................68
5.0 Mechanical Specifications................................................................................................69
5.1 S.E.P. Package...................................................................................................69
5.1.1 Materials Information..............................................................................69
5.1.2 Signal Listing (S.E.P. Package) ............................................................70
5.2 PPGA Package...................................................................................................79
5.2.1 PPGA Package Materials Information....................................................79
5.2.2 PPGA Package Signal Listing................................................................81
5.3 FC-PGA/FC-PGA2 Packages .............................................................................92
5.3.1 FC-PGA Mechanical Specifications .......................................................92
5.3.2 Mechanical Specifications (FC-PGA2 Package)....................................94
5.3.2.1 Recommended Mechanical Keep-Out Zones
(FC-PGA2 Package) .................................................................96
5.3.3 FC-PGA/FC-PGA2 Package Signal List.................................................97
5.4 Processor Markings (PPGA/FC-PGA/FC-PGA2 Packages).............................108
5.5 Heatsink Volumetric Keepout Zone Guidelines.................................................109
6.0 Boxed Processor Specifications.....................................................................................110
6.1 Mechanical Specifications for the Boxed Intel®Celeron®Processor................110
6.1.1 Mechanical Specifications for the S.E.P. Package...............................110
6.1.1.1 Boxed Processor Heatsink Weight..........................................112
6.1.1.2 Boxed Processor Retention Mechanism.................................112
6.1.2 Mechanical Specifications for the PPGA Package...............................113
6.1.2.1 Boxed Processor Heatsink Weight..........................................114
6.1.3 Mechanical Specifications for the FC-PGA/FC-PGA2 Packages.........114
6.1.3.1 Boxed Processor Heatsink Weight..........................................115
6.2 Thermal Specifications......................................................................................115
6.2.1 Thermal Requirements for the Boxed Intel®Celeron®Processor........115
6.2.1.1 Boxed Processor Cooling Requirements ................................115
6.2.1.2 Boxed Processor Thermal Cooling Solution Clip ....................117
6.3 Electrical Requirements for the Boxed Intel®Celeron®Processor ...................117
6.3.1 Electrical Requirements .......................................................................117
7.0 Processor Signal Description.........................................................................................120
7.1 Signal Summaries.............................................................................................126

Datasheet 5
Intel®Celeron®Processor up to 1.10 GHz
Figures 1 Clock Control State Machine...............................................................................16
2 BCLK to Core Logic Offset..................................................................................48
3 BCLK*, PICCLK, and TCK Generic Clock Waveform .........................................49
4 System Bus Valid Delay Timings ........................................................................49
5 System Bus Setup and Hold Timings..................................................................49
6 System Bus Reset and Configuration Timings (For the S.E.P. and
PPGA Packages) ................................................................................................50
7 System Bus Reset and Configuration Timings (For the
FC-PGA/FC-PGA2 Package)..............................................................................50
8 Power-On Reset and Configuration Timings.......................................................51
9 Test Timings (TAP Connection)..........................................................................51
10 Test Reset Timings .............................................................................................51
11 BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins .....53
12 BCLK, TCK, PICCLK Generic Clock Waveform at the Processor
Edge Fingers.......................................................................................................54
13 Low to High AGTL+ Receiver Ringback Tolerance.............................................56
14 Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback .....................57
15 Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform
(FC-PGA/FC-PGA2 Packages)...........................................................................63
16 Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback ....................64
17 Processor Functional Die Layout (CPUID 0686h)...............................................67
18 Processor Functional Die Layout (up to CPUID 0683h)......................................67
19 Processor Substrate Dimensions (S.E.P. Package) ...........................................70
20 Processor Substrate Primary/Secondary Side Dimensions (S.E.P. Package)....70
21 Package Dimensions (PPGA Package)..............................................................79
22 PPGA Package (Pin Side View)..........................................................................81
23 Package Dimensions (FC-PGA Package)...........................................................92
24 Package Dimensions (FC-PGA2 Package).........................................................94
25 Volumetric Keep-Out...........................................................................................96
26 Component Keep-Out .........................................................................................96
27 Package Dimensions (FC-PGA/FC-PGA2 Packages) ........................................97
28 Top Side Processor Markings (PPGA Package)...............................................108
29 Top Side Processor Markings (FC-PGA Package)...........................................108
30 Top Side Processor Markings (FC-PGA2 Package).........................................108
31 Retention Mechanism for the Boxed Intel® Celeron®Processor in the
S.E.P. Package.................................................................................................111
32 Side View Space Requirements for the Boxed Processor in the S.E.P.
Package ............................................................................................................111
33 Front View Space Requirements for the Boxed Processor in the S.E.P.
Package ............................................................................................................112
34 Boxed Intel®Celeron®Processor in the PPGA Package..................................113
35 Side View Space Requirements for the Boxed Processor in the PPGA
Package ............................................................................................................113
36 Conceptual Drawing of the Boxed Intel®Celeron®Processor in the
370-Pin Socket (FC-PGA/FC-PGA2 Packages)................................................114
37 Dimensions of Mechanical Step Feature in Heatsink Base for the
FC-PGA/FC-PGA2 Packages ...........................................................................114
38 Top View Airspace Requirements for the Boxed Processor in the
S.E.P. Package.................................................................................................115

Intel®Celeron®Processor up to 1.10 GHz
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39 Side View Airspace Requirements for the Boxed Intel®Celeron®
Processor in the FC-PGA/FC-PGA2 and PPGA Packages ..............................116
40 Volumetric Keepout Requirements for The Boxed Fan Heatsink......................116
41 Clip Keepout Requirements for the 370-Pin (Top View) ...................................117
42 Boxed Processor Fan Heatsink Power Cable Connector Description ..............118
43 Motherboard Power Header Placement for the S.E.P. Package ......................119
44 Motherboard Power Header Placement Relative to the 370-pin Socket...........119

Datasheet 7
Intel®Celeron®Processor up to 1.10 GHz
Tables 1 Processor Identification.......................................................................................13
2 Voltage Identification Definition...........................................................................20
3Intel
®Celeron®Processor System Bus Signal Groups.......................................22
4 Absolute Maximum Ratings................................................................................24
5 Voltage and Current Specifications.....................................................................25
6 AGTL+ Signal Groups DC Specifications............................................................31
7 Non-AGTL+ Signal Group DC Specifications......................................................32
8 Processor AGTL+ Bus Specifications .................................................................33
9 System Bus AC Specifications (Clock) at the Processor Edge Fingers
(for S.E.P. Package)............................................................................................35
10 System Bus AC Specifications (Clock) at the Processor
Core Pins (for Both S.E.P. and PGA Packages).................................................36
11 System Bus AC Specifications (SET Clock)........................................................37
12 Valid Intel®Celeron®Processor System Bus, Core Frequency..........................38
13 System Bus AC Specifications (AGTL+ Signal Group) at the Processor
Edge Fingers (for S.E.P. Package).....................................................................39
14 System Bus AC Specifications (AGTL+ Signal Group) at the Processor
Core Pins (for S.E.P. Package)...........................................................................39
15 Processor System Bus AC Specifications (AGTL+ Signal Group) at the
Processor Core Pins (for PPGA Package)..........................................................40
16 System Bus AC Specifications (AGTL+ Signal Group) at the Processor
Core Pins (for FC-PGA/FC-PGA2 Packages).....................................................40
17 System Bus AC Specifications (CMOS Signal Group) at the Processor
Edge Fingers (for S.E.P. Package).....................................................................41
18 System Bus AC Specifications (CMOS Signal Group) at the Processor
Core Pins (for Both S.E.P., PGA, and FC-PGA/FC-PGA2 Packages)................41
19 System Bus AC Specifications (CMOS Signal Group) .......................................42
20 System Bus AC Specifications (Reset Conditions)
(for Both S.E.P. and PPGA Packages) ...............................................................42
21 System Bus AC Specifications (Reset Conditions) (for the
FC-PGA/FC-PGA2 Packages) ............................................................................42
22 System Bus AC Specifications (APIC Clock and APIC I/O) at the
Processor Edge Fingers (for S.E.P. Package)....................................................43
23 System Bus AC Specifications (APIC Clock and APIC I/O) at the
Processor Core Pins (For S.E.P. and PGA Packages).......................................44
24 System Bus AC Specifications (APIC Clock and APIC I/O)................................45
25 System Bus AC Specifications (TAP Connection) at the Processor
Edge Fingers (For S.E.P. Package)....................................................................45
26 System Bus AC Specifications (TAP Connection) at the Processor
Core Pins (for Both S.E.P. and PPGA Packages)...............................................46
27 System Bus AC Specifications (TAP Connection) ..............................................47
28 BCLK Signal Quality Specifications for Simulation at the Processor Core
(for Both S.E.P. and PPGA Packages) ...............................................................52
29 BCLK/PICCLK Signal Quality Specifications for Simulation at the
Processor Pins (for the FC-PGA/FC-PGA2 Packages).......................................53
30 BCLK Signal Quality Guidelines for Edge Finger Measurement
(for the S.E.P. Package)......................................................................................54
31 AGTL+ Signal Groups Ringback Tolerance Specifications at the
Processor Core (For Both the S.E.P. and PPGA Packages)..............................55

Intel®Celeron®Processor up to 1.10 GHz
8 Datasheet
32 AGTL+ Signal Groups Ringback Tolerance Specifications at the
Processor Pins (For FC-PGA/FC-PGA2 Packages) ...........................................55
33 AGTL+ Signal Groups Ringback Tolerance Guidelines for Edge Finger
Measurement on the S.E.P. Package.................................................................56
34 Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the
Processor Core (S.E.P. and PPGA Packages)...................................................58
35 Signal Ringback Guidelines for Non-AGTL+ Signal Edge Finger
Measurement (S.E.P. Package)..........................................................................58
36 Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the
Processor Pins (FC-PGA/FC-PGA2 Packages)..................................................58
37 Example Platform Information.............................................................................61
38 66 MHz AGTL+ Signal Group Overshoot/Undershoot Tolerance at
Processor Pins (FC-PGA/FC-PGA2 Packages)..................................................62
39 33 MHz CMOS Signal Group Overshoot/Undershoot Tolerance at
Processor Pins (FC-PGA/FC-PGA2 Packages)..................................................63
40 Processor Power for the PPGA and FC-PGA Packages....................................66
41 Intel®Celeron®Processor for the FC-PGA2 Package Thermal Design Power .67
42 Thermal Diode Parameters (S.E.P. and PPGA Packages).................................68
43 Thermal Diode Parameters (FC-PGA/FC-PGA2 Packages)...............................68
44 Thermal Diode Interface......................................................................................68
45 S.E.P. Package Signal Listing by Pin Number....................................................71
46 S.E.P. Package Signal Listing by Signal Name ..................................................75
47 Package Dimensions (PPGA Package)..............................................................80
48 Information Summary (PPGA Package) .............................................................80
49 PPGA Package Signal Listing by Pin Number....................................................82
50 PPGA Package Signal Listing in Order by Signal Name ....................................87
51 Package Dimensions (FC-PGA Package) ..........................................................93
52 Processor Die Loading Parameters (FC-PGA Package)....................................93
53 Package Dimensions (FC-PGA2 Package) ........................................................95
54 Processor Case Loading Parameters (FC-PGA2 Package)...............................95
55 FC-PGA/FC-PGA2 Signal Listing in Order by Signal Name ...............................98
56 FC-PGA/FC-PGA2 Signal Listing in Order by Pin Number...............................103
57 Boxed Processor Fan Heatsink Spatial Dimensions for the S.E.P. Package ...112
58 Fan Heatsink Power and Signal Specifications.................................................118
59 Alphabetical Signal Reference..........................................................................120
60 Output Signals...................................................................................................126
61 Input Signals .....................................................................................................127
62 Input/Output Signals (Single Driver)..................................................................128
63 Input/Output Signals (Multiple Driver) ...............................................................128

Datasheet 9
Intel®Celeron®Processor up to 1.10 GHz
Revision History
Revision Date Description
-020 January 2002 • Added IHS specifications for 900 MHz, 950 MHz, and 1 GHz.
• Added 566 MHz specification for CPUID of 068Ah.

Intel®Celeron®Processor up to 1.10 GHz
10 Datasheet
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