Intel Pentium III Processor 512K Guide

Low Voltage Intel
®
Pentium
®
III
Processor 512K Dual Processor
Platform
Design Guide
March 2002
Order Number: 273674-001

2Design Guide
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
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Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Low Voltage Intel®Pentium®III processor 512K may contain design defects or errors known as errata which may cause the product to deviate
from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
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Copyright © Intel Corporation, 2002
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Design Guide 3
LV Intel
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Pentium
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Contents
1.0 Introduction ...............................................................................................................................7
1.1 Related Documents ..............................................................................................................7
1.2 Conventions and Terminology..............................................................................................8
2.0 General Design Considerations........................................................................................9
2.1 Nominal Board Stackup........................................................................................................9
2.2 Micro-FCBGA Component Keepout ...................................................................................10
3.0 Processor Host Bus Design..............................................................................................13
3.1 Initial Timing Analysis .........................................................................................................13
3.2 General Topology and Layout Guidelines ..........................................................................14
3.3 Wired-OR Signal Considerations........................................................................................15
3.4 Simulation Methodology .....................................................................................................16
3.5 Trace Routing.....................................................................................................................17
3.6 Layout Rules for AGTL Signals ..........................................................................................17
3.6.1 Ground Reference .................................................................................................17
3.6.2 Reference Plane Splits ..........................................................................................17
3.6.3 CPU Breakout........................................................................................................17
3.6.4 Minimizing Crosstalk..............................................................................................17
3.7 Layout Rules for Non-AGTL (CMOS) Signals ....................................................................18
3.8 Undershoot/Overshoot Requirements ................................................................................18
3.9 Debug Port Routing Guidelines..........................................................................................19
3.9.1 Target System Implementation..............................................................................19
4.0 Clocking ....................................................................................................................................24
4.1 General Clocking Considerations .......................................................................................24
4.2 Single Ended Host Bus Clocking Routing...........................................................................25
4.2.1 CLKREF Filter Implementation..............................................................................27
4.2.2 Single-Ended Clocking BSEL[1:0] Implementation................................................28
4.3 Debug Port Host Clock Connection....................................................................................29
4.4 Clock Driver Decoupling and Power Delivery.....................................................................29
5.0 Power..........................................................................................................................................30
5.1 Terminology........................................................................................................................30
5.2 Typical Power Delivery .......................................................................................................30
5.3 LV Intel®Pentium®III Processor 512K Power Requirements............................................32
5.3.1 Voltage Tolerance..................................................................................................32
5.3.2 Multiple Voltages ...................................................................................................32
5.3.3 Voltage Sequencing...............................................................................................33
5.4 Meeting Dual Processor Power Requirements...................................................................33
5.4.1 Supplying Voltage..................................................................................................33
5.4.2 Decoupling Technology and Transient Response.................................................33
5.5 Recommendations..............................................................................................................35
5.5.1 Decoupling Guidelines for LV Intel®Pentium®III Processor 512K Designs .........35
5.5.2 PLL Filter Recommendations ................................................................................36

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6.0 Thermals...................................................................................................................................38
6.1 THERMTRIP# Requirements .............................................................................................38
6.2 THERMTRIP# Erratum.......................................................................................................38
7.0 System Design Checklist...................................................................................................40
7.1 Introduction.........................................................................................................................40
7.2 Host Interface AGTL Bus and AGTL Signals......................................................................40
7.3 CMOS (Non-AGTL) Signals................................................................................................41
7.4 TAP/ITP Checklist...............................................................................................................42
7.5 Miscellaneous Checklist .....................................................................................................42
Figures
1 Sample Board Stackup.................................................................................................................9
2 Micro-FCBGA Component Keepout ...........................................................................................10
3Micro-FCBGA Package – Top and Bottom Isometric Views ......................................................12
4 System Bus T-Topology .............................................................................................................14
5 Wired-OR Termination Topology................................................................................................16
6 Simple Terminations...................................................................................................................20
7 TCK Termination, DP System ....................................................................................................21
8 PRDYx# Signal Termination.......................................................................................................21
9 RESET# Signal Termination.......................................................................................................22
10 JTAG Signals TDI/TDO for Processor Only ...............................................................................23
11 Host Bus Clock Connections......................................................................................................24
12 Single Ended Clocking Topology - CPU.....................................................................................25
13 Single Ended Clocking Topology................................................................................................25
14 CLKREF Filter Implementation...................................................................................................27
15 Single-Ended Clock BSEL Circuit (133 MHz).............................................................................28
16 Ideal LV Intel®Pentium®III Processor 512K Power Supply Scheme........................................31
17 Power Distribution for a DP System Motherboard......................................................................31
18 Detailed Power Distribution Model .............................................................................................32
19 VRM 8.5 Board Power Distribution Model..................................................................................32
20 1206 Capacitor Pad and Via Layouts.........................................................................................34
21 Processor PLL Filter...................................................................................................................36
22 PLL Power Low Pass Filter Response.......................................................................................37
23 LV Intel Pentium III processor 512K Example THERMTRIP# Workaround Circuit.....................39

Design Guide 5
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Tables
1 Related Documents......................................................................................................................7
2 Micro-FCBGA Package Mechanical Specifications....................................................................11
3 System Timing Equations...........................................................................................................13
4 System Timing Terms.................................................................................................................13
5 System Bus Timing Parameters.................................................................................................14
6 Sample CPU to CPU flight time calculations..............................................................................14
7Trace Lengths for “T” Topology (ServerWorks Chipset).............................................................15
8 Component Values for T Topology.............................................................................................15
9 Wired-OR Values........................................................................................................................16
10 System Signal Layout Guidelines...............................................................................................20
11 JTAG Signal Layout Guidelines..................................................................................................20
12 Execution Signals Routing Guidelines........................................................................................21
13 Debug Port Termination Requirement........................................................................................22
14 Routing Guidelines .....................................................................................................................23
15 Component Values for SE Clocking Topology............................................................................26
16 CLKREF Component Values......................................................................................................27
17 BSEL[1:0] Encoding....................................................................................................................28
18 LV Intel Pentium III processor 512K Bulk Capacitance Recommendations ...............................35
19 THERMTRIP# Timing Requirements..........................................................................................38
20 AGTL Signals..............................................................................................................................40
21 CMOS Signals............................................................................................................................41
22 TAP/ITP Signals .........................................................................................................................42
23 Clock Signals..............................................................................................................................42
24 Miscellaneous Signals................................................................................................................43
25 Power Signals.............................................................................................................................44

6Design Guide
LV Intel
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Revision History
Date Revision Description
March 2002 001 First release of this document.

LV Intel
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Design Guide 7
1.0 Introduction
This design guide is intended to be used by LV Intel Pentium III processor 512K system developers.
This design guide documents Intel’s design recommendations for dual-processor systems based on
the LV Intel®Pentium®III processor 512K with the ServerWorks* HE-SL and LE3 chipset. In
addition to providing design recommendations such as layout and routing guidelines, this
document also addresses possible system design issues such as processor power delivery, layout
considerations for mechanical pieces, EMI design impacts and system bus decoupling.
Carefully follow the design information, debug recommendations and system checklist presented
in this document. These design guidelines have been developed to ensure maximum flexibility for
board designers while reducing the risk of board related issues. The design information provided in
this document falls into one of two categories:
•Design Recommendations are necessary to meet the timing and signal quality specifications.
•Design Considerations are suggestions for platform design. These provide one way to meet
the design recommendations. They are based on the reference platforms designed by Intel.
They could be used as an example, but may not be applicable to your particular design.
Note: The guidelines recommended in this document are based on experience and simulation work done
at Intel while developing LV Intel Pentium III processor 512K based systems. The
recommendations are subject to change.
1.1 Related Documents
The reader of this specification should also be familiar with the material and concepts presented in
the following documents:
Table 1. Related Documents
Document Order Number
P6 Family of Processors Hardware Developer’s Manual 244001
IA-32 Intel
®
Architecture Software Developer’s Manual
• Volume I: Basic Architecture
• Volume II: Instruction Set Reference
• Volume III: System Programming Guide
245470
245471
245472
VRM 8.5 DC-DC Converter Design Guidelines 249659
Low Voltage Intel
®
Pentium
®
III Processor 512K Datasheet 273673
Low Voltage Intel
®
Pentium
®
III Processor 512K (DP) Thermal Design Guide 273675
Low Voltage Intel
®
Pentium
®
III Processor 512K/815E Chipset Platform Design
Guide
273676
Intel
®
Pentium
®
III Processor Specification Update 244453
Intel Processor Identification and the CPUID Instruction 241618

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8Design Guide
1.2 Conventions and Terminology
For this document, the following terminology applies.
•Low Voltage Intel®Pentium®III Processor 512K - Intel’s name for the next generation
Intel®Pentium®III processor based on Intel’s 0.13-micron (i.e., 1.25 V VTT / AGTL)
technology. This processor contains 512 Kbytes of L2 cache, is dual processor capable, and
has a 133 MHz processor side bus.
•Micro FCBGA - Micro Flip Chip Ball Grid Array. The package technology used on the LV
Intel Pentium III processor 512K.
•Keep-out zone - The area on or near a Micro FCBGA packaged processor that system designs
can not utilize.
•Processor - For this document, the term processor is the generic form of the LV Intel Pentium
III processor 512K for the Micro FCBGA package.

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Design Guide 9
2.0 General Design Considerations
This section documents layout and routing guidelines for LV Intel Pentium III processor 512K
platforms. This section does not discuss the functional aspects of any bus, or the layout guidelines
for an add-in device.
If the guidelines listed in this document are not followed, it is very important that thorough signal
integrity and timing simulations are completed for each design. Any deviation from the guidelines
should be simulated. Even when the guidelines are followed, Intel recommends that you simulate
critical signals to ensure proper signal integrity and flight time.
The trace impedance noted (i.e., 55 Ω± 10%) is the “nominal” trace impedance for a 4.5-mil wide
trace. Nominal trace impedance is the impedance of the trace when not subjected to the fields
created by changing current in neighboring traces. When calculating flight times, it is important to
consider the minimum and maximum impedance of a trace based on the switching of neighboring
traces. Using wider spaces between the traces can minimize this trace-to-trace coupling. In
addition, these wider spaces reduce settling time.
Coupling between two traces is a function of the coupled length, the distance separating the traces,
the signal edge rate, and the degree of mutual capacitance and inductance. To minimize the effects
of trace-to-trace coupling, follow the routing guidelines documented in this section.
2.1 Nominal Board Stackup
Figure 1 is an example of a 14-layer board stack-up. The impedance of all the signal layers should
be 55 Ω± 10%. A lower trace impedance reduces signal edge rates, overshoot, and undershoot, and
has less crosstalk than a higher trace impedance. A higher trace impedance increases edge rates and
may slightly decrease signal flight times. Please note that thicker core may help reduce board
warpage issues.
Figure 1. Sample Board Stackup
Signal Layer
Power Plane
Signal Layer
Ground Plane
Signal Layer
Signal Layer
Power Plane
Ground Plane
Signal Layer
Signal Layer
Ground Plane
Signal Layer
Power Plane
Signal Layer

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Additional guidelines on board stack-up, placement, and layout include the following.
•The board impedance (Z) should be between 49.5 Ωand 60.5 Ω(55 Ω± 10% is
recommended).
•The dielectric process variation in the PCB fabrication should be minimized.
•The ground plane should not be split on the ground plane layer.
•Keep vias for decoupling capacitors as close to the capacitor pads as possible.
2.2 Micro-FCBGA Component Keepout
Figure 2 shows the keepout zones and dimensions for the Micro-FCBGA package. Table 2
provides the values for the mechanical specifications.
Figure 2. Micro-FCBGA Component Keepout
35 (E)
35 (D)
PIN A1 CORNER
E1
D1
A
Ø0.78(b)
479 places
K2
SUBSTRATE KEEPOUT ZONE
DO NOT CONTACT PACKAGE
INSIDE THIS LINE
7 (K1)
8 places
5 (K)
4 places
NOTE:
Alldimensions in millimeters. Values shownare for reference only
A2
0.20

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Table 2. Micro-FCBGA Package Mechanical Specifications
Symbol Parameter Min Max Unit
A Overall height, as delivered (1) 2.27 2.77 mm
A2 Die height 0.854 mm
b Ball diameter 0.78 mm
D Package substrate length 34.9 35.1 mm
E Package substrate width 34.9 35.1 mm
D1 Die length 11.18 mm
E1 Die width 7.19 mm
e Ball pitch 1.27 mm
N Ball count 479 each
K Keep-out outline from edge of package 5 mm
K1 Keep-out outline at corner of package 7 mm
K2 Capacitor keep-out height —0.7 mm
S Package edge to first ball center 1.625 mm
-- Solder ball coplanarity 0.2 mm
Pdie Allowable pressure on the die for thermal solution — 689 kPa
W Package weight 4.5 g
NOTES:
1. All dimensions are subject to change.
2. Overall height as delivered. Values were based on design specifications and tolerances. Final height after
surface mount depends on OEM motherboard design and SMT process.

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Figure 3. Micro-FCBGA Package – Top and Bottom Isometric Views
TOP VIEW BOTTOM VIEW
LABEL DIE
PACKAGE KEEPOUT
CAPACITOR AREA

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3.0 Processor Host Bus Design
3.1 Initial Timing Analysis
To determine the available flight time window, perform an initial timing analysis. Analysis of setup
and hold conditions will determine the minimum and maximum flight time bounds for the system
bus. Use the following equations to establish the system flight time limits.
Component timings for the LV Intel Pentium III processor 512K are available in the Low Voltage
Intel®Pentium®
III Processor 512K Datasheet (order number 273673). Please contact your chipset
vendor for documentation concerning the chipset component timing.
Table 5 provides recommended values for system timings. Skew and jitter values for the clock
generator device come from the clock driver vendor’s datasheet. The PCB skew specification is
based on the results of extensive simulations performed by Intel engineers. The Tadj value is based
on Intel’s experience with systems that use previous generations of processors.
Table 3. System Timing Equations
Equation
Tflight,min >= Thold - Tco,min + Tskew
Tflight,max <= Tcycle - Tco,max - Tsu - Tskew - Tjit - Tadj
Table 4. System Timing Terms
Term Description
Tcycle System cycle time. Defined as the reciprocal of the frequency.
Tflight,min Minimum system flight time.
Tflight,max Maximum system flight time.
Tco,max Maximum driver delay from input clock to output data.
Tco,min Minimum driver delay from input clock to output data.
Tsu Minimum setup time. Defined as the time for which the input data must be valid prior to the
input clock.
Thold Minimum hold time. Defined as the time for which the input data must remain valid after the
input clock.
Tskew Clock generator skew. Defined as the maximum delay variation between output clock
signals from the system clock generator, the maximum delay variation between clock
signals due to system board variation and chipset loading variation.
Tjit Clock jitter. Defined as the maximum edge to edge variation in a given clock signal.
Tadj
Multi-bit timing adjustment factor. This term accounts for the additional delay that occurs in
the network when multiple data bits switch in the same cycle. The adjustment factor
includes mechanisms such as package and PCB crosstalk, high inductance current return
paths, and simultaneous switching noise.

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Table 6 summarizes the flight time requirements for CPU to CPU transfers that result from using
the component timing specifications and recommended system timings. All component values
should be verified against the latest specifications before proceeding with analysis.
3.2 General Topology and Layout Guidelines
Intel recommends that all LV Intel Pentium III processor 512K dual-processing platforms use a
system bus T-topology. Figure 4 shows a high level diagram of this topology. The pull-up resistors
shown inside the processor packages are the processor’s on-die AGTL termination, since the LV
Intel Pentium III processor 512K has on-die termination.
Table 5. System Bus Timing Parameters
Timing Term Value
Tskew [ns] 0.25
Tjit [ns] 0.20
Tadj [ns] 0.50
Tcycle [ns] (133 MHz) 7.50
Table 6. Sample CPU to CPU flight time calculations
Driver Receiver Calculation
CPU CPU Tflight,min >= 1.0 - 0.4 + 0.25 = 0.85 ns
CPU CPU Tflight,max <= 7.5 - 3.25 - 0.95 - 0.25 - 0.2 - 0.5 = 2.35 ns
Figure 4. System Bus T-Topology
Chipset
CPU0 CPU1
L0 L1
L2
RTTCTRL
VTT
R1 R2
VTT
R3
RTTCTRL
R4

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Table 7 contains the length specifications for the segments of the T-topology. Note that lengths L0
and L1 must be length matched to within 0.25 inches (per net, not between nets). Table 8 contains
the component values for the T-topology.
3.3 Wired-OR Signal Considerations
The Wired-OR signals of the processor’s host bus require additional consideration. The Wired-OR
signals in a LV Intel Pentium III processor 512K processor system are HIT#, HITM#, BNR#,
AERR#, BERR#, and BINIT#. The Wired-OR signals may be driven by multiple bus agents at the
same time, such as both processors asserting the HIT# signal to signify a cache hit on a line they
both contain. With multiple driving agents, these signals are susceptible to being overdriven, which
results in excessive overshoot and ringback on these signals.
Terminating the Wired-OR signals at the chipset branch of the T topology reduces the effect of
multiple driving agents on these signals. Intel recommends that system designers carefully examine
the signal integrity of these signals and optionally implement the circuit shown in Figure 5. This
recommendation will work correctly for systems designed with the standard T topology.
Please note that the incorporation of Wired-OR termination is optional. Intel has not seen any
system failures on systems which do not implement the Wired-OR termination recommendations.
Therefore, systems which are already in the latter phases of design may wish to forgo
implementing these recommendations until an opportunity presents itself to incorporate them.
However, it is the responsibility of the system designer to ensure that the signal quality of these
signals meets the component specifications.
Table 7. Trace Lengths for “T” Topology (ServerWorks Chipset)
Segment Min Length (inches) Max Length (inches)
L0 2.8 3.4
L1 2.8 3.4
L2 1.7 2.3
Table 8. Component Values for T Topology
Reference Value Tolerance
R1 (on chip) R3 N/A
R2 (on chip) R4 N/A
R3 68Ω+/- 10%
R4 68Ω+/- 10%

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Please note that the value range for R1 present a set of tradeoffs for flight time and dampening
effects. Choosing a value near the upper end of the range (around 200 Ω) impacts the flight times
the least, but provides minimal dampening. Choosing a value at the lower end of the range (around
100 Ω), provides optimal dampening but has a larger impact on the signal flight times. Intel
recommends a value of 150 Ω±10% as a reasonable tradeoff between dampening and flight time.
3.4 Simulation Methodology
Analog simulations are recommended for high-speed system bus designs. Start simulations prior to
layout. Pre-layout simulations provide a detailed picture of the working “solution space” that meets
flight time and signal quality requirements. By basing board layout guidelines on the solution
space, the iterations between layout and post-layout simulations can be reduced.
Figure 5. Wired-OR Termination Topology
Table 9. Wired-OR Values
Item Min Max Notes
L0 2.8” 3.4”
L1 2.8” 3.4”
L2 1.70” 2.3”
L3 1.5” Route to shortest length
L4 0“ 0.2” Should be as short as possible. Optimal case is to make this value
zero, making the L3 stub come after the chipset pin.
R1 100 Ω220 ΩThe range of values has tradeoffs in flight time and dampening
effects. 150 Ω±10% is a base recommendation.
Chipset “T” Stub
VTT
R1
L2
L4
L0 L1 CPU 1CPU 0
L3
Chipset

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Intel recommends running simulations at the device pads for signal quality and at the device pins
for timing analysis. However, simulation results at the device pins may be used later to correlate
simulation performance against actual system measurements.
The Low Voltage Intel®Pentium®
III Processor 512K I/O Signal Integrity Models are available
from http://www.intel.com/design/pentiumiii/devtools.
3.5 Trace Routing
The following guidelines should be followed when routing the AGTL host bus signal traces:
•Traces should have an impedance of 55 Ω± 10%
•The nominal trace width should be 4.5 mils.
•The L0 and L1 lengths in Table 7 should be matched to within 0.25 inches (per net, not
between nets).
•Minimize the number of vias and layer transitions.
•Minimum 10 mils spacing
3.6 Layout Rules for AGTL Signals
3.6.1 Ground Reference
It is strongly recommended that AGTL signals be routed on the signal layer next to the ground
layer (referenced to ground). It is important to provide effective signal return path with low
inductance. The best signal routing is directly adjacent to a solid GND plane with no splits or cuts.
Eliminate parallel traces between layers not separated by a power or ground plane.
3.6.2 Reference Plane Splits
Splits in reference planes disrupt signal return paths and increase overshoot/undershoot due to
significantly increased inductance. For optimal signal integrity, high-speed signals should not be
routed over power plane splits.
3.6.3 CPU Breakout
Intel strongly recommends that AGTL signals do not traverse multiple signal layers. Intel
recommends breaking out all signals from the CPU on the same layer. If routing is tight, breakout
from the CPU on the opposite routing layer over a ground reference, and cross over to the main
signal layer near the CPU.
Note: Following the above layout rules is critical for AGTL signal integrity.
3.6.4 Minimizing Crosstalk
Adhering to the following general rules will minimize the impact of crosstalk in the high speed
AGTL bus design:
•Maximize the space between traces. Maintain a minimum of 10mils (assuming a 4.5 mil trace)
between trace edges wherever possible. It may be necessary to use tighter spacing when

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routing between component pins. Minimize the distance that traces have to be close and
parallel to each other, and maximize the distance between the sections when the spacing
restrictions relax.
•Avoid parallelism between signals on adjacent layers if there is no AC reference plane
between them. As a rule of thumb, route adjacent layers orthogonally.
•Since AGTL is a low signal swing technology, it is important to isolate AGTL signals from
other signals by at least 25 mils. This will avoid coupling from signals that have larger voltage
swings, such as 3.3 V system memory.
•Select a board stack-up that minimizes the coupling between adjacent signals. Minimize the
nominal characteristic impedance within the AGTL specification. This can be done by
minimizing the height of the trace from its reference plane, which minimizes the crosstalk.
•Route AGTL address, data and control signals in separate groups to minimize crosstalk
between groups. Keep at least 25 mils between each group of signals.
•Minimize the dielectric used in the system. This places the traces closer to their reference
plane and reduces the crosstalk magnitude.
•Minimize the dielectric process variation used in the PCB fabrication.
•Minimize the cross sectional area of the traces. This can be done by using narrower traces or
by using thinner copper, but the trade-off for this smaller cross sectional area is a higher trace
resistivity that can reduce the falling edge noise margin because of the I*R loss along the trace.
3.7 Layout Rules for Non-AGTL (CMOS) Signals
The following layout rules should be used for all CMOS signals:
•The trace impedance should be 55 Ω+/- 10%.
•External termination resistors should be placed in the middle of the trace to prevent long
reflection times and reduce reflection ledges.
•Do not route CMOS traces next to AGTL traces. Switching noise on the AGTL traces may
attack the nearby CMOS traces.
•Route a CMOS trace on one signal layer. If layer switching is unavoidable, minimize the
number of layer switches.
•Try to use only one reference plane for a trace (either Vcc or Vss).
•Although CMOS signals are slow, they may still have speed path problems. This is especially
true for APIC clock and APIC data. Try to avoid long routes.
3.8 Undershoot/Overshoot Requirements
Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high
voltage or below VSS. The overshoot guideline limits transitions beyond VCC or VSS due to the
fast signal edge rates. The processor can be damaged by repeated overshoot events on buffers if the
charge is large enough (i.e., if the overshoot is great enough). Determining the impact of an
overshoot/undershoot condition requires knowledge of the magnitude, the pulse direction and the
activity factor (AF). Permanent damage to the processor is the likely result of excessive
overshoot/undershoot. Violating the overshoot/undershoot guideline makes satisfying the ringback
specification difficult.

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When performing simulations to determine impact of overshoot and undershoot, ESD diodes must
be properly characterized. ESD protection diodes do not act as voltage clamps and will not provide
overshoot or undershoot protection. ESD diodes modeled within Intel I/O buffer models do not
clamp undershoot or overshoot and will yield correct simulation results. If other I/O buffer models
are being used to characterize the LV Intel Pentium III processor 512K performance, care must be
taken to ensure that ESD models do not clamp extreme voltage levels. Intel I/O buffer models also
contain I/O capacitance characterization. Therefore, removing the ESD diodes from an I/O buffer
model will impact results and may yield excessive overshoot/undershoot.
Refer to the latest Low Voltage Intel®Pentium®
III Processor 512K Datasheet for detailed
undershoot/overshoot requirements.
3.9 Debug Port Routing Guidelines
This chapter describes the processor debug port, in-target probe (ITP) platform design guidelines.
3.9.1 Target System Implementation
Follow the implementation guidelines provided in this section to help ensure a fully functional ITP
debug system. These guidelines are preliminary, and additional changes may be required. The
signals involved in the ITP debug system are high speed signals and must be routed with high
speed design considerations in mind. The implementation offers flexibility in areas such as JTAG
routing (i.e., scan chain), addition of non-ITP compliant parts, and clock rate. However, the
implementation is not flexible in system and execution signal connections.
Intel uses an ITP for internal debug and system validation and recommends that all system designs
include a debug port.
3.9.1.1 Signal Layout Guidelines
The debug port (Test Access Port) is part of the processor scan chain. It must be connected to the
bus clock and system bus signals. This implies that the designer will place the Debug Port within
12 inches of the nearest processor.
There are three signal groups within the debug port, as described in the datasheet. Each group has a
different set of layout requirements. The system signals are special ITP-specific signals and are
both inputs and outputs. The JTAG signals are system resources and may be shared with local
JTAG tools. Input and output signals are available. The execution signals are a combination of
CMOS and AGTL level signals. They are both inputs and outputs to the ITP.
The ITP TCK and TMS signals must be routed with a maximum trace resistance of 2.0 ohm to
reduce the amount of DC shifting on these signals. This is due to the small termination values that
are recommended for these signals.
System Signal Layout Guidelines
Table 10 provides the system signal layout guidelines. See Table 13 for termination values.

LV Intel
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Pentium
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III Processor 512K Dual Processor Platform
20 Design Guide
JTAG Signal Layout Guidelines
Reflections on TCK that cause mid-threshold ringing will render the primary system debug tool
inoperative. Simulate the behavioral model, and verify signal integrity using your system bus
signal analysis tools. The following table provides the JTAG signal layout guidelines. It is highly
recommended that TCK be simulated to ensure proper signal quality is maintained.
Table 10. System Signal Layout Guidelines
Signal Routing Notes Sample Layout
POWERON Route with normal trace 2 to 6 inches to the debug port
connector Figure 6a
BCLK, BCLK# N/A
DBRESET#, BSEN#,
DBINST# Figure 6a
Figure 6. Simple Terminations
Table 11. JTAG Signal Layout Guidelines
Signal Routing Notes Sample Layout
TCK Critical JTAG signal which requires timing and signal integrity considerations; driver is 74VCX16245 with external edge rate control on
TCK Figure 7
TMS, TDI,
TDO Critical JTAG signal which requires timing and signal integrity considerations. ITP driver is 74VCX16245. TMS must be routed with TCK. Figure 6a
TRST# Pull-down resistors should be used to force TRST# assertion (low). Figure 6b