Intel Xeon 5500 Series Technical manual

Reference Number: 321324-017
Intel® Xeon® Processor 5500
Series
Specification Update
February 2014

2Intel® Xeon® Processor 5500 Series
Specification Update, February 2014
Legal Lines and Disclaimers
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Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
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changes to them.
The Intel® Xeon® Processor 5500 Series may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
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Copyright © 2014, Intel Corporation. All Rights Reserved.

Intel® Xeon® Processor 5500 Series 3
Specification Update, February 2014
Contents
Revision History...............................................................................................................5
Preface ..............................................................................................................................7
Summary Tables of Changes........................................................................................10
Identification Information..............................................................................................20
Errata...............................................................................................................................27
Specification Changes...................................................................................................79
Specification Clarifications...........................................................................................80
Documentation Changes...............................................................................................81
§

4Intel® Xeon® Processor 5500 Series
Specification Update, February 2014

Intel® Xeon® Processor 5500 Series 5
Specification Update, February 2014
Revision History
Revision Version Description Date
321324 -001 Public Release March 2009
321324 -002 Added Errata AAK102 and AAK103 April 2009
321324 -003 Added Errata AAK104 and AAK105 May 2009
321324 -004 Added Errata AAK106 through AAK110 June 2009
321324 -005 Added Errata AAK111 through AAK115 July 2009
321324 -006 Added Errata AAK116 through AAK121
Added SLBGE, SLBKC and SLBGF to CPU Identification Table September 2009
321324 -007 Added Errata AAK122 through AAK127 October 2009
321324 -008 Updated Spec Update to match Nov. NDA Spec Update
Added AAK128 through AAK150 December 2009
321324 -009 Added Erratum AAK151 February 2010
321324 -010 Added Erratum AAK152 March 2010
321324 -011 Added Erratum AAK153 April 2010
321324 -012 Added Errata AAK154 and AAK155 July 2010
321324 -013 Added Errata AAK156 and AAK157. Updated AAK76. Included
Microcode Updates tables. December 2010
321324 -014 Added Errata AAK158 through AAK160 January 2011
321324 -015 Added Errata AAK161 through AAK166 April 2011
321324 -016 Added Errata AAK167-AAK171 August 2013
322324 -017 Added Errata AAK172-AAK181 February 2014

6Intel® Xeon® Processor 5500 Series
Specification Update, February 2014
Preface
This document is an update to the specifications contained in the “Affected Documents”
table below. This document is a compilation of device and documentation errata,
specification clarifications and changes. It is intended for hardware system
manufacturers and software developers of applications, operating systems, or tools.
Information types defined in “Nomenclature” are consolidated into the specification
update and are no longer published in other documents.
This document may also contain information that was not previously published.
Affected Documents
Related Documents
Document Title Document Number/
Location
Intel® Xeon® Processor 5500 Series Datasheet Volume 1 and 2 321321 & 321322
Document Title Document Number/
Location
AP-485, Intel® Processor Identification and the CPUID Instruction http://www.intel.com/
design/processor/applnots/
241618.htm
Intel® 64 and IA-32 Architectures Software Developer’s Manual
• Volume 1: Basic Architecture
• Volume 2A: Instruction Set Reference Manual A-M
• Volume 2B: Instruction Set Reference Manual N-Z
• Volume 3A: System Programming Guide
• Volume 3B: System Programming Guide
http://www.intel.com/
products/processor/
manuals/index.htm
Intel® 64 and IA-32 Intel Architecture Optimization Reference Manual http://www.intel.com/ products/processor/
manuals/index.htm
Intel® 64 and IA-32 Architectures Software Developer’s Manual
Documentation Changes http://www.intel.com/
design/processor/specupdt/
252046.htm

Intel® Xeon® Processor 5500 Series 7
Specification Update, February 2014
Nomenclature
Errata are design defects or errors. These may cause the Intel® Xeon® Processor
5500 Series behavior to deviate from published specifications. Hardware and software
designed to be used with any given stepping must assume that all errata documented
for that stepping are present on all devices.
S-Spec Number is a five-digit code used to identify products. Products are
differentiated by their unique characteristics, for example, core speed, L2 cache size,
package type, and so forth, as described in the processor identification information
table. Read all notes associated with each S-Spec number.
Specification Changes are modifications to the current published specifications.
These changes will be incorporated in any new release of the specification.
Specification Clarifications describe a specification in greater detail or further
highlight a specification’s impact to a complex design situation. These clarifications will
be incorporated in any new release of the specification.
Documentation Changes include typos, errors, or omissions from the current
published specifications. These will be incorporated in any new release of the
specification.
Note: Errata remain in the specification update throughout the product’s lifecycle, or until a
particular stepping is no longer commercially available. Under these circumstances,
errata removed from the specification update are archived and available upon request.
Specification changes, specification clarifications and documentation changes are
removed from the specification update when the appropriate changes are made to the
appropriate product specification or user documentation (datasheets, manuals, and so
forth).

8Intel® Xeon® Processor 5500 Series
Specification Update, February 2014
Summary Tables of Changes
The following tables indicate the errata, specification changes, specification
clarifications, or documentation changes which apply to the Intel® Xeon® Processor
5500 Series product. Intel may fix some of the errata in a future stepping of the
component, and account for the other outstanding issues through documentation or
specification changes as noted. These tables uses the following notations:
Codes Used in Summary Tables
Stepping
X: Errata exists in the stepping indicated. Specification Change or
Clarification that applies to this stepping.
(No mark)
or (Blank box): This erratum is fixed in listed stepping or specification change
does not apply to listed stepping.
Page
(Page): Page location of item in this document.
Status
Doc: Document change or update will be implemented.
Plan Fix: This erratum may be fixed in a future stepping of the product.
Fixed: This erratum has been previously fixed.
No Fix: There are no plans to fix this erratum.
Row
Change bar to left of table row indicates this erratum is either new or modified from the
previous version of the document.
Each Specification Update item is prefixed with a capital letter to distinguish the
product. The key below details the letters that are used in Intel’s microprocessor
Specification Updates:

Intel® Xeon® Processor 5500 Series 9
Specification Update, February 2014
Errata (Sheet 1 of 7)
Number Steppings Status ERRATA
C-0 C-1 D-0
AAK1. XXXNoFix
MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB
Error
AAK2. XXXNoFix
Debug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled
Breakpoints
AAK3. XXXNoFixMONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang
AAK4. XXXNoFix
Corruption of CS Segment Register During RSM While Transitioning From Real
Mode to Protected Mode
AAK5. XXXNoFixThe Processor May Report a #TS Instead of a #GP Fault
AAK6. XXXNoFix
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page
Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or
Lead to Memory-Ordering Violations
AAK7. XXXNoFix
Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher
Priority Interrupts/Exceptions and May Push the Wrong Address Onto the Stack
AAK8. XXXNoFixPerformance Monitor SSE Retired Instructions May Return Incorrect Values
AAK9. XXXNoFixPremature Execution of a Load Operation Prior to Exception Handler Invocation
AAK10. XXXNoFixMOV To/From Debug Registers Causes Debug Exception
AAK11. XXXNoFix
Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR Image Leads
to Partial Memory Update
AAK12. XXXNoFixValues for LBR/BTS/BTM will be Incorrect after an Exit from SMM
AAK13. XXXNoFix
Single Step Interrupts with Floating Point Exception Pending May Be
Mishandled
AAK14. XXXNoFixFault on ENTER Instruction May Result in Unexpected Values on Stack Frame
AAK15. XXXNoFix
IRET under Certain Conditions May Cause an Unexpected Alignment Check
Exception
AAK16. XXXNoFix
General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be
Preempted
AAK17. XXXNoFix
General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit
Violation above 4-G Limit
AAK18. XXXNoFix
LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt
Occurs in 64-bit Mode
AAK19. XXXNoFix
Performance Monitoring Events for Read Miss to Level 3 Cache Fill Occupancy
Counter may be Incorrect
AAK20. XXXNoFixA VM Exit on MWAIT May Incorrectly Report the Monitoring Hardware as Armed
AAK21. XXXNoFixMemory Aliasing of Code Pages May Cause Unpredictable System Behavior
AAK22. XXXNoFixDelivery Status of the LINT0 Register of the Local Vector Table May be Lost
AAK23. XXXNoFixPerformance Monitor Event SEGMENT_REG_LOADS Counts Inaccurately
AAK24. XXXNoFix
#GP on Segment Selector Descriptor that Straddles Canonical Boundary May
Not Provide Correct Exception Error Code
AAK25. XXXNoFix
Improper Parity Error Signaled in the IQ Following Reset When a Code
Breakpoint is Set on a #GP Instruction
AAK26. XXXNoFix
An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/
POP SS Instruction if it is Followed by an Instruction That Signals a Floating
Point Exception
AAK27. XXXNoFixIA32_MPERF Counter Stops Counting During On-Demand TM1
AAK28. XXXNoFix
Intel® QuickPath Interconnect (Intel® QPI) Memory Controller May Hang If
Uncorrectable ECC Errors Occur on Both Channels in Mirror Channel Mode

10 Intel® Xeon® Processor 5500 Series
Specification Update, February 2014
AAK29. XXXNoFix
Simultaneous Correctable ECC Errors on Different Memory Channels With
Patrol Scrubbing Enabled May Result in Incorrect Information Being Logged
AAK30. XXXNoFix
Intel QPI Memory Controller tTHROT_OPREF Timings May be Violated During
Self Refresh Entry
AAK31. XXXNoFixProcessor May Over Count Correctable Cache MESI State Errors
AAK32. XXXNoFix
Synchronous Reset of IA32_APERF/IA32_MPERF Counters on Overflow Does
Not Work
AAK33. XXXNoFIx
Disabling Thermal Monitor While Processor is Hot, Then Re-enabling, May
Result in Stuck Core Operating Ratio
AAK34. XX FixedThe PECI Throttling Counter May Not be Accurate
AAK35. XXXNoFix
PECI Does Not Support PCI Configuration Reads/Writes to Misaligned
Addresses
AAK36. XXXNoFixOVER Bit for IA32_MCi_STATUS Register May Get Set on Specific lnternal Error
AAK37. XXXNoFix
Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause
an Unexpected Interrupt
AAK38. XX FixedA Processor Core May Not Wake Up from S1 State
AAK39. XXXNoFixReading Reserved APIC Registers May Not Signal an APIC Error
AAK40. XX Fixed
A Logical Processor Receiving a SIPI After a VM Entry Into WFS State May
Become Unresponsive
AAK41. XXXNoFix
Memory Controller May Deliver Incorrect Data When Memory Ranks Are In
Power-Down
AAK42. XXXNoFixFaulting MMX™ Instruction May Incorrectly Update x87 FPU Tag Word
AAK43. XX Fixed
A Floating-Point Store Instruction May Cause an Unexpected x87 FPU Floating-
Point Error (#MF)
AAK44. XX FixedIncorrect TLB Translation May Occur After Exit From C6
AAK45. XFixedUSB 1.1 ISOCH Audio Glitches with Intel QPI Locks and Deep C-States
AAK46. XX Fixed
Stack Pointer May Become Incorrect In Loops With Unbalanced Push and Pop
Operations
AAK47. XXXNoFix
A P-state Change While Another Core is in C6 May Prevent Further C-state and
P-state Transitions
AAK48. XXXNoFixCertain Store Parity Errors May Not Log Correct Address in IA32_MCi_ADDR
AAK49. XXXNoFix
xAPIC Timer May Decrement Too Quickly Following an Automatic Reload While
in Periodic Mode
AAK50. XXXNoFix
Certain Undefined Opcodes Crossing a Segment Limit May Result in #UD
Instead of #GP Exception
AAK51. XXXNoFixIndication of A20M Support is Inverted
AAK52. XXXNoFix
Reported Memory Type May Not Be Used to Access the VMCS and Referenced
Data Structures
AAK53. XX FixedAfter VM Entry, Instructions May Incorrectly Operate as if CS.D=0
AAK54. XX FixedAn Intel QPI Link in a DP Configuration May Hang Due to Flit Prioritization
AAK55. XX FixedSpurious Machine Check Error May Occur When Logical Processor is Woken Up
AAK56. XXXNoFixB0-B3 Bits in DR6 For Non-Enabled Breakpoints May be Incorrectly Set
AAK57. XXXNoFixCore C6 May Clear Previously Logged TLB Errors
AAK58. XXXNoFix
Processor May Hang When Two Logical Processors Are in Specific Low Power
States
AAK59. XXXNoFixMOVNTDQA From WC Memory May Pass Earlier Locked Instructions
Errata (Sheet 2 of 7)
Number Steppings Status ERRATA
C-0 C-1 D-0

Intel® Xeon® Processor 5500 Series 11
Specification Update, February 2014
AAK60. XXXNoFixPerformance Monitor Event MISALIGN_MEM_REF May Over Count
AAK61. XXXNoFix
Changing the Memory Type for an In-Use Page Translation May Lead to
Memory-Ordering Violations
AAK62. XX Fixed
Writes to IA32_CR_PAT or IA32_EFER MSR May Cause an Incorrect ITLB
Translation
AAK63. XX FixedThe “Virtualize APIC Accesses” VM-Execution Control May be Ignored
AAK64. XXXNoFix
In Memory Lockstep Mode Per DIMM Correctable ECC Errors Are Logged
Incorrectly
AAK65. XX FixedC6 Transitions May Cause Spurious Updates to the xAPIC Error Status Register
AAK66. XX Fixed
Critical ISOCH Traffic May Cause Unpredictable System Behavior When Write
Major Mode Enabled
AAK67. XXXNoFixRunning with Write Major Mode Disabled May Lead to a System Hang
AAK68. XXXNoFixMemory Controller Address Parity Error Injection Does Not Work Correctly
AAK69. XXXNoFixMemory Controller Opportunistic Refreshes Might be Missed
AAK70. XXXNoFix
Delivery of Certain Events Immediately Following a VM Exit May Push a
Corrupted RIP Onto The Stack
AAK71. XXXNoFix
The Combination of a Bus Lock and a Data Access That is Split Across Page
Boundaries May Lead to Processor Livelock
AAK72. XNoFixCPUID Instruction Returns Incorrect Brand String
AAK73. XXXNoFix
An Unexpected Page Fault May Occur Following the Unmapping and Re-
mapping of a Page
AAK74. XXXNoFix
Infinite Stream of Interrupts May Occur if an ExtINT Delivery Mode Interrupt is
Received while All Cores in C6
AAK75. XXXNoFixTwo xAPIC Timer Event Interrupts May Unexpectedly Occur
AAK76. XXXNoFix
EOI Transaction May Not be Sent if Software Enters Core C6 During an
Interrupt Service Routine
AAK77. XXXNoFixFREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS During SMM
AAK78. XXXNoFix
PEBS Records For Load Latency Monitoring May Contain an Incorrect Linear
Address
AAK79. X1X1XNoFixPEBS Field “Data Linear Address” is Not Sign Extended to 64 Bits
AAK80. XXXNoFixCore C6 May Not Operate Correctly in the Presence of Bus Locks
AAK81. X1X1XNoFix
USB 1.1 ISOCH Audio Glitches With Intel QPI L1 and Package C6 in a DP
Configuration
AAK82. XXXNoFix
Intel® Turbo Boost Technology May be Limited Immediately After Package C-
state Exit with Intel QPI L1 Mode Disabled
AAK83. XXXNoFixAPIC Error “Received Illegal Vector” May be Lost
AAK84. XXXNoFix
CPUID Incorrectly Indicates the UnHalted Reference Cycle Architectural Event
is Supported
AAK85. XX Fixed
Architectural Performance Monitor Event ‘Branch Misses Retired’ is Counted
Incorrectly
AAK86. XXXNoFix
DR6.B0-B3 May Not Report All Breakpoints Matched When a MOV/POP SS is
Followed by a Store Instruction
AAK87. XXXNoFix
An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May also Result in a
System Hang
AAK88. XXXNoFixIA32_PERF_GLOBAL_CTRL MSR May be Incorrectly Initialized
AAK89. XXXNoFixECC Errors Can Not be Injected on Back-to-Back Writes
Errata (Sheet 3 of 7)
Number Steppings Status ERRATA
C-0 C-1 D-0

12 Intel® Xeon® Processor 5500 Series
Specification Update, February 2014
AAK90. XXXNoFix
Performance Monitor Interrupts Generated From Uncore Fixed Counters
(394H) May be Ignored
AAK91. XXXNoFix
Processors with SMT May Hang on P-State Transition or ACPI Clock Modulation
Throttling
AAK92. XXXNoFix
Performance Monitor Counter INST_RETIRED.STORES May Count Higher than
Expected
AAK93. XXXNoFix
Sleeping Cores May Not be Woken Up on Logical Cluster Mode Broadcast IPI
Using Destination Field Instead of Shorthand
AAK94. XXXNoFixFaulting Executions of FXRSTOR May Update State Inconsistently
AAK95. XXXNoFix
Failing DIMM ID May be Incorrect in the 2DPC Configuration When Mirroring is
Enabled
AAK96. XXXNoFixISSUEONCE Bit in MC_SCRUB_CONTROL Register Does Not Work Correctly
AAK97. XXXNoFix
Unexpected Intel QPI Link Behavior May Occur When a CRC Error Happens
During L0s
AAK98. XXXNoFix
Performance Monitor Event EPT.EPDPE_MISS May be Counted While EPT is
Disabled
AAK99. XXXNoFix
Intel® QuickPath Interconnect Memory Controller Operating In Lockstep Mode
May Deliver Incorrect Data on Exiting Package C3 or C6 State
AAK100. XXXNoFixPerformance Monitor Counters May Count Incorrectly
AAK101. XXXNoFix
Memory Thermal Throttling May Not Work as Expected in Lockstep Channel
Mode
AAK102. XXXNoFix
Processor Forward Progress Mechanism Interacting With Certain MSR/CSR
Writes May Cause Unpredictable System Behavior
AAK103. XX Fixed
USB 1.1 Isoch Memory Latencies May Increase During Package C3/C6
Transitions
AAK104. XXXNoFixProcessor May Incorrectly Demote Processor C6 State to a C3 State
AAK105. XXXNoFix
Performance Monitor Event Offcore_response_0 (B7H) Does Not Count NT
Stores to Local DRAM Correctly
AAK106. XXXNoFix
EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a
Translation Change
AAK107. XXXNoFix
Persistent Stream of Correctable Memory ECC Errors May Disable the
Scrubbing Engine
AAK108. XXXNoFix
System May Hang if MC_CHANNEL_{0,1,2}_MC_DIMM_INIT_CMD.DO_ZQCL
Commands Are Not Issued in Increasing Populated DDR3 Rank Order
AAK109. XXXNoFixLER and LBR MSRs May Be Incorrectly Updated During a Task Switch
AAK110. XX Fixed
Virtualized WRMSR to the IA32_EXT_XAPIC_TPR MSR Uses Incorrect Value for
TPR Threshold
AAK111. XXXNoFix
Back to Back Uncorrected Machine Check Errors May Overwrite
IA32_MC3_STATUS.MSCOD
AAK112. XXXNoFix
Memory Intensive Workloads with Core C6 Transitions May Cause System
Hang
AAK113. XXXNoFix
Corrected Errors With a Yellow Error Indication May be Overwritten by Other
Corrected Errors
AAK114. XXXNoFix
PSI# Signal May Incorrectly be Left Asserted
AAK115. XXXNoFix
A Patrol Scrub Operation Conflicting with a Memory Self Refresh Request May
Result in a System Hang
AAK116. XXXNoFix
A String Instruction that Re-maps a Page May Encounter an Unexpected Page
Fault
AAK117. XXXNoFix
Lockstep Memory Configurations May Not Operate Correctly With Package C3/
C6 States Enabled
Errata (Sheet 4 of 7)
Number Steppings Status ERRATA
C-0 C-1 D-0

Intel® Xeon® Processor 5500 Series 13
Specification Update, February 2014
AAK118. XXXNoFix
Memory ECC Errors May be Observed When a UC Partial Write is Followed by a
UC Read to the Same Location
AAK119. XXXNoFix
Performance Monitor Events DCACHE_CACHE_LD and DCACHE_CACHE_ST
May Overcount
AAK120. XXXNoFixRapid Core C3/C6 Transition May Cause Unpredictable System Behavior
AAK121. XXXNoFix
Performance Monitor Events INSTR_RETIRED and MEM_INST_RETIRED May
Count Inaccurately
AAK122. XXXNoFix
A Page Fault May Not be Generated When the PS bit is set to “1” in a PML4E or
PDPTE
AAK123. XXXNoFix
Package C3/C6 Transitions When Memory 2x Refresh is Enabled May Result in
a System Hang
AAK124. X X X Plan Fix Intel QPI Link in a DP Configuration May Hang Due to Back-Back CRC Errors
AAK125. X X X Plan Fix tRP Timing Violations May be Observed Near a Self Refresh Entry
AAK126. X X X Plan Fix Concurrent Updates to a Segment Descriptor May be Lost
AAK127. X X X Plan Fix PMIs May be Lost During Core C6 Transitions
AAK128. XXXNoFix
Uncacheable Access to a Monitored Address Range May Prevent Future
Triggering of the Monitor Hardware
AAK129. XXXNoFix
Memory Controller Clock Circuits May Show a Temperature Sensitive
Dependence on Power-On Conditions
AAK130. XXXNoFix
BIST Results May be Additionally Reported After a GETSEC[WAKEUP] or INIT-
SIPI Sequence
AAK131. XXXNoFix
Enabling Demand/Patrol Scrubs Along With WMM May Cause Unpredictable
System Behavior
AAK132. XXXNoFixPending x87 FPU Exceptions (#MF) May be Signaled Earlier Than Expected
AAK133. XXXNoFixVM Exits Due to “NMI-Window Exiting” May Be Delayed by One Instruction
AAK134. X X X Plan Fix VM Exits Due to EPT Violations Do Not Record Information About Pre-IRET NMI
Blocking
AAK135. XXXNoFix
Multiple Performance Monitor Interrupts are Possible on Overflow of
IA32_FIXED_CTR2
AAK136. XXXNoFixLBRs May Not be Initialized During Power-On Reset of the Processor
AAK137. XXXNoFix
Unexpected Interrupts May Occur on C6 Exit If Using APIC Timer to Generate
Interrupts
AAK138. XXXNoFix
BTM or BTS Records May have Incorrect Branch From Information After an
Enhanced Intel SpeedStep® Technology Transition, T-states, C1E, or Adaptive
Thermal Throttling
AAK139. XXXNoFixVMX-Preemption Timer Does Not Count Down at the Rate Specified
AAK140. XXXNoFixVM Exits Due to LIDT/LGDT/SIDT/SGDT Do Not Report Correct Operand Size
AAK141. XXXNoFix
INVLPG Following INVEPT or INVVPID May Fail to Flush All Translations for a
Large Page
AAK142. XXXNoFix
Performance Monitoring Events STORE_BLOCKS.NOT_STA and
STORE_BLOCKS.STA May Not Count Events Correctly
AAK143. XXXNoFixStorage of PEBS Record Delayed Following Execution of MOV SS or STI
AAK144. XXXNoFix
Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some
Transitions
AAK145. XXXNoFixThe PECI Bus May be Tri-stated After System Reset
AAK146. XXXNoFixMSRs May Be Unreliable
AAK147. XXXNoFixAn Exit From the Core C6-state May Result in the Dropping of an Interrupt
Errata (Sheet 5 of 7)
Number Steppings Status ERRATA
C-0 C-1 D-0

14 Intel® Xeon® Processor 5500 Series
Specification Update, February 2014
AAK148. XXXNoFixPMIs During Core C6 Transitions May Cause the System to Hang
AAK149. XXXNoFix
2 MB Page Split Lock Accesses Combined With Complex Internal Events May
Cause Unpredictable System Behavior
AAK150. X X X Plan Fix IA32_MC8_CTL2 MSR is Not Cleared on Processor Warm Reset
AAK151. XXXNoFix
The Combination of a Page-Split Lock Access And Data Accesses That Are Split
Across Cacheline Boundaries May Lead to Processor Livelock
AAK152. XXXNoFix
FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access
Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-
bit Mode
AAK153. XXXNoFixIO_SMI Indication in SMRAM State Save Area May Be Lost
AAK154. XXXNoFix
Performance Monitor Events for Hardware Prefetches Which Miss the L1 Data
Cache May be Over Counted
AAK155. XXXNoFixVM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
AAK156. XXXNoFix
Intel QPI Lane May Be Dropped During Full Frequency Deskew Phase of
Training
AAK157. XXXNoFix
PerfMon Overflow Status Can Not be Cleared After Certain Conditions Have
Occurred
AAK158. XXXNoFix
An Unexpected Page Fault or EPT Violation May Occur After Another Logical
Processor Creates a Valid Translation for a Page
AAK159. XXXNoFixL1 Data Cache Errors May be Logged With Level Set to 1 Instead of 0
AAK160. XXXNoFix
Stack Pushes May Not Occur Properly for Events Delivered Immediately After
VM Entry to 16-Bit Software
AAK161. XXXNoFixPerfMon Event LOAD_HIT_PRE.SW_PREFETCH May Overcount
AAK162. XXXNoFixSuccessive Fixed Counter Overflows May be Discarded
AAK163. XXXNoFix
#GP May be Signaled When Invalid VEX Prefix Precedes Conditional Branch
Instructions
AAK164. XXXNoFix
A Logical Processor May Wake From Shutdown State When Branch-Trace
Messages or Branch-Trace Stores Are Enabled
AAK165. XXXNoFix
Task Switch to a TSS With an Inaccessible LDTR Descriptor May Cause
Unexpected Faults
AAK166. XXXNoFix
Changes to Reserved Bits of Some Non-Architectural MSR's May Cause
Unpredictable System Behavior
AAK167. XXXNoFixVirtual-APIC Page Accesses With 32-Bit PAE Paging May Cause a System Crash
AAK168. XXXNoFix
SMRAM State-Save Area Above the 4 GB Boundary May Cause Unpredictable
System Behavior
AAK169. XXXNoFix
The Corrected Error Count Overflow Bit in IA32_ MC0_STATUS is Not Updated
After a UC Error is Logged
AAK170. XXXNoFixThe Upper 32 Bits of CR3 May be Incorrectly Used With 32-Bit Paging
AAK171. XXXNoFixEPT Violations May Report Bits 11:0 of Guest Linear Address Incorrectly
AAK172. XXXNoFixMCI_ADDR May be Incorrect For Cache Parity Errors
AAK173. XXXNoFix
A Machine Check Occurring During VM Entry May Cause Unpredictable
Behavior
AAK174. XXXNoFix
A Combination of Data Accesses That Are Split Across Cacheline Boundaries
May Lead to a Processor Hang
AAK175. XXXNoFix
Execution of INVVPID Outside 64-Bit Mode Cannot Invalidate Translations For
64-Bit Linear Addresses
AAK176. XXXNoFix
VM Exits Due to "NMI-Window Exiting" May Not Occur Following a VM Entry to
the Shutdown State
Errata (Sheet 6 of 7)
Number Steppings Status ERRATA
C-0 C-1 D-0

Intel® Xeon® Processor 5500 Series 15
Specification Update, February 2014
AAK177. XXXNoFix
All system interrupt sources should be quiesced before hardware disabling
Logical Processor local APIC(s).
AAK178. XXXNoFix
VM Entries That Return From SMM Using VMLAUNCH May Not Update The
Launch State of the VMCS
AAK179. XXXNoFix
VM Entry May Clear Bytes 81H-83H on Virtual-APIC Page When “Use TPR
Shadow” Is 0
AAK180. XXXNoFixA First Level Data Cache Parity Error May Result in Unexpected Behavior
AAK181. XXXNoFix
Executing The GETSEC Instruction While Throttling May Result in a Processor
Hang
Notes:
1. For this stepping of the product BIOS workaround is not available.
Errata (Sheet 7 of 7)
Number Steppings Status ERRATA
C-0 C-1 D-0

16 Intel® Xeon® Processor 5500 Series
Specification Update, February 2014
Specification Changes
Number SPECIFICATION CHANGES
None for this revision of this specification update.
Specification Clarifications
Number SPECIFICATION CLARIFICATIONS
AAK1. Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation
Documentation Changes
Number DOCUMENTATION CHANGES
None for this revision of the specification update.

Intel® Xeon® Processor 5500 Series 17
Specification Update, February 2014
Identification Information
Component Identification via Programming Interface
The Intel® Xeon® Processor 5500 Series stepping can be identified by the following
register contents:
Notes:
1. The Extended Family, bits [27:20] are used in conjunction with the Family Code, specified in bits [11:8],
to indicate whether the processor belongs to the Intel386™, Intel486™, Pentium®, Pentium® Pro,
Pentium® 4, Intel® Core™ processor family or Intel® Core™ i7 family.
2. The Extended Model, bits [19:16] in conjunction with the Model Number, specified in bits [7:4], are
used to identify the model of the processor within the processor’s family.
3. The Processor Type, specified in bits [13:12] indicates whether the processor is an original OEM
processor, an OverDrive processor, or a dual processor (capable of being used in a dual processor
system).
4. The Family Code corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX
register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of
the Device ID register accessible through Boundary Scan.
5. The Model Number corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX
register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the
Device ID register accessible through Boundary Scan.
6. The Stepping ID in bits [3:0] indicates the revision number of that model. See Table 1 for the processor
stepping ID number in the CPUID information.
When EAX is initialized to a value of ‘1’, the CPUID instruction returns the Extended
Family, Extended Model, Processor Type, Family Code, Model Number and Stepping ID
value in the EAX register. Note that the EDX processor signature value after reset is
equivalent to the processor signature output value in the EAX register.
Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX
registers after the CPUID instruction is executed with a 2 in the EAX register.
Reserved Extended
Family1Extended Model2Reserved Processor Type3Family Code4Model Number5Stepping ID6
31:28 27:20 19:16 15:14 13:12 11:8 7:4 3:0
00000000b 0001b 00b 0110 1010b xxxxb

18 Intel® Xeon® Processor 5500 Series
Specification Update, February 2014
Component Marking Information
Intel® Xeon® Processor 5500 Series stepping can be identified by the following
component markings:
Notes:
Figure 1. Processor Top-side Markings (Example)
Table 1. Intel® Xeon® Processor 5500 Series Identification
S-Spec
Number Stepping CPUID
Core Frequency (GHz) /
Intel® QuickPath
Interconnect (GT/s) /
DDR3 (MHz)
Availablebins
of Intel®
Turbo Boost
Technology
Cache
Size
(MB) Notes
SLBF3 D-0 0x000106A5 2.93 / 6.40 / 1333 2/2/3/3 8 3, 4
SLBF4 D-0 0x000106A5 2.80 / 6.40 /1333 2/2/3/3 8 3, 5
SLBF5 D-0 0x000106A5 2.66 / 6.40 /1333 2/2/3/3 8 3, 6
SLBF6 D-0 0x000106A5 2.53 / 5.86 /1066 1/1/1/2 8 3, 7
SLBF7 D-0 0x000106A5 2.40 / 5.86/ 1066 1/1/2/2 8 3, 8
SLBFD D-0 0x000106A5 2.26 / 5.86 / 1066 1/1/2/2 8 3, 9
SLBF8 D-0 0x000106A5 2.13 / 4.80 / 800 n/a 4 3, 10
SLBF9 D-0 0x000106A5 2.00 / 4.80 / 800 n/a 4 3, 11
SLBEZ D-0 0x000106A5 1.86 / 4.80 / 800 n/a 4 3, 12
SLBFA D-0 0x000106A5 2.26 / 5.86 / 1066 1/1/2/2 8 3, 13
SLBFH D-0 0x000106A5 2.13 / 4.80 / 800 n/a 4 3, 14
SLBF2 D-0 0x000106A5 3.20 / 6.40 / 1333 1/1/1/2 8 3, 15
SLBGK D-0 0x000106A5 2.00 / 5.86 / 1066 na/na/2/3 8 3, 20
SLBFW D-0 0x000106A5 2.13 / 5.86 / 1066 1/1/2/2 8 3, 19
SLBGE D-0 0x000106A5 3.33 / 6.40 / 1333 1/1/1/2 8 3, 21
SLBKC D-0 0x000106A5 2.26 / 4.80 / 800 n/a 8 3, 22
SLBGF D-0 0x000106A5 2.40 / 5.86 / 1066 1/1/2/2 8 3, 23
SLBKD D-0 0x000106A5 2.00 / 4.80 / 800 n/a 4 3, 24

Intel® Xeon® Processor 5500 Series 19
Specification Update, February 2014
1. Although these units are factory-configured for 1333 MHz integrated memory controller frequency, Intel
does not support operation beyond 1066 MHz; however, this processor has additional support to
override the integrated memory controller frequency.
2. Column indicates the number of frequency bins (133.33 MHz) of Intel® Turbo Boost Technology that are
available for 4, 3, 2, or 1 cores active respectively.
3. CPUID is 0000106Ash, where ‘s’ is the stepping number.
4. This is an Intel® Xeon Processor X5570 with 95W TDP (Thermal Design Power).
5. This is an Intel® Xeon Processor X5560 with 95W TDP (Thermal Design Power).
6. This is an Intel® Xeon Processor X5550 with 95W TDP (Thermal Design Power).
7. This is an Intel® Xeon Processor E5540 with 80W TDP (Thermal Design Power).
8. This is an Intel® Xeon Processor E5530 with 80W TDP (Thermal Design Power).
9. This is an Intel® Xeon Processor E5520 with 80W TDP (Thermal Design Power).
10. This is an Intel® Xeon Processor E5506 with 80W TDP (Thermal Design Power).
11. This is an Intel® Xeon Processor E5504 with 80W TDP (Thermal Design Power).
12. This is an Intel® Xeon Processor E5502 with 80W TDP (Thermal Design Power).
13. This is an Intel® Xeon Processor L5520 with 60W TDP (Thermal Design Power).
14. This is an Intel® Xeon Processor L5506 with 60W TDP (Thermal Design Power).
15. This is an Intel® Xeon Processor W5580 with 130W TDP (Thermal Design Power).
16. Column indicates the number of frequency bins (133.33 MHz) of Intel® Turbo Boost Technology that are
available for 4, 3, 2, or 1 cores active respectively.
17. This is an Intel® Xeon Processor 5500 Series with 60W TDP and elevated case temperature spec.
18. This is an Intel® Xeon Processor 5500 Series with 38W TDP and elevated case temperature spec.
19. This is an Intel® Xeon Processor L5518 with 60W TDP and elevated case temperature spec.
20. This is an Intel® Xeon Processor L5508 with 38W TDP and elevated case temperature spec.
21. This is an Intel® Xeon Processor W5590 with 130W TDP (Thermal Design Power).
22. This is an Intel® Xeon Processor E5507 with 80W TDP (Thermal Design Power).
23. This is an Intel® Xeon Processor L5530 with 60W TDP (Thermal Design Power).
24. This is an Intel® Xeon Processor E5503 with 80W TDP (Thermal Design Power).
Mixing Processor Within DP Platforms
Intel supports dual processor (DP) configurations consisting of processors:
1. From the same power optimization segment
2. That support the same maximum Intel® QuickPath Interconnect (Intel® QPI) and
DDR3 memory speeds.
3. That share symmetry across physical packages with respect to the number of
logical processors per package, number of cores per package, number of Intel QPI
Interfaces, and cache topology.
4. That have identical Extended Family, Extended Model, Processor Type, Family Code
and Model Number as indicated by the function 1 of the CPUID instruction.
Note: Processors must operate with the same Intel QPI, DDR3 memory and core frequency.
While Intel does nothing to prevent processors from operating together, some
combinations may not be supported due to limited validation, which may result in
uncharacterized errata. Coupling this fact with the large number of Intel Xeon
processor 5500 series attributes, the following population rules and stepping matrix
have been developed to clearly define supported configurations.
1. Processors must be of the same power-optimization segment. This insures
processors include the same maximum Intel QPI and DDR3 operating speeds and
cache sizes.
2. Processors must operate at the same core frequency. Note: Processors within the
same power-optimization segment supporting different maximum core frequencies
(for example, a 2.93 GHz / 95 W and 2.66 GHz / 95W) can be operated within a
system. However, both must operated at the highest frequency rating commonly
supported. Mixing components operating at different internal clock frequencies is
not supported and will not be validated by Intel.
3. Processors must share symmetry across physical packages with respect to the
number of logical processors per package, number of Intel QPI Interfaces, and
cache topology.

20 Intel® Xeon® Processor 5500 Series
Specification Update, February 2014
4. Mixing dissimilar steppings is only supported with processors that have identical
Extended Family, Extended Model, Processor type, Family Code and Model Number
as indicated by the function 1 of the CPUID instruction. Mixing processors of
different steppings but the same model (as per CPUID instruction) is supported.
Details regarding the CPUID instruction are provided in the AP-487, Intel®
Processor Identification and the CPUID Instruction application note and Intel® 64
and IA-32 Architectures Software Developer’s Manual, Volume 2A.
5. After AND’ing the feature flag and extended feature flag from the installed
processors, any processor whose set of feature flags exactly matches the AND’ed
feature flags can be selected by the BIOS as the BSP. If no processor exactly
matches the AND’ed feature flag values, then the processors with the numerically
lower CPUID should be selected as the BSP.
6. Intel requires that the processor microcode update be loaded on each processor
operating within the system. Any processor that does not have the proper
microcode update loaded is considered by Intel to be operating out of specification.
7. The workarounds identified in this, and subsequent specification updates, must
properly applied to each processor in the system. Certain errata are specific to the
multiprocessor environment. Errata for all processor steppings will affect system
performance if not properly worked around.
8. Customers are fully responsible for the validation of their system configurations.
25.
26.