Intel P4000 - 11-2010 User manual

Document Number: 324456-005
Intel® Celeron® Mobile Processor
P4000 and U3000 Series
Specification Update
November 2010

2Specification Update
Legal Lines and Disclaimers
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life sustaining, critical control or safety systems, or in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them.
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family,
not across different processor families. See http://www.intel.com/products/processor_number for details.
The processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.Contact your local Intel sales office or your distributor to
obtain the latest specifications and before placing your product order.
Intel, Intel Core, Centrino, Celeron, Pentium, Intel Xeon, Intel SpeedStep and the Intel logo are trademarks or registered
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*Other names and brands may be claimed as the property of others.
Copyright © 2010, Intel Corporation. All Rights Reserved.

Specification Update 3
Contents
Revision History ........................................................................................................4
Preface......................................................................................................................5
Summary Tables of Changes......................................................................................7
Identification Information.......................................................................................14
Errata......................................................................................................................17
Specification Changes..............................................................................................43
Specification Clarifications ......................................................................................43
Documentation Changes..........................................................................................44
§

Revision History
4 Specification Update
Revision History
Revision Version Description Date
-001 -001 Initial Release March 2010
-002 -001
• Updated K-0 Stepping Microcode Update
• Updated C-2 Stepping Microcode Update
• Fixed AAZ69
• Added Errata AAZ10S-11S
July 2010
-003 -001 • Added Errata AAZ96-AAZ99
• Added Revision/Version to clarify if there are ever multiple releases
within a month August 2010
-004 -001 • Added new processor sku P4600 October 2010
-005 -001 • Added Errata AAZ100-103
• Updated Errata AAZ32 and AAZ76 November 2010

Specification Update 5
Preface
Preface
This document is an update to the specifications contained in the Affected Documents
table below. This document is a compilation of device and documentation errata,
specification clarifications and changes. It is intended for hardware system
manufacturers and software developers of applications, operating systems, or tools.
Information types defined in Nomenclature are consolidated into the specification
update and are no longer published in other documents.
This document may also contain information that was not previously published.
Affected Documents
Related Documents
Notes:
1. Documentation changes for Intel® 64 and IA-32 Architecture Software Developer's Manual volumes 1,
2A, 2B, 3A, and 3B, and bug fixes are posted in the Intel® 64 and IA-32 Architecture Software
Developer's Manual Documentation Changes.
Document Title Document Number/
Location
Intel® Celeron® Mobile Processor P4000 and U3000 Series
Datasheet 324471-001
Document Title Document Number/
Location
AP-485, Intel® Processor Identification and the CPUID
Instruction http://www.intel.com/ design/processor/applnots/
241618.htm
Intel®64 and IA-32 Architectures Software Developer’s Manual,
Volume 1: Basic Architecture
Intel®64 and IA-32 Architectures Software Developer’s Manual,
Volume 2A: Instruction Set Reference Manual A-M
Intel®64 and IA-32 Architectures Software Developer’s Manual,
Volume 2B: Instruction Set Reference Manual N-Z
Intel®64 and IA-32 Architectures Software Developer’s Manual,
Volume 3A: System Programming Guide
Intel®64 and IA-32 Architectures Software Developer’s Manual,
Volume 3B: System Programming Guide
Intel®64 and IA-32 Intel Architecture Optimization Reference
Manual
Intel®64 and IA-32 Architectures Software Developer’s Manual
Documentation Changes (see note 1)
http://www.intel.com/
products/processor/manuals/
index.htm
ACPI Specifications www.acpi.info

Preface
6 Specification Update
Nomenclature
Errata are design defects or errors. These may cause the Intel® Celeron® P4000 and
U3000 Mobile Processor Series behavior to deviate from published specifications.
Hardware and software designed to be used with any given stepping must assume that
all errata documented for that stepping are present on all devices.
S-Spec Number is a five-digit code used to identify products. Products are
differentiated by their unique characteristics,e.g., core speed, L3 cache size, package
type, etc. as described in the processor identification information table. Read all notes
associated with each S-Spec number.
Specification Changes are modifications to the current published specifications.
These changes will be incorporated in any new release of the specification.
Specification Clarifications describe a specification in greater detail or further
highlight a specification’s impact to a complex design situation. These clarifications will
be incorporated in any new release of the specification.
Documentation Changes include typos, errors, or omissions from the current
published specifications. These will be incorporated in any new release of the
specification.
Note: Errata remain in the specification update throughout the product’s lifecycle, or until a
particular stepping is no longer commercially-available. Under these circumstances,
errata removed from the specification update are archived and available upon request.
Specification changes, specification clarifications and documentation changes are
removed from the specification update when the appropriate changes are made to the
appropriate product specification or user documentation (datasheets, manuals, etc.).
§ §

Specification Update 7
Summary Tables of Changes
Summary Tables of Changes
The following tables indicate the errata, specification changes, specification
clarifications, or documentation changes which apply to the processor. Intel may fix
some of the errata in a future stepping of the component, and account for the other
outstanding issues through documentation or specification changes as noted. These
tables uses the following notations:
Codes Used in Summary Tables
Stepping
X: Errata exists in the stepping indicated. Specification Change or
Clarification that applies to this stepping.
(No mark)
or (Blank box): This erratum is fixed in listed stepping or specification change
does not apply to listed stepping.
Page
(Page): Page location of item in this document.
Status
Doc: Document change or update will be implemented.
Plan Fix: This erratum may be fixed in a future stepping of the product.
Fixed: This erratum has been previously fixed.
No Fix: There are no plans to fix this erratum.
Row
Change bar to left of table row indicates this erratum is either new or modified from the
previous version of the document.
Each Specification Update item is prefixed with a capital letter to distinguish the
product. The key below details the letters that are used in Intel’s microprocessor
Specification Updates:

Summary Tables of Changes
8 Specification Update
AAZ
Errata (Sheet 1 of 5)
Number Steppings Status ERRATA
C-2 K-0
AAZ1 X X No Fix The Processor May Report a #TS Instead of a #GP Fault
AAZ2 X X No Fix
REP MOVS/STOS Executing with Fast Strings Enabled and
Crossing Page Boundaries with Inconsistent Memory Types May
Use an Incorrect Data Size or Lead to Memory-Ordering
Violations
AAZ3 X X No Fix Code Segment Limit/Canonical Faults on RSM May Be Serviced before Higher Priority Interrupts/Exceptions and May Push the
Wrong Address onto the Stack
AAZ4 X X No Fix Performance Monitor SSE Retired Instructions May Return
Incorrect Values
AAZ5 X X No Fix Premature Execution of a Load Operation Prior to Exception
Handler Invocation
AAZ6 X X No Fix MOV To/From Debug Registers Causes Debug Exception
AAZ7 X X No Fix Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR
Image Leads to Partial Memory Update
AAZ8 X X No Fix Values for LBR/BTS/BTM Will Be Incorrect after an Exit from
SMM
AAZ9 X X No Fix Single Step Interrupts with Floating Point Exception Pending
May Be Mishandled
AAZ10 X X No Fix Fault on ENTER Instruction May Result in Unexpected Values on
Stack Frame
AAZ11 X X No Fix IRET under Certain Conditions May Cause an Unexpected
Alignment Check Exception
AAZ12 X X No Fix General Protection Fault (#GP) for Instructions Greater than 15
Bytes May Be Preempted
AAZ13 X X No Fix General Protection (#GP) Fault May Not Be Signaled on Data
Segment Limit Violation above 4-G Limit
AAZ14 X X No Fix LBR, BTS, BTM May Report a Wrong Address When an
Exception/Interrupt Occurs in 64-bit Mode
AAZ15 X X No Fix MONITOR or CLFLUSH on the Local XAPIC's Address Space
Results in Hang
AAZ16 X X No Fix Corruption of CS Segment Register during RSM While
Transitioning from Real Mode to Protected Mode
AAZ17 X X No Fix Performance Monitoring Events for Read Miss to Level 3 Cache
Fill Occupancy Counter May Be Incorrect
AAZ18 X X No Fix A VM Exit on MWAIT May Incorrectly Report the Monitoring
Hardware as Armed
AAZ19 X X No Fix Performance Monitor Event SEGMENT_REG_LOADS Counts
Inaccurately
AAZ20 X X No Fix #GP on Segment Selector Descriptor That Straddles Canonical
Boundary May Not Provide Correct Exception Error Code

Specification Update 9
Summary Tables of Changes
AAZ21 X X No Fix Improper Parity Error Signaled in the IQ Following Reset When a
Code Breakpoint Is Set on a #GP Instruction
AAZ22 XXNoFix
An Enabled Debug Breakpoint or Single Step Trap May Be Taken
after MOV SS/POP SS Instruction If It Is Followed by an
Instruction That Signals a Floating Point Exception
AAZ23 X X No Fix IA32_MPERF Counter Stops Counting during On-Demand TM1
AAZ24 X X No Fix The Memory Controller tTHROT_OPREF Timings May Be Violated
during Self-Refresh Entry
AAZ25 X X No Fix Synchronous Reset of IA32_APERF/IA32_MPERF Counters on
Overflow Does Not Work
AAZ26 X X No Fix Disabling Thermal Monitor While Processor is Hot, Then Re-
enabling, May Result in Stuck Core Operating Ratio
AAZ27 X X No Fix Writing the Local Vector Table (LVT) When an Interrupt is
Pending May Cause an Unexpected Interrupt
AAZ28 X X No Fix xAPIC Timer May Decrement Too Quickly Following an
Automatic Reload While in Periodic Mode
AAZ29 X X No Fix Changing the Memory Type for an In-Use Page Translation May
Lead to Memory-Ordering Violations
AAZ30 X X No Fix Infinite Stream of Interrupts May Occur If an ExtINT Delivery
Mode Interrupt is Received While All Cores in C6
AAZ31 X X No Fix Two xAPIC Timer Event Interrupts May Unexpectedly Occur
AAZ32 X X No Fix EOI Transaction May Not Be Sent If Software Enters Core C6
during an Interrupt Service Routine
AAZ33 X X No Fix FREEZE_WHILE_SMM Does Not Prevent Event from Pending
PEBS during SMM
AAZ34 X X No Fix APIC Error “Received Illegal Vector” May Be Lost
AAZ35 X X No Fix DR6 May Contain Incorrect Information When the First
Instruction after a MOV SS,r/m or POP SS Is a Store
AAZ36 X X No Fix An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May
Also Result in a System Hang
AAZ37 X X No Fix IA32_PERF_GLOBAL_CTRL MSR May Be Incorrectly Initialized
AAZ38 X X No Fix Performance Monitor Counter INST_RETIRED.STORES May
Count Higher Than Expected
AAZ39 X X No Fix Sleeping Cores May Not Be Woken Up on Logical Cluster Mode
Broadcast IPI Using Destination Field Instead of Shorthand
AAZ40 X X No Fix Faulting Executions of FXRSTOR May Update State
Inconsistently
AAZ41 X X No Fix Performance Monitor Event EPT.EPDPE_MISS May Be Counted
While EPT Is Disable
AAZ42 X X No Fix Memory Aliasing of Code Pages May Cause Unpredictable
System Behavior
AAZ43 X X No Fix Performance Monitor Counters May Count Incorrectly
Errata (Sheet 2 of 5)
Number Steppings Status ERRATA
C-2 K-0

Summary Tables of Changes
10 Specification Update
AAZ44 X X No Fix Performance Monitor Event Offcore_response_0 (B7H) Does Not
Count NT Stores to Local DRAM Correctly
AAZ45 X X No Fix EFLAGS Discrepancy on Page Faults and on EPT-Induced VM
Exits after a Translation Change
AAZ46 X X No Fix Back-to-Back Uncorrected Machine Check Errors May Overwrite
IA32_MC3_STATUS.MSCOD
AAZ47 X X No Fix Corrected Errors with a Yellow Error Indication May Be
Overwritten by Other Corrected Errors
AAZ48 X X No Fix Performance Monitor Events DCACHE_CACHE_LD and
DCACHE_CACHE_ST May Overcount
AAZ49 X X No Fix Performance Monitor Events INSTR_RETIRED and
MEM_INST_RETIRED May Count Inaccurately
AAZ50 X X No Fix A Page Fault May Not Be Generated When the PS Bit Is Set to
"1" in a PML4E or PDPTE
AAZ51 X X No Fix BIST Results May Be Additionally Reported after a
GETSEC[WAKEUP] or INIT-SIPI Sequence
AAZ52 X X No Fix Pending x87 FPU Exceptions (#MF) May Be Signaled Earlier
Than Expected
AAZ53 X X No Fix VM Exits Due to "NMI-Window Exiting" May Be Delayed by One
Instruction
AAZ54 X X No Fix VM Exits Due to EPT Violations Do Not Record Information about
Pre-IRET NMI Blocking.
AAZ55 X X No Fix Multiple Performance Monitor Interrupts are Possible on
Overflow of IA32_FIXED_CTR2
AAZ56 X X No Fix LBRs May Not be Initialized During Power-On Reset of the
Processor
AAZ57 X X No Fix LBR, BTM or BTS Records May Have Incorrect Branch From Information After an Enhanced Intel SpeedStep® Technology
Transition, T-states, C1E, or Adaptive Thermal Throttling
AAZ58 X X No Fix VMX-Preemption Timer Does Not Count Down at the Rate
Specified
AAZ59 X X No Fix Multiple Performance Monitor Interrupts Are Possible on
Overflow of Fixed Counter 0
AAZ60 X X No Fix VM Exits Due to LIDT/LGDT/SIDT/SGDT Do Not Report Correct
Operand Size
AAZ61 X X No Fix DPRSLPVR Signal May Be Incorrectly Asserted on Transition
between Low Power C-states
AAZ62 X X No Fix Performance Monitoring Events STORE_BLOCKS.NOT_STA and
STORE_BLOCKS.STA May Not Count Events Correctly
AAZ63 X X No Fix Storage of PEBS Record Delayed Following Execution of MOV SS
or STI
AAZ64 X X No Fix Performance Monitoring Event FP_MMX_TRANS_TO_MMX May
Not Count Some Transitions
Errata (Sheet 3 of 5)
Number Steppings Status ERRATA
C-2 K-0