Intel i960 Jx User manual

Release Date: December, 1997
Order Number: 272483-002
i960®Jx Microprocessor
Developer’s Manual

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otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
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Copyright © Intel Corporation, 1997
*Third-party brands and names are the property of their respective owners.
ii May, 1998 272483-002

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i960®Jx Microprocessor
Developer’s Manual
CHAPTER 1
INTRODUCTION
1.1 Product Features........................................................................................................... 1-4
1.1.1 Instruction Cache .................................................................................................... 1-4
1.1.2 Data Cache ............................................................................................................. 1-4
1.1.3 On-chip (Internal) Data RAM ................................................................................... 1-4
1.1.4 Local Register Cache .............................................................................................. 1-5
1.1.5 Interrupt Controller .................................................................................................. 1-5
1.1.6 Timer Support .......................................................................................................... 1-6
1.1.7 Memory-Mapped Control Registers (MMR) ............................................................. 1-6
1.1.8 External Bus ............................................................................................................ 1-6
1.1.9 Complete Fault Handling and Debug Capabilities ................................................... 1-7
1.2 ABOUT THIS MANUAL................................................................................................. 1-7
1.3 NOTATION AND TERMINOLOGY................................................................................ 1-8
1.3.1 Reserved and Preserved ......................................................................................... 1-8
1.3.2 Specifying Bit and Signal Values ............................................................................. 1-9
1.3.3 Representing Numbers ........................................................................................... 1-9
1.3.4 Register Names ....................................................................................................... 1-9
1.4 Related Documents..................................................................................................... 1-10
CHAPTER 2
DATA TYPES AND MEMORY ADDRESSING MODES
2.1 DATA TYPES................................................................................................................ 2-1
2.1.1 Integers ................................................................................................................... 2-2
2.1.2 Ordinals ................................................................................................................... 2-2
2.1.3 Bits and Bit Fields .................................................................................................... 2-3
2.1.4 Triple- and Quad-Words .......................................................................................... 2-3
2.1.5 Register Data Alignment ......................................................................................... 2-3
2.1.6 Literals ..................................................................................................................... 2-4
2.2 BIT AND BYTE ORDERING IN MEMORY.................................................................... 2-4
2.2.1 Bit Ordering ............................................................................................................. 2-4
2.2.2 Byte Ordering .......................................................................................................... 2-4
2.3 MEMORY ADDRESSING MODES............................................................................... 2-6
2.3.1 Absolute .................................................................................................................. 2-7
2.3.2 Register Indirect ...................................................................................................... 2-7
2.3.3 Index with Displacement ......................................................................................... 2-8
2.3.4 IP with Displacement ............................................................................................... 2-8
2.3.5 Addressing Mode Examples .................................................................................... 2-8

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CHAPTER 3
PROGRAMMING ENVIRONMENT
3.1 OVERVIEW................................................................................................................... 3-1
3.2 REGISTERS AND LITERALS AS INSTRUCTION OPERANDS................................... 3-1
3.2.1 Global Registers ...................................................................................................... 3-2
3.2.2 Local Registers ........................................................................................................ 3-3
3.2.3 Register Scoreboarding ........................................................................................... 3-4
3.2.4 Literals ..................................................................................................................... 3-4
3.2.5 Register and Literal Addressing and Alignment ....................................................... 3-4
3.3 MEMORY-MAPPED CONTROL REGISTERS.............................................................. 3-6
3.3.1 Memory-Mapped Registers (MMR) ......................................................................... 3-6
3.3.1.1 Restrictions on Instructions that Access Memory-Mapped Registers .............. 3-6
3.3.1.2 Access Faults ................................................................................................... 3-7
3.4 ARCHITECTURALLY DEFINED DATA STRUCTURES............................................. 3-11
3.5 MEMORY ADDRESS SPACE..................................................................................... 3-13
3.5.1 Memory Requirements .......................................................................................... 3-14
3.5.2 Data and Instruction Alignment in the Address Space .......................................... 3-15
3.5.3 Byte, Word and Bit Addressing .............................................................................. 3-15
3.5.4 Internal Data RAM ................................................................................................. 3-16
3.5.5 Instruction Cache ................................................................................................... 3-16
3.5.6 Data Cache ............................................................................................................ 3-17
3.6 LOCAL REGISTER CACHE........................................................................................ 3-17
3.7 PROCESSOR-STATE REGISTERS........................................................................... 3-17
3.7.1 Instruction Pointer (IP) Register ............................................................................ 3-17
3.7.2 Arithmetic Controls (AC) Register .......................................................................... 3-18
3.7.2.1 Initializing and Modifying the AC Register ...................................................... 3-18
3.7.2.2 Condition Code (AC.cc) .................................................................................. 3-19
3.7.3 Process Controls (PC) Register ............................................................................. 3-21
3.7.3.1 Initializing and Modifying the PC Register ...................................................... 3-22
3.7.4 Trace Controls (TC) Register ................................................................................. 3-23
3.8 USER-SUPERVISOR PROTECTION MODEL ........................................................... 3-23
3.8.1 Supervisor Mode Resources ................................................................................. 3-23
3.8.2 Using the User-Supervisor Protection Model ......................................................... 3-24
CHAPTER 4
CACHE AND ON-CHIP DATA RAM
4.1 INTERNAL DATA RAM................................................................................................. 4-1
4.2 LOCAL REGISTER CACHE.......................................................................................... 4-2
4.3 BIG ENDIAN ACCESSES TO INTERNAL RAM AND DATA CACHE........................... 4-4
4.4 INSTRUCTION CACHE ................................................................................................ 4-4
4.4.1 Enabling and Disabling the Instruction Cache ......................................................... 4-4
4.4.2 Operation While the Instruction Cache Is Disabled ................................................. 4-5
4.4.3 Loading and Locking Instructions in the Instruction Cache ..................................... 4-5

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4.4.4 Instruction Cache Visibility ...................................................................................... 4-5
4.4.5 Instruction Cache Coherency .................................................................................. 4-5
4.5 DATA CACHE............................................................................................................... 4-6
4.5.1 Enabling and Disabling the Data Cache .................................................................. 4-6
4.5.2 Multi-Word Data Accesses that Partially Hit the Data Cache .................................. 4-7
4.5.3 Data Cache Fill Policy ............................................................................................. 4-8
4.5.4 Data Cache Write Policy ......................................................................................... 4-8
4.5.5 Data Cache Coherency and Non-Cacheable Accesses .......................................... 4-9
4.5.6 External I/O and Bus Masters and Cache Coherency ........................................... 4-10
4.5.7 Data Cache Visibility ............................................................................................. 4-10
CHAPTER 5
INSTRUCTION SET OVERVIEW
5.1 INSTRUCTION FORMATS........................................................................................... 5-1
5.1.1 Assembly Language Format ................................................................................... 5-1
5.1.2 Instruction Encoding Formats .................................................................................. 5-2
5.1.3 Instruction Operands ............................................................................................... 5-3
5.2 INSTRUCTION GROUPS............................................................................................. 5-4
5.2.1 Data Movement ....................................................................................................... 5-5
5.2.1.1 Load and Store Instructions ............................................................................. 5-5
5.2.1.2 Move ................................................................................................................ 5-6
5.2.1.3 Load Address ................................................................................................... 5-6
5.2.2 Select Conditional ................................................................................................... 5-6
5.2.3 Arithmetic ................................................................................................................ 5-7
5.2.3.1 Add, Subtract, Multiply, Divide, Conditional Add, Conditional Subtract ............ 5-8
5.2.3.2 Remainder and Modulo .................................................................................... 5-8
5.2.3.3 Shift, Rotate and Extended Shift ...................................................................... 5-9
5.2.3.4 Extended Arithmetic ....................................................................................... 5-10
5.2.4 Logical ................................................................................................................... 5-10
5.2.5 Bit, Bit Field and Byte Operations ......................................................................... 5-11
5.2.5.1 Bit Operations ................................................................................................ 5-11
5.2.5.2 Bit Field Operations ........................................................................................ 5-11
5.2.5.3 Byte Operations ............................................................................................. 5-11
5.2.6 Comparison ........................................................................................................... 5-12
5.2.6.1 Compare and Conditional Compare ............................................................... 5-12
5.2.6.2 Compare and Increment or Decrement .......................................................... 5-13
5.2.6.3 Test Condition Codes ..................................................................................... 5-13
5.2.7 Branch ................................................................................................................... 5-14
5.2.7.1 Unconditional Branch ..................................................................................... 5-14
5.2.7.2 Conditional Branch ......................................................................................... 5-15
5.2.7.3 Compare and Branch ..................................................................................... 5-15
5.2.8 Call/Return ............................................................................................................ 5-16
5.2.9 Faults ..................................................................................................................... 5-17
5.2.10 Debug .................................................................................................................... 5-18
5.2.11 Atomic Instructions ................................................................................................ 5-18

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5.2.12 Processor Management ........................................................................................ 5-19
5.3 PERFORMANCE OPTIMIZATION.............................................................................. 5-20
5.3.1 Instruction Optimizations ....................................................................................... 5-20
5.3.1.1 Load / Store Execution Model ........................................................................ 5-20
5.3.1.2 Compare Operations ...................................................................................... 5-20
5.3.1.3 Microcoded Instructions ................................................................................. 5-21
5.3.1.4 Multiply-Divide Unit Instructions ..................................................................... 5-21
5.3.1.5 Multi-Cycle Register Operations ..................................................................... 5-21
5.3.1.6 Simple Control Transfer ................................................................................. 5-22
5.3.1.7 Memory Instructions ....................................................................................... 5-22
5.3.1.8 Unaligned Memory Accesses ......................................................................... 5-23
5.3.2 Miscellaneous Optimizations ................................................................................. 5-23
5.3.2.1 Masking of Integer Overflow ........................................................................... 5-23
5.3.2.2 Avoid Using PFP, SP, R3 As Destinations for MDU Instructions ................... 5-23
5.3.2.3 Use Global Registers (g0 - g14) As Destinations for MDU Instructions ......... 5-23
5.3.2.4 Execute in Imprecise Fault Mode ................................................................... 5-24
CHAPTER 6
INSTRUCTION SET REFERENCE
6.1 NOTATION.................................................................................................................... 6-1
6.1.1 Alphabetic Reference .............................................................................................. 6-2
6.1.2 Mnemonic ................................................................................................................ 6-2
6.1.3 Format ..................................................................................................................... 6-2
6.1.4 Description ............................................................................................................... 6-3
6.1.5 Action ....................................................................................................................... 6-3
6.1.6 Faults ....................................................................................................................... 6-5
6.1.7 Example ................................................................................................................... 6-5
6.1.8 Opcode and Instruction Format ............................................................................... 6-6
6.1.9 See Also .................................................................................................................. 6-6
6.1.10 Side Effects ............................................................................................................. 6-6
6.1.11 Notes ....................................................................................................................... 6-6
6.2 INSTRUCTIONS............................................................................................................ 6-6
6.2.1 ADD<cc> ................................................................................................................. 6-7
6.2.2 addc ....................................................................................................................... 6-10
6.2.3 addi, addo .............................................................................................................. 6-11
6.2.4 alterbit .................................................................................................................... 6-12
6.2.5 and, andnot ............................................................................................................ 6-13
6.2.6 atadd ...................................................................................................................... 6-14
6.2.7 atmod ..................................................................................................................... 6-15
6.2.8 b, bx ....................................................................................................................... 6-16
6.2.9 bal, balx ................................................................................................................. 6-17
6.2.10 bbc, bbs ................................................................................................................. 6-19
6.2.11 BRANCH<cc> ........................................................................................................ 6-21
6.2.12 bswap .................................................................................................................... 6-23
6.2.13 call ......................................................................................................................... 6-24

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6.2.14 calls ....................................................................................................................... 6-25
6.2.15 callx ....................................................................................................................... 6-27
6.2.16 chkbit ..................................................................................................................... 6-29
6.2.17 clrbit ....................................................................................................................... 6-30
6.2.18 cmpdeci, cmpdeco ................................................................................................ 6-31
6.2.19 cmpinci, cmpinco ................................................................................................... 6-32
6.2.20 COMPARE ............................................................................................................ 6-33
6.2.21 COMPARE AND BRANCH<cc> ............................................................................ 6-35
6.2.22 concmpi, concmpo ................................................................................................ 6-38
6.2.23 dcctl ....................................................................................................................... 6-40
6.2.24 divi, divo ................................................................................................................ 6-47
6.2.25 ediv ........................................................................................................................ 6-48
6.2.26 emul ....................................................................................................................... 6-49
6.2.27 eshro ..................................................................................................................... 6-50
6.2.28 extract .................................................................................................................... 6-51
6.2.29 FAULT<cc> ........................................................................................................... 6-52
6.2.30 flushreg .................................................................................................................. 6-54
6.2.31 fmark ..................................................................................................................... 6-55
6.2.32 halt ......................................................................................................................... 6-56
6.2.33 icctl ........................................................................................................................ 6-58
6.2.34 intctl ....................................................................................................................... 6-66
6.2.35 intdis ...................................................................................................................... 6-68
6.2.36 inten ....................................................................................................................... 6-69
6.2.37 LOAD ..................................................................................................................... 6-70
6.2.38 lda .......................................................................................................................... 6-73
6.2.39 mark ...................................................................................................................... 6-74
6.2.40 modac .................................................................................................................... 6-75
6.2.41 modi ....................................................................................................................... 6-76
6.2.42 modify .................................................................................................................... 6-77
6.2.43 modpc .................................................................................................................... 6-78
6.2.44 modtc ..................................................................................................................... 6-80
6.2.45 MOVE .................................................................................................................... 6-81
6.2.46 muli, mulo .............................................................................................................. 6-84
6.2.47 nand ...................................................................................................................... 6-85
6.2.48 nor ......................................................................................................................... 6-86
6.2.49 not, notand ............................................................................................................ 6-87
6.2.50 notbit ...................................................................................................................... 6-88
6.2.51 notor ...................................................................................................................... 6-89
6.2.52 or, ornot ................................................................................................................. 6-90
6.2.53 remi, remo ............................................................................................................. 6-91
6.2.54 ret .......................................................................................................................... 6-92
6.2.55 rotate ..................................................................................................................... 6-94
6.2.56 scanbit ................................................................................................................... 6-95
6.2.57 scanbyte ................................................................................................................ 6-96

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6.2.58 SEL<cc> ................................................................................................................ 6-97
6.2.59 setbit ...................................................................................................................... 6-99
6.2.60 SHIFT .................................................................................................................. 6-100
6.2.61 spanbit ................................................................................................................. 6-103
6.2.62 STORE ................................................................................................................ 6-104
6.2.63 subc ..................................................................................................................... 6-108
6.2.64 SUB<cc> ............................................................................................................. 6-109
6.2.65 subi, subo ............................................................................................................ 6-112
6.2.66 syncf .................................................................................................................... 6-113
6.2.67 sysctl .................................................................................................................... 6-114
6.2.68 TEST<cc> ............................................................................................................ 6-118
6.2.69 xnor, xor ............................................................................................................... 6-120
CHAPTER 7
PROCEDURE CALLS
7.1 CALL AND RETURN MECHANISM.............................................................................. 7-2
7.1.1 Local Registers and the Procedure Stack ............................................................... 7-2
7.1.2 Local Register and Stack Management ................................................................... 7-4
7.1.2.1 Frame Pointer ................................................................................................... 7-4
7.1.2.2 Stack Pointer .................................................................................................... 7-4
7.1.2.3 Considerations When Pushing Data onto the Stack ........................................ 7-4
7.1.2.4 Considerations When Popping Data off the Stack ........................................... 7-5
7.1.2.5 Previous Frame Pointer .................................................................................... 7-5
7.1.2.6 Return Type Field ............................................................................................. 7-5
7.1.2.7 Return Instruction Pointer ................................................................................. 7-5
7.1.3 Call and Return Action ............................................................................................. 7-5
7.1.3.1 Call Operation .................................................................................................. 7-6
7.1.3.2 Return Operation .............................................................................................. 7-7
7.1.4 Caching Local Register Sets ................................................................................... 7-7
7.1.4.1 Reserving Local Register Sets for High Priority Interrupts ............................... 7-8
7.1.5 Mapping Local Registers to the Procedure Stack .................................................. 7-11
7.2 MODIFYING THE PFP REGISTER............................................................................. 7-11
7.3 PARAMETER PASSING............................................................................................. 7-12
7.4 LOCAL CALLS ............................................................................................................ 7-14
7.5 SYSTEM CALLS ......................................................................................................... 7-15
7.5.1 System Procedure Table ....................................................................................... 7-15
7.5.1.1 Procedure Entries ........................................................................................... 7-17
7.5.1.2 Supervisor Stack Pointer ................................................................................ 7-17
7.5.1.3 Trace Control Bit ............................................................................................ 7-17
7.5.2 System Call to a Local Procedure ......................................................................... 7-18
7.5.3 System Call to a Supervisor Procedure ................................................................. 7-18
7.6 USER AND SUPERVISOR STACKS.......................................................................... 7-19
7.7 INTERRUPT AND FAULT CALLS............................................................................... 7-19
7.8 RETURNS................................................................................................................... 7-20

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7.9 BRANCH-AND-LINK................................................................................................... 7-21
CHAPTER 8
FAULTS
8.1 FAULT HANDLING OVERVIEW................................................................................... 8-1
8.2 FAULT TYPES.............................................................................................................. 8-3
8.3 FAULT TABLE .............................................................................................................. 8-4
8.4 STACK USED IN FAULT HANDLING........................................................................... 8-6
8.5 FAULT RECORD .......................................................................................................... 8-6
8.5.1 Fault Record Description ......................................................................................... 8-7
8.5.2 Fault Record Location ............................................................................................. 8-8
8.6 MULTIPLE AND PARALLEL FAULTS.......................................................................... 8-9
8.6.1 Multiple Non-Trace Faults on the Same Instruction ................................................ 8-9
8.6.2 Multiple Trace Fault Conditions on the Same Instruction ........................................ 8-9
8.6.3 Multiple Trace and Non-Trace Fault Conditions on the Same Instruction ............... 8-9
8.6.4 Parallel Faults .......................................................................................................... 8-9
8.6.4.1 Faults on Multiple Instructions Executed in Parallel ....................................... 8-10
8.6.4.2 Fault Record for Parallel Faults ...................................................................... 8-11
8.6.5 Override Faults ...................................................................................................... 8-11
8.6.6 System Error ......................................................................................................... 8-12
8.7 FAULT HANDLING PROCEDURES........................................................................... 8-12
8.7.1 Possible Fault Handling Procedure Actions .......................................................... 8-13
8.7.2 Program Resumption Following a Fault ................................................................ 8-13
8.7.2.1 Faults Happening Before Instruction Execution ............................................. 8-13
8.7.2.2 Faults Happening During Instruction Execution ............................................. 8-14
8.7.2.3 Faults Happening After Instruction Execution ................................................ 8-14
8.7.3 Return Instruction Pointer (RIP) ............................................................................ 8-14
8.7.4 Returning to the Point in the Program Where the Fault Occurred ......................... 8-15
8.7.5 Returning to a Point in the Program Other Than Where the Fault Occurred ......... 8-15
8.7.6 Fault Controls ........................................................................................................ 8-15
8.8 FAULT HANDLING ACTION....................................................................................... 8-16
8.8.1 Local Fault Call ...................................................................................................... 8-17
8.8.2 System-Local Fault Call ........................................................................................ 8-17
8.8.3 System-Supervisor Fault Call ................................................................................ 8-17
8.8.4 Faults and Interrupts ............................................................................................. 8-18
8.9 PRECISE AND IMPRECISE FAULTS ........................................................................ 8-19
8.9.1 Precise Faults ........................................................................................................ 8-19
8.9.2 Imprecise Faults .................................................................................................... 8-19
8.9.3 Asynchronous Faults ............................................................................................. 8-19
8.9.4 No Imprecise Faults (AC.nif) Bit ............................................................................ 8-20
8.9.5 Controlling Fault Precision .................................................................................... 8-20
8.10 FAULT REFERENCE.................................................................................................. 8-21
8.10.1 ARITHMETIC Faults .............................................................................................. 8-22
8.10.2 CONSTRAINT Faults ............................................................................................ 8-23

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8.10.3 OPERATION Faults ............................................................................................... 8-24
8.10.4 OVERRIDE Faults ................................................................................................. 8-26
8.10.5 PARALLEL Faults .................................................................................................. 8-27
8.10.6 PROTECTION Faults ............................................................................................ 8-28
8.10.7 TRACE Faults ........................................................................................................ 8-29
8.10.8 TYPE Faults .......................................................................................................... 8-32
CHAPTER 9
TRACING AND DEBUGGING
9.1 TRACE CONTROLS ..................................................................................................... 9-1
9.1.1 Trace Controls (TC) Register ................................................................................... 9-2
9.1.2 PC Trace Enable Bit and Trace-Fault-Pending Flag ............................................... 9-3
9.2 TRACE MODES ............................................................................................................ 9-3
9.2.1 Instruction Trace ...................................................................................................... 9-3
9.2.2 Branch Trace ........................................................................................................... 9-4
9.2.3 Call Trace ................................................................................................................ 9-4
9.2.4 Return Trace ............................................................................................................ 9-4
9.2.5 Prereturn Trace ....................................................................................................... 9-4
9.2.6 Supervisor Trace ..................................................................................................... 9-5
9.2.7 Mark Trace .............................................................................................................. 9-5
9.2.7.1 Software Breakpoints ....................................................................................... 9-5
9.2.7.2 Hardware Breakpoints ...................................................................................... 9-5
9.2.7.3 Requesting Modification Rights to Hardware Breakpoint Resources ............... 9-6
9.2.7.4 Breakpoint Control Register ............................................................................. 9-7
9.2.7.5 Data Address Breakpoint (DAB) Registers ....................................................... 9-9
9.2.7.6 Instruction Breakpoint (IPB) Registers ........................................................... 9-10
9.3 GENERATING A TRACE FAULT................................................................................ 9-11
9.4 HANDLING MULTIPLE TRACE EVENTS................................................................... 9-11
9.5 TRACE FAULT HANDLING PROCEDURE ................................................................ 9-12
9.5.1 Tracing and Interrupt Procedures .......................................................................... 9-12
9.5.2 Tracing on Calls and Returns ................................................................................ 9-12
9.5.2.1 Tracing on Explicit Call ................................................................................... 9-13
9.5.2.2 Tracing on Implicit Call ................................................................................... 9-14
9.5.2.3 Tracing on Return from Explicit Call ............................................................... 9-15
9.5.2.4 Tracing on Return from Implicit Call: Fault Case ............................................ 9-15
9.5.2.5 Tracing on Return from Implicit Call: Interrupt Case ...................................... 9-16
CHAPTER 10
TIMERS
10.1 TIMER REGISTERS.................................................................................................... 10-2
10.1.1 Timer Mode Registers (TMR0, TMR1) .................................................................. 10-3
10.1.1.1 Bit 0 - Terminal Count Status Bit (TMRx.tc) ................................................... 10-4
10.1.1.2 Bit 1 - Timer Enable (TMRx.enable) ............................................................... 10-4
10.1.1.3 Bit 2 - Timer Auto Reload Enable (TMRx.reload) ........................................... 10-5
10.1.1.4 Bit 3 - Timer Register Supervisor Read/Write Control (TMRx.sup) ................ 10-5

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10.1.1.5 Bits 4, 5 - Timer Input Clock Select (TMRx.csel1:0) ....................................... 10-6
10.1.2 Timer Count Register (TCR0, TCR1) .................................................................... 10-6
10.1.3 Timer Reload Register (TRR0, TRR1) .................................................................. 10-7
10.2 TIMER OPERATION................................................................................................... 10-7
10.2.1 Basic Timer Operation ........................................................................................... 10-7
10.2.2 Load/Store Access Latency for Timer Registers ................................................... 10-9
10.3 TIMER INTERRUPTS............................................................................................... 10-11
10.4 POWERUP/RESET INITIALIZATION ....................................................................... 10-11
10.5 UNCOMMON TCRX AND TRRX CONDITIONS....................................................... 10-12
10.6 TIMER STATE DIAGRAM......................................................................................... 10-13
CHAPTER 11
INTERRUPTS
11.1 OVERVIEW................................................................................................................. 11-1
11.1.1 The i960®Jx Processor Interrupt Controller .......................................................... 11-2
11.2 SOFTWARE REQUIREMENTS FOR INTERRUPT HANDLING................................ 11-3
11.3 INTERRUPT PRIORITY.............................................................................................. 11-3
11.4 INTERRUPT TABLE ................................................................................................... 11-4
11.4.1 Vector Entries ........................................................................................................ 11-5
11.4.2 Pending Interrupts ................................................................................................. 11-5
11.4.3 Caching Portions of the Interrupt Table ................................................................. 11-6
11.5 INTERRUPT STACK AND INTERRUPT RECORD.................................................... 11-7
11.6 MANAGING INTERRUPT REQUESTS ...................................................................... 11-8
11.6.1 External Interrupts ................................................................................................. 11-8
11.6.2 Non-Maskable Interrupt (NMI) ............................................................................... 11-8
11.6.3 Timer Interrupts ..................................................................................................... 11-9
11.6.4 Software Interrupts ................................................................................................ 11-9
11.6.5 Posting Interrupts .................................................................................................. 11-9
11.6.5.1 Posting Software Interrupts via sysctl ............................................................ 11-9
11.6.5.2 Posting Software Interrupts Directly in the Interrupt Table ........................... 11-11
11.6.5.3 Posting External Interrupts ........................................................................... 11-11
11.6.5.4 Posting Hardware Interrupts ........................................................................ 11-11
11.6.6 Resolving Interrupt Priority .................................................................................. 11-11
11.6.7 Sampling Pending Interrupts in the Interrupt Table ............................................. 11-12
11.6.8 Interrupt Controller Modes ................................................................................... 11-14
11.6.8.1 Dedicated Mode ........................................................................................... 11-14
11.6.8.2 Expanded Mode ........................................................................................... 11-15
11.6.8.3 Mixed Mode .................................................................................................. 11-17
11.6.9 Saving the Interrupt Mask ................................................................................... 11-17
11.7 EXTERNAL INTERFACE DESCRIPTION ................................................................ 11-18
11.7.1 Pin Descriptions .................................................................................................. 11-18
11.7.2 Interrupt Detection Options ................................................................................. 11-19
11.7.3 Memory-Mapped Control Registers ..................................................................... 11-21
11.7.4 Interrupt Control Register (ICON) ........................................................................ 11-22

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11.7.5 Interrupt Mapping Registers (IMAP0-IMAP2) ...................................................... 11-23
11.7.5.1 Interrupt Mask (IMSK) and Interrupt Pending (IPND) Registers ................... 11-25
11.7.5.2 Interrupt Controller Register Access Requirements ..................................... 11-27
11.7.5.3 Default and Reset Register Values .............................................................. 11-28
11.8 INTERRUPT OPERATION SEQUENCE................................................................... 11-28
11.8.1 Setting Up the Interrupt Controller ....................................................................... 11-31
11.8.2 Interrupt Service Routines ................................................................................... 11-31
11.8.3 Interrupt Context Switch ...................................................................................... 11-32
11.8.3.1 Servicing an Interrupt from Executing State ................................................. 11-32
11.8.3.2 Servicing an Interrupt from Interrupted State ............................................... 11-33
11.9 OPTIMIZING INTERRUPT PERFORMANCE........................................................... 11-33
11.9.1 Interrupt Service Latency ..................................................................................... 11-35
11.9.2 Features to Improve Interrupt Performance ......................................................... 11-35
11.9.2.1 Vector Caching Option ................................................................................. 11-35
11.9.2.2 Caching Interrupt Routines and Reserving Register Frames ....................... 11-36
11.9.2.3 Caching the Interrupt Stack .......................................................................... 11-36
11.9.3 Base Interrupt Latency ........................................................................................ 11-37
11.9.4 Maximum Interrupt Latency ................................................................................. 11-38
11.9.4.1 Avoiding Certain Destinations for MDU Operations ..................................... 11-42
11.9.4.2 Masking Integer Overflow Faults for syncf ................................................... 11-42
CHAPTER 12
INITIALIZATION AND SYSTEM REQUIREMENTS
12.1 OVERVIEW................................................................................................................. 12-1
12.2 INITIALIZATION .......................................................................................................... 12-2
12.2.1 Reset State Operation ........................................................................................... 12-3
12.2.2 Self Test Function (STEST, FAIL) ......................................................................... 12-6
12.2.2.1 The STEST Pin .............................................................................................. 12-7
12.2.2.2 External Bus Confidence Test ........................................................................ 12-7
12.2.2.3 The Fail Pin (FAIL) ......................................................................................... 12-7
12.2.2.4 IMI Alignment Check and System Error ......................................................... 12-8
12.2.2.5 FAIL Code ...................................................................................................... 12-8
12.3 Architecturally Reserved Memory Space .................................................................... 12-9
12.3.1 Initial Memory Image (IMI) ................................................................................... 12-10
12.3.1.1 Initialization Boot Record (IBR) .................................................................... 12-13
12.3.1.2 Process Control Block (PRCB) ..................................................................... 12-16
12.3.2 Process PRCB Flow ............................................................................................ 12-18
12.3.2.1 AC Initial Image ............................................................................................ 12-19
12.3.2.2 Fault Configuration Word ............................................................................. 12-19
12.3.2.3 Instruction Cache Configuration Word ......................................................... 12-19
12.3.2.4 Register Cache Configuration Word ............................................................. 12-19
12.3.3 Control Table ....................................................................................................... 12-20
12.4 DEVICE IDENTIFICATION ON RESET.................................................................... 12-22
12.4.1 Reinitializing and Relocating Data Structures ...................................................... 12-22
12.5 Startup Code Example .............................................................................................. 12-23

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12.6 SYSTEM REQUIREMENTS...................................................................................... 12-34
12.6.1 Input Clock (CLKIN) ............................................................................................ 12-34
12.6.2 Power and Ground Requirements (VCC, VSS) ..................................................... 12-34
12.6.3 VCC5 Pin Requirements ....................................................................................... 12-35
12.6.4 Power and Ground Planes .................................................................................. 12-35
12.6.5 Decoupling Capacitors ........................................................................................ 12-36
12.6.6 I/O Pin Characteristics ......................................................................................... 12-36
12.6.6.1 Output Pins .................................................................................................. 12-37
12.6.6.2 Input Pins ..................................................................................................... 12-37
12.6.7 High Frequency Design Considerations .............................................................. 12-38
12.6.8 Line Termination .................................................................................................. 12-38
12.6.9 Latchup ................................................................................................................ 12-39
12.6.10 Interference ......................................................................................................... 12-40
CHAPTER 13
MEMORY CONFIGURATION
13.1 Memory Attributes....................................................................................................... 13-1
13.1.1 Physical Memory Attributes ................................................................................... 13-1
13.1.2 Logical Memory Attributes ..................................................................................... 13-2
13.2 Differences With Previous i960 Processors................................................................ 13-3
13.3 Programming the Physical Memory Attributes (PMCON Registers)........................... 13-4
13.3.1 Bus Width .............................................................................................................. 13-5
13.4 Physical Memory Attributes at Initialization................................................................. 13-5
13.4.1 Bus Control (BCON) Register ................................................................................ 13-6
13.5 Boundary Conditions for Physical Memory Regions................................................... 13-7
13.5.1 Internal Memory Locations .................................................................................... 13-7
13.5.2 Bus Transactions Across Region Boundaries ....................................................... 13-7
13.5.3 Modifying the PMCON Registers ........................................................................... 13-7
13.6 Programming the Logical Memory Attributes.............................................................. 13-8
13.6.1 Defining the Effective Range of a Logical Data Template ................................... 13-11
13.6.2 Selecting the Byte Order ..................................................................................... 13-12
13.6.3 Data Caching Enable .......................................................................................... 13-12
13.6.4 Enabling the Logical Memory Template .............................................................. 13-12
13.6.5 Initialization .......................................................................................................... 13-13
13.6.6 Boundary Conditions for Logical Memory Templates .......................................... 13-13
13.6.6.1 Internal Memory Locations ........................................................................... 13-13
13.6.6.2 Overlapping Logical Data Template Ranges ............................................... 13-13
13.6.6.3 Accesses Across LMT Boundaries .............................................................. 13-14
13.6.7 Modifying the LMT Registers ............................................................................... 13-14
13.6.8 Dynamic Byte Order Changing ............................................................................ 13-14
CHAPTER 14
EXTERNAL BUS
14.1 OVERVIEW................................................................................................................. 14-1

xiv
14.2 BUS OPERATION....................................................................................................... 14-1
14.2.1 Basic Bus States ................................................................................................... 14-2
14.2.2 Bus Signal Types ................................................................................................... 14-4
14.2.2.1 Clock Signal ................................................................................................... 14-4
14.2.2.2 Address/Data Signal Definitions ..................................................................... 14-4
14.2.2.3 Control/Status Signal Definitions .................................................................... 14-4
14.2.3 Bus Accesses ........................................................................................................ 14-6
14.2.3.1 Bus Width ....................................................................................................... 14-7
14.2.3.2 Basic Bus Accesses ....................................................................................... 14-9
14.2.3.3 Burst Transactions ....................................................................................... 14-11
14.2.3.4 Wait States ................................................................................................... 14-17
14.2.3.5 Recovery States ........................................................................................... 14-19
14.2.4 Bus and Control Signals During Recovery and Idle States ................................. 14-22
14.2.5 Data Alignment .................................................................................................... 14-22
14.2.6 Byte Ordering and Bus Accesses ........................................................................ 14-28
14.2.7 Atomic Bus Transactions ..................................................................................... 14-30
14.2.8 Bus Arbitration ..................................................................................................... 14-31
14.2.8.1 HOLD/HOLDA Protocol ................................................................................ 14-32
14.2.8.2 BSTAT Signal ............................................................................................... 14-33
14.3 BUS APPLICATIONS................................................................................................ 14-34
14.3.1 System Block Diagrams ...................................................................................... 14-34
14.3.1.1 Memory Subsystems .................................................................................... 14-37
14.3.1.2 I/O Subsystems ............................................................................................ 14-37
CHAPTER 15
TEST FEATURES
15.1 ON-CIRCUIT EMULATION (ONCE)............................................................................ 15-1
15.1.1 Entering/Exiting ONCE Mode ................................................................................ 15-1
15.2 BOUNDARY SCAN (JTAG)......................................................................................... 15-2
15.2.1 Boundary Scan Architecture .................................................................................. 15-2
15.2.1.1 TAP Controller ................................................................................................ 15-2
15.2.1.2 Instruction Register ........................................................................................ 15-2
15.2.1.3 Test Data Registers ........................................................................................ 15-2
15.2.1.4 TAP Elements ................................................................................................ 15-3
15.3 TAP REGISTERS........................................................................................................ 15-5
15.3.1 Instruction Register (IR) ......................................................................................... 15-5
15.3.2 TAP Test Data Registers ....................................................................................... 15-6
15.3.2.1 Device Identification Register ......................................................................... 15-6
15.3.2.2 Bypass Register ............................................................................................. 15-6
15.3.2.3 RUNBIST Register ......................................................................................... 15-7
15.3.2.4 Boundary-Scan Register ................................................................................ 15-7
15.3.3 Boundary Scan Instruction Set .............................................................................. 15-8
15.3.4 IEEE Required Instructions ................................................................................... 15-8
15.3.5 TAP Controller ....................................................................................................... 15-9
15.3.5.1 Test Logic Reset State ................................................................................. 15-10
15.3.5.2 Run-Test/Idle State ...................................................................................... 15-10

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15.3.5.3 Select-DR-Scan State .................................................................................. 15-10
15.3.5.4 Capture-DR State ......................................................................................... 15-10
15.3.5.5 Shift-DR State .............................................................................................. 15-11
15.3.5.6 Exit1-DR State ............................................................................................. 15-11
15.3.5.7 Pause-DR State ........................................................................................... 15-11
15.3.5.8 Exit2-DR State ............................................................................................. 15-11
15.3.5.9 Update-DR State .......................................................................................... 15-12
15.3.5.10 Select-IR Scan State .................................................................................... 15-12
15.3.5.11 Capture-IR State .......................................................................................... 15-12
15.3.5.12 Shift-IR State ................................................................................................ 15-12
15.3.5.13 Exit1-IR State ............................................................................................... 15-13
15.3.5.14 Pause-IR State ............................................................................................. 15-13
15.3.5.15 Exit2-IR State ............................................................................................... 15-13
15.3.5.16 Update-IR State ........................................................................................... 15-13
15.3.6 Boundary-Scan Register ..................................................................................... 15-14
15.3.6.1 Example ....................................................................................................... 15-15
15.3.7 Boundary Scan Description Language Example ................................................. 15-18
APPENDIX A
CONSIDERATIONS FOR WRITING PORTABLE CODE
A.1 CORE ARCHITECTURE.................................................................................................. A-1
A.2 ADDRESS SPACE RESTRICTIONS............................................................................... A-2
A.2.1 Reserved Memory ..................................................................................................... A-2
A.2.2 Initialization Boot Record ........................................................................................... A-2
A.2.3 Internal Data RAM ..................................................................................................... A-2
A.2.4 Instruction Cache ...................................................................................................... A-2
A.3 Data and Data Structure Alignment.................................................................................. A-3
A.4 RESERVED LOCATIONS IN REGISTERS AND DATA STRUCTURES......................... A-4
A.5 INSTRUCTION SET......................................................................................................... A-4
A.5.1 Instruction Timing ...................................................................................................... A-4
A.5.2 Implementation-Specific Instructions ......................................................................... A-5
A.6 EXTENDED REGISTER SET........................................................................................... A-5
A.7 INITIALIZATION............................................................................................................... A-5
A.8 MEMORY CONFIGURATION .......................................................................................... A-6
A.9 INTERRUPTS .................................................................................................................. A-6
A.10 OTHER i960 Jx PROCESSOR IMPLEMENTATION-SPECIFIC FEATURES.................. A-6
A.10.1 Data Control Peripheral Units .................................................................................... A-7
A.10.2 Timers ....................................................................................................................... A-7
A.10.3 Fault Implementation ................................................................................................. A-7
A.11 BREAKPOINTS................................................................................................................ A-7
APPENDIX B
OPCODES AND EXECUTION TIMES
B.1 INSTRUCTION REFERENCE BY OPCODE ................................................................... B-1

xvi
APPENDIX C
MACHINE-LEVEL INSTRUCTION FORMATS
C.1 GENERAL INSTRUCTION FORMAT.............................................................................. C-1
C.2 REG FORMAT................................................................................................................. C-2
C.3 COBR FORMAT.............................................................................................................. C-3
C.4 CTRL FORMAT............................................................................................................... C-4
C.5 MEM FORMAT ................................................................................................................ C-4
C.5.1 MEMA Format Addressing ........................................................................................ C-5
C.5.2 MEMB Format Addressing ........................................................................................ C-6
APPENDIX D
REGISTER AND DATA STRUCTURES
D.1 REGISTERS.................................................................................................................... D-3
GLOSSARY
INDEX

xvii
FIGURES
Figure 1-1. i960®Jx Microprocessor Functional Block Diagram............................................ 1-3
Figure 2-1. Data Types and Ranges...................................................................................... 2-1
Figure 2-2. Data Placement in Registers ............................................................................... 2-6
Figure 3-1. i960®Jx Processor Programming Environment Elements .................................. 3-2
Figure 3-2. Memory Address Space .................................................................................... 3-13
Figure 3-3. Arithmetic Controls (AC) Register...................................................................... 3-18
Figure 3-4. Process Controls (PC) Register......................................................................... 3-21
Figure 4-1. Internal Data RAM and Register Cache .............................................................. 4-2
Figure 5-1. Machine-Level Instruction Formats...................................................................... 5-3
Figure 6-1. dcctl
src1 and src/dst Formats........................................................................... 6-41
Figure 6-2. Store Data Cache to Memory Output Format.................................................... 6-42
Figure 6-3. D-Cache Tag and Valid Bit Formats.................................................................. 6-43
Figure 6-4. icctl
src1 and src/dst Formats............................................................................ 6-59
Figure 6-5. Store Instruction Cache to Memory Output Format........................................... 6-61
Figure 6-6. I-Cache Set Data, Tag and Valid Bit Formats.................................................... 6-62
Figure 6-7. Src1 Operand Interpretation ............................................................................ 6-114
Figure 6-8.
src/dst Interpretation for Breakpoint Resource Request.................................. 6-115
Figure 7-1. Procedure Stack Structure and Local Registers.................................................. 7-3
Figure 7-2. Frame Spill........................................................................................................... 7-9
Figure 7-3. Frame Fill........................................................................................................... 7-10
Figure 7-4. System Procedure Table ................................................................................... 7-16
Figure 7-5. Previous Frame Pointer Register (PFP) (r0)...................................................... 7-20
Figure 8-1. Fault-Handling Data Structures ........................................................................... 8-1
Figure 8-2. Fault Table and Fault Table Entries..................................................................... 8-5
Figure 8-3. Fault Record ........................................................................................................ 8-7
Figure 8-4. Storage of the Fault Record on the Stack............................................................ 8-8
Figure 9-1. 80960Jx Trace Controls (TC) Register................................................................ 9-2
Figure 9-2. Breakpoint Control Register (BPCON)................................................................. 9-8
Figure 9-3. Data Address Breakpoint (DAB) Register Format ............................................. 9-10
Figure 9-4. Instruction Breakpoint (IPB) Register Format.................................................... 9-10
Figure 10-1. Timer Functional Diagram ................................................................................. 10-1
Figure 10-2. Timer Mode Register (TMR0, TMR1) ................................................................ 10-3
Figure 10-3. Timer Count Register (TCR0, TCR1)................................................................. 10-6
Figure 10-4. Timer Reload Register (TRR0, TRR1)............................................................... 10-7
Figure 10-5. Timer Unit State Diagram ................................................................................ 10-13
Figure 11-1. Interrupt Handling Data Structures .................................................................... 11-2
Figure 11-2. Interrupt Table ................................................................................................... 11-4
Figure 11-3. Storage of an Interrupt Record on the Interrupt Stack....................................... 11-7
Figure 11-4. Dedicated Mode............................................................................................... 11-14

xviii
Figure 11-5. Expanded Mode .............................................................................................. 11-15
Figure 11-6. Implementation of Expanded Mode Sources................................................... 11-16
Figure 11-7. Interrupt Sampling ........................................................................................... 11-20
Figure 11-8. Interrupt Control (ICON) Register.................................................................... 11-22
Figure 11-9. Interrupt Mapping (IMAP0-IMAP2) Registers.................................................. 11-24
Figure 11-10. Interrupt Pending (IPND) Register................................................................... 11-25
Figure 11-11. Interrupt Mask (IMSK) Registers ..................................................................... 11-26
Figure 11-12. Interrupt Controller........................................................................................... 11-30
Figure 11-13. Interrupt Service Flowchart.............................................................................. 11-34
Figure 12-1. Processor Initialization Flow.............................................................................. 12-2
Figure 12-2. Cold Reset Waveform ....................................................................................... 12-4
Figure 12-3. FAIL Sequence.................................................................................................. 12-8
Figure 12-4. Initial Memory Image (IMI) and Process Control Block (PRCB)...................... 12-12
Figure 12-5. PMCON14_15 Register Bit Description in IBR................................................ 12-15
Figure 12-6. Process Control Block Configuration Words.................................................... 12-17
Figure 12-7. Control Table................................................................................................... 12-21
Figure 12-8. IEEE 1149.1 Device Identification Register..................................................... 12-22
Figure 12-9. VCC5 Current-Limiting Resistor........................................................................ 12-35
Figure 12-10. Reducing Characteristic Impedance................................................................ 12-36
Figure 12-11. Series Termination ......................................................................................... 12-39
Figure 12-12. AC Termination................................................................................................ 12-39
Figure 12-13. Avoid Closed-Loop Signal Paths..................................................................... 12-41
Figure 13-1. PMCON and LMCON Example ......................................................................... 13-2
Figure 13-2. PMCON Register Bit Description....................................................................... 13-5
Figure 13-3. Bus Control Register (BCON)............................................................................ 13-6
Figure 13-4. Logical Memory Template Starting Address Registers (LMADR0-1) ................ 13-8
Figure 13-5. Logical Memory Template Mask Registers (LMMR0-1) .................................... 13-9
Figure 13-6. Default Logical Memory Configuration Register (DLMCON)........................... 13-10
Figure 14.1. Bus States with Arbitration ................................................................................ 14-3
Figure 14-2. Data Width and Byte Encodings........................................................................ 14-7
Figure 14-3. Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus...... 14-10
Figure 14-4. 32-Bit Wide Data Bus Bursts........................................................................... 14-12
Figure 14-5. 16-Bit Wide Data Bus Bursts........................................................................... 14-12
Figure 14-6. 8-Bit Wide Data Bus Bursts............................................................................. 14-13
Figure 14-7. Unaligned Write Transaction ........................................................................... 14-14
Figure 14-8. Burst Read and Write Transactions w/o Wait States, 32-bit Bus..................... 14-15
Figure 14-9. Burst Read and Write Transactions w/o Wait States, 8-bit Bus....................... 14-16
Figure 14-10. Burst Write Transactions With 2,1,1,1 Wait States, 32-bit Bus........................ 14-18
Figure 14-11. Burst Read/Write Transactions with 1,0 Wait States - Extra Tr State
on Read, 16-Bit Bus ........................................................................................ 14-20

xix
Figure 14-12. Burst Read/Write Transactions with 1,0 Wait States, Extra Tr State
on Read, 16-Bit Bus 14-21
Figure 14-13. Summary of Aligned and Unaligned Accesses (32-Bit Bus)............................ 14-25
Figure 14-14. Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued)........ 14-26
Figure 14-15. Accesses Generated by Double Word Read Bus Request, Misaligned
One Byte From Quad Word Boundary, 32-Bit Bus, Little Endian 14-27
Figure 14-16. Multi-Word Access to Big-Endian Memory Space ........................................... 14-29
Figure 14-17. The LOCK Signal............................................................................................. 14-31
Figure 14-18. Arbitration Timing Diagram for a Bus Master................................................... 14-33
Figure 14-19. Generalized 80960Jx System with 80960 Local Bus....................................... 14-35
Figure 14-20. Generalized 80960Jx System with 80960 Local Bus and Backplane Bus....... 14-35
Figure 14-21. 80960Jx System with 80960 Local Bus, PCI Local Bus and Local Bus
for High End Microprocessor 14-36
Figure 15-1. Test Access Port Block Diagram ....................................................................... 15-3
Figure 15-2. TAP Controller State Diagram ........................................................................... 15-4
Figure 15-3. JTAG Example................................................................................................. 15-16
Figure 15-4. Timing diagram illustrating the loading of Instruction Register ........................ 15-17
Figure 15-5. Timing diagram illustrating the loading of Data Register ................................. 15-18
Figure C-1. Instruction Formats............................................................................................. C-1
Figure D-1. AC (Arithmetic Controls) Register....................................................................... D-3
Figure D-2. PC (Process Controls) Register.......................................................................... D-4
Figure D-3. Procedure Stack Structure and Local Registers................................................. D-5
Figure D-4. System Procedure Table .................................................................................... D-6
Figure D-5. PFP (Previous Frame Pointer) Register (r0)....................................................... D-7
Figure D-6. Fault Table and Fault Table Entries.................................................................... D-8
Figure D-7. Fault Record ....................................................................................................... D-9
Figure D-8. TC (Trace Controls) Register............................................................................ D-10
Figure D-9. BPCON (Breakpoint Control) Register.............................................................. D-10
Figure D-10. DAB (Data Address Breakpoint) Register Format ............................................ D-11
Figure D-11. IPB (Instruction Breakpoint) Register Format................................................... D-11
Figure D-12. TMR0-1 (Timer Mode Register)........................................................................ D-12
Figure D-13. TCR0-1 (Timer Count Register)........................................................................ D-12
Figure D-14. TRR0-1 (Timer Reload Register)...................................................................... D-13
Figure D-15. Interrupt Table .................................................................................................. D-14
Figure D-16. Storage of an Interrupt Record on the Interrupt Stack...................................... D-15
Figure D-17. ICON (Interrupt Control) Register..................................................................... D-16
Figure D-18. IMAP0-IMAP2 (Interrupt Mapping) Registers ................................................... D-17
Figure D-19. IMSK (Interrupt Mask) Registers....................................................................... D-18
Figure D-20. Interrupt Pending (IPND) Register.................................................................... D-19
Figure D-21. Initial Memory Image (IMI) and Process Control Block (PRCB) ....................... D-20
Figure D-22. Process Control Block Configuration Words..................................................... D-21

xx
Figure D-23. Control Table..................................................................................................... D-22
Figure D-24. IEEE 1149.1 Device Identification Register....................................................... D-23
Figure D-25. PMCON Register Bit Description....................................................................... D-23
Figure D-26. BCON (Bus Control) Register............................................................................ D-24
Figure D-27. DLMCON (Default Logical Memory Configuration) Register............................. D-24
Figure D-28. LMADR0:1 Logical Memory Template Starting Address Registers................... D-25
Figure D-29. LMMR0:1 (Logical Memory Mask Registers)..................................................... D-25