Intel Core 2 Duo Processor User manual

Order Num ber : 317443- 001US
I nt el®CoreTM 2 Duo proce ssor w it h
t he Mobile I nt e l®9 4 5 GME Express
Chipset
Developm ent Kit User’s M anual
Ma y 2 0 0 7

I nt el®CoreTM 2 Duo processor with t he Mobile I ntel®945GME Expr ess Chipset
Manual May 2007
2Or der Num ber : 3 17 44 3- 00 1US
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I nt el®CoreTM 2 Duo processor w it h t he Mobile I nt el®945GME Expr ess Chipset
May 2007 Manual
Order Nu m ber : 317443- 001US 3
Con t e n t s—I n t el ®9 4 5 GM E Expr ess Chipse t
Cont e nt s
1 .0 About This Manua l ..................................................................................................... 7
1.1 Cont ent Overv iew . ....................................... .......................... .............................. 7
1.2 Text Conventions ................................................................................................ 7
1.3 Glossar y of Term s an d Acrony m s.................................. ............. ............. ............... 9
1.4 Support Options ................................................................................................ 14
1.4.1 Elect r onic Support Syst em s ......... ....... ................... .............. ........... ......... 14
1.4.2 Addit ional Technical Support .................................................................... 14
1.5 Product Lit erat ure ............................................................................................. 14
1.6 Relat ed Docum ent s ........................................................................................... 15
2 . 0 Ge t t ing St a rt e d ........................................................................................................ 16
2.1 Overview ......................................................................................................... 16
2.1.1 I nt el®945GME Express Chipset Developm ent Kit Features........................... 16
2.2 I ncluded Hardw ar e and Docum ent ation ................................................. ............... 18
2.3 Soft ware Key Feat ures ....................................................................................... 18
2.3.1 AMI * BI OS ............................................................................................ 18
2.4 Before You Begin ............................................................................................... 19
2.5 Set ting Up t he Evaluat ion Board .......................................................................... 20
2.6 Configur ing the BI OS ......................................................................................... 21
3 . 0 Th e or y o f Ope ra t io n................................................................................................. 22
3.1 Block Diagram .................................................................................................. 22
3.2 Mechanical For m Fact or ... .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . 23
3.3 Therm al Managem ent . ........................................................................ ............... 23
3.4 System Features and Operat ion .......................................................................... 23
3.4.1 I n tel( R) 945GME GMCH .. .. .. ... ............................................ .. .. .. ... ............. 23
3.4.1.1 System Mem or y ....................................................................... 24
3.4.1.2 DMI ........................................................................................ 24
3.4.1.3 Advanced Graphics and Display I nt erface ..................................... 24
3.4.2 I CH7- M ................................................................................................. 24
3.4.2.1 PCI Express* Slots .................................................................... 24
3.4.2.2 PCI Slot s ................................................................................. 25
3.4.2 .3 On- Board LAN . .. .. .. ... ................................................................ 25
3.4.2.4 AC’97 and High Definit ion Audio.................................................. 25
3.4.2.5 ATA / Storage .......................................................................... 25
3.4.2.6 USB Connectors........................................................................ 26
3.4.2. 7 LPC Super I / O ( SI O) / LPC Slot ...... .. .. .. .. ............................ .. .. .. .. ... 26
3.4.2.8 Serial, I rDA.............................................................................. 26
3.4.2. 9 BI OS Firm w ar e Hub ( FWH) . ...................................... .. .. .. ... ......... 26
3.4.2.1 0 Sy st em Managem en t Con t roller ( SMC) / Keyboard Cont roller ... ......... 26
3.4.2.11 Clocks ..................................................................................... 27
3.4.2 .12 Real Tim e Clock ........................................................................ 27
3.4.2 .13 Ther m al Mon it or ing ................................. ................... ............... 27
3.4.3 Sy st em I / O and Connect or Sum m ary ......................................... .............. . 27
3.4.3.1 PCI Express* Support ................................................................ 28
3.4.3.2 SATA Support ........................................................................... 28
3.4.3.3 I DE Suppor t ... .......................................................................... 28
3.4.3.4 USB Ports ................................................................................ 28
3.4.3.5 VGA Connector ......................................................................... 28
3.4.3 .6 Key boar d/ Mouse . .. .. .. .. .. ............................................................ 29
3.4.3.7 32 bit/ 33 MHz PCI Connect ors .................................................... 29
3.4.3.8 Et hernet Gigabit LAN I nt erface connect or ..................................... 29
3.4.3.9 LVDS Flat Panel Display I nter face................................................ 29
3.4.4 POST Code Debugger ......................... ................................... .................. 29

I n t el®9 4 5 GM E Ex p r ess Ch ip se t —Con t e n t s
I nt el®CoreTM 2 Duo processor wit h t he Mobile I nt el®945GME Express Chipset
Manual May 2007
4Or der Num ber : 3 17 44 3- 00 1US
3.5 Clock Gener at ion .... .......... ......... .. ........ ........... .. .... ............ ... .. ............ ... .. ........... 29
3.6 Pow er Managem ent St at es . .. .. .. .. .. .. .. .. ... .. ......... .. .... ............. .. ...... ........... .. ...... ..... 30
3.6.1 Transit ion t o S3 . .. ........... .. ...... ............ ... .. ............ ... .. ............ ..... .. ........... 31
3.6.2 Transit ion t o S4 . .. ........... .. ...... ............ ... .. ............ ... .. ............ ..... .. ........... 31
3.6.3 Transit ion t o S5 . .. ........... .. ...... ............ ... .. ............ ... .. ............ ..... .. ........... 31
3.6.4 Transit ion t o Full- On ......................... .. .. .. ... ........................................ .. .. . 31
3.7 Pow er Measur em ent Support .................................. ............. .. .... ............ ... .. ......... 31
4 .0 H ar dw a re Refer ence ..... ................... .. ................... .. ................. .. ................. .. ........... 35
4.1 Pr im ar y Feat ures ....................... ...... ............ ... .. .............. ... .. ............ ..... .. .......... . 35
4.2 Back Panel Connect or s .. .. .... ....... .. ...... .......... ... .. .......... ....... .. ...... .......... ... .. ......... 38
4.3 Configur at ion Set tin gs ..................................... .......... ......... .. .... .......... ... .. ........ ... 39
4.4 Pow er On and Reset But t ons ............................ .... ...... ........ ... .. ........ ...... ... .. ........ . 42
4.5 LEDs ................................................................................................................ 43
4.6 Ot her Header s, Slot s, and Socket s . .. .. .. .. .. .... .... ... .. ........ ....... .. .... .......... ... .. ........ ... 43
4.6.1 H8 Pr ogr am m ing Headers .. .. ...... ........... .. ...... ........... .. ........ ......... .. .......... . 43
4.6.2 Expansion Slot s an d Sock et s ................. ........ ........ ... .. ........ ........ ... .. ........ . 44
4.6.2 .1 478 Pin Gr id Ar ray ( Micro- FCPGA) Socket . .. ............................. .. .. . 44
4.6.2 .2 PCI Expr ess* ( x1 6) . ... ................................................................ 45
4.6.2 .3 Media Expansion Car d ( MEC) Slot . ........................................ .. .. .. . 47
4.6.2 .4 PCI Expr ess* ( x1 ) . .. .. .. .. .. .......................................................... 49
4.6.2 .5 I DE Conn ect or . .. .. .. .. .. ... .. ....... .. ...... ........... .. ........ ......... .. .......... . 51
4.6. 2. 6 SATA Pinou t ............................................................................. 51
4.6.2 .7 Fan Connect ors ......................................... .. ...... ........... .. .... ....... 52
A H e at Sin k I n st a lla t ion I n st r u ct ion s . .. .. .. ... .. ........... .. ................. .. ................. .. ........... 53
Figure s
1Intel
®945GME Express Chipset Developm ent Kit Block Diagram ..................................... 22
2Intel
®945GME Express Chipset Com ponent Locat ions .. .. .. .. ......... .. .. .. ......... .. .. .. ......... .. .. 3 5
3 Back Panel Connector Locations..................................................................... .. ........... 38
4 Configurat ion Jum per and Swit ch Locat ions.. ........ ........................................................ 39
5Intel
®945GME Express Chipset Developm ent Kit Power On and Reset But tons .................42
6 Heatsink and Backplat e ............................................................................................. 53
7 Backplat e Pins.................................. ............ ......... .. .......... ....... .. ............ ..... .. ........... 54
8 Applying t he Therm al Gr ease ......................... ........ ... .. ........ ....... .. .... ........ ..... .. ...... ..... 55
9 Squeezing Act ivat ion Ar m . .. .. .. .. .. .. .. .. .. .. ... .. .......... ... .. ............ ..... .. .......... ....... .. .......... . 55
10 I nstalling the Heatsink ..............................................................................................56
11 Plugging in t he Fan .............................................................. ..... .. .......... ....... .. .......... . 57
12 Com plet ed Assem bly ......................... ........................................................... ............. 57
Ta bles
1 Acronym s ........................................ ....................... .................................... ............. 11
2 I nt el Lit er at ur e Centers ..................... ........................................................... ............. 14
3 Relat ed Docum ent s................................................ .. ........ ......... .. .......... ....... .. ........... 15
4 Pr im ar y Syst em Clocks... .. ........ ......... .. ...... ............. .. .... ............ ... .. ............ ... .. ........... 29
5Intel
®945GME Express Chipset Developm ent Kit Power Managem ent St ates.................... 30
6Intel
®945GME Express Chipset Developm ent Kit Volt age Rails ....................................... 32
7Intel
®945GME Express Chipset Com ponent Location Legend ......................................... 36
8 Supported Configurat ion Jum per/ Swit ch Settings .......................................................... 40
9Intel
®945GME Express Chipset LED Funct ion Legend. .. .. .. .. .. ......... .. .. .. ........ .. .. .. ......... .. . 43
10 H8 Program m ing Jum pers....................................... ...................................... ............. 44
11 Expansion Slot s an d Sock et s .................................................................. ....... .. ...... ..... 44
12 PCI Expr ess* ( x 16) Pinout ( J6 C1) ......................... .. .. .. ... ............................................. 45

I nt el®CoreTM 2 Duo processor w it h t he Mobile I nt el®945GME Expr ess Chipset
May 2007 Manual
Order Nu m ber : 317443- 001US 5
Con t e n t s—I n t el ®9 4 5 GM E Expr ess Chipse t
13 MEC Slot ( J6C1) . .. .. ................................................................ .. .. .. .. .. ........................ 47
14 PCI Express* ( x1 ) Pinout ( J7C1, J8C1) .. .. ................................................ .. .. .. ... ........... 49
15 I DE Connect or ( J7J1) .. ............................................................ .. .. .. .. .. ........................ 51
16 SATA Por t 0 Dat a Connect or Pinout ( J7H1) .... .. .. .. .. ...................................... .. .. .. ... ....... 51
17 SATA Por t 0 Power Connect or Pinout ( J6H3) . ..... .. ........................................................ 52
18 SATA Port 2 Mobile Driv e Connect or Pinout ( J8J2) . ....................................................... 52
19 Fan Con nect ors ( J3F1 and J3C1) ...... .. .. .. .. ................................................... .. .. .. .. ....... 52

I n t el®9 4 5 GM E Ex pr ess Chipse t—Revision H ist or y
I nt el®CoreTM 2 Duo processor wit h t he Mobile I nt el®945GME Express Chipset
Manual May 2007
6Or der Num ber : 3 17 44 3- 00 1US
Re vision H ist or y
D a t e Re v isio n D e scr ip t io n
May 20 07 001 I nit ial r elease

I nt el®CoreTM 2 Duo processor w it h t he Mobile I nt el®945GME Expr ess Chipset
May 2007 Manual
Order Nu m ber : 317443- 001US 7
Ab ou t T hi s M a n u al —I n t e l®9 4 5 GM E Ex pr ess Ch ip set
1 .0 About This Ma nual
This user’s manual describes the use of t he I nt el®CoreTM 2 Duo processor wit h the
Mobile I nt el®945GME Express Chipset. This m anual has been w rit ten for OEMs, syst em
evaluat ors, and em bedded syst em dev eloper s. This docum ent defines all j u m per s,
headers, LED functions, and t heir locat ions on t he board, along w it h subsyst em
feat ures and POST codes. This m anual assum es basic fam iliar it y in t he fundam ent al
concepts involved wit h installing and configur ing hardware for a personal com puter
sy st em .
For the lat est inform at ion about t he I nt el®945GME Express Chipset Developm ent Kit ,
visit :
htt p: / / developer.intel.com / design/ intarch/ devkits/ index.htm
For design docum ents related t o t his plat form please contact ht t p: / /
developer.intel.com / design/ int arch/ core2duo/ t ech_docs.ht m .
Note: The I nt el®945GME Express Chipset support s both I nt el®CoreTM Duo processors and
I ntel®CoreTM 2 Duo processors. For t he I nt el®945GME Expr ess Chipset wit h I ntel®
Cor eTM Duo Processors Developm ent Kit User's Manual, visit ht tp: / / download.int el.com
1 .1 Con t en t Ove rview
Chapter 1.0, “About This Manual” — This ch apt er cont ains a descr ipt ion of convent ion s
used in this m anual. The last few sect ions explain how to obt ain lit erat ure and cont act
cust om er suppor t .
Chapt er 2 .0 , “ Get t ing St ar ted” — Provides com plet e instruct ions on how to configur e
t he evaluation boar d and pr ocessor assem bly by sett ing j um per s, connecting
per ipherals, providing power, and configuring the BI OS.
Chapt er 3 .0 , “ Theory of Oper at ion” — This chapt er provides inform ation on t he syst em
design.
Chapt er 4 .0, “ Har dw ar e Reference” — This chapt er pr ov ides a descript ion of j u m per
set t ings and funct ions, board debug capabilit ies, and pinout inform ation for connectors.
Appendix A, “ Heat Sink I nst allation I nst ruct ions” gives det ailed inst allat ion inst ruct ions
for t he I ntel®CoreTM 2 Duo processor heat sink.
1 .2 Te x t Con vent ion s
The following not at ions m ay be used t hroughout t his m anual.
# The pound sym bol ( # ) appended t o a signal nam e indicat es t hat
t he sign al is act iv e low. ( e. g., PRSNT1 # )
Va ria bles Var iables ar e shown in it alics. Variables m ust be replaced with
correct values.

I n t e l®9 4 5 GM E Ex pr e ss Ch ip se t —Abo ut T his M a nu a l
I nt el®CoreTM 2 Duo processor wit h t he Mobile I nt el®945GME Express Chipset
Manual May 2007
8Or der Num ber : 3 17 44 3- 00 1US
I n st r uct ion s I nst ruct ion m nem onics are shown in uppercase. When you are
pr ogram m ing, inst ruct ions are not case- sensitive. You m ay use
eit her uppercase or lower case.
N u m b er s Hexadecim al num bers are represented by a str ing of
hexadecim al digit s followed by t he charact er H. A zer o prefix is
added t o num bers t hat begin with A t hrough F. ( For exam ple, FF
is shown as 0FFH.) Decim al and binar y num ber s ar e
r epresen t ed by t h eir cust om ary not at ion s. ( That is, 255 is a
decim al num ber and 1111 1111 is a binary num ber. I n som e
cases, t he let ter B is added for clarity.)
Un it s of M e a su r e The following abbreviat ions are used t o repr esent unit s of
m easur e:
A am ps, am peres
GByt e gigabytes
KByt e kilobytes
KΩkilo- ohm s
m A m illiam ps, m illiam peres
MBy te m egabyt es
MHz m egahert z
m s m illiseconds
m W m illiwat ts
ns nanoseconds
pF picofarads
W wat ts
V volt s
µA m icroam ps, m icroam peres
µF m icrofarads
µs m icroseconds
µW m icrowat ts
Sig na l N a m e s Signal nam es are shown in upper case. When several signals
shar e a com m on nam e, an individual signal is r epresented by
the signal nam e followed by a num ber, w hile t he group is
represent ed by t he signal nam e followed by a variable ( n) . For
exam ple, t he lower chip- select signals ar e nam ed CS0# , CS1# ,
CS2# , and so on; they are collectively called CSn# . A pound
sy m bol ( # ) appended t o a signal nam e ident ifies an act ive- low
signal. Port pins are represent ed by the port abbreviat ion, a
per iod, an d t h e pin num ber ( e. g., P1. 0) .

I nt el®CoreTM 2 Duo processor w it h t he Mobile I nt el®945GME Expr ess Chipset
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Order Nu m ber : 317443- 001US 9
Ab ou t T hi s M a n u al —I n t e l®9 4 5 GM E Ex pr ess Ch ip set
1 .3 Glossary of Ter m s a nd Acronym s
This sect ion def ines convent ions and t er m inology used t hr ough out t his docum en t.
Aggr essor A net work t hat t ransm its a coupled signal t o anot her net work.
An t i- e t ch Any plan e- split , void or cut out in a VCC or GND plane.
Assist e d Gu nning Tr a nsce ive r Logic+
The f ront- side bus u ses a bu s t ech nology called AGTL+ , or
Assist ed Gunning Transceiver Logic. AGTL+ buffers are open-
drain, and require pull-up resist ors to provide the high logic level
and t erm inat ion. AGTL+ out put buffers differ from GTL+ buffer s
wit h t he addition of an act ive pMOS pull- up transistor t o assist
the pull- up resistors during the first clock of a low-t o- high
volt age t ransit ion.
Asyn chronous GTL+ The processor does not ut ilize CMOS voltage levels on any
signals t hat connect to t he processor. As a r esult , legacy input
signals such as A20M# , I GNNE# , I NI T# , LI NT0/ I NTR, LI NT1/
NMI , PWRGOOD, SMI # , SLP# , and STPCLK# ut ilize GTL+ input
buffers. Legacy out put signals ( FERR# and I ERR# ) and non-
AGTL+ signals ( THERMTRI P# and PROCHOT# ) also ut ilize GTL+
output buffers. All of t hese signals follow t he sam e DC
requirem ent s as AGTL+ signals, however the outputs are not
act ively dr iven high (during a logical 0 to 1 transit ion) by t he
processor (the m ajor differ ence betw een GTL+ and AGTL+ ).
These signals do not have set up or hold tim e specificat ions in
relat ion to BCLK[ 1: 0] , and are therefore referred t o as
“Asynchronous GTL+ Signals”. However, all of t he Asynchronous
GTL+ signals are required t o be assert ed for at least t wo BCLKs
in order for t he processor t o r ecognize t hem .
Bus Agen t A com ponent or gr oup of com ponents t hat , when com bined,
represent a single load on t he AGTL+ bus.
Cr osst a lk The r ecept ion on a vict im net work of a signal im posed by
aggr essor net wor k( s) t hr ou gh induct ive and cap acit iv e coupling
bet ween t he net works.
• Backward Crosst alk - Coupling that creat es a signal in a
vict im net wor k t hat t rav els in t he opposit e dir ect ion as t he
aggressor’s signal.
• Forward Crosstalk - Coupling that cr eates a signal in a
vict im net wor k t hat t rav els in t he sam e dir ect ion as t he
aggressor’s signal.
• Even Mode Crosst alk - Coupling from a signal or m ultiple
aggressors when all t he aggressors swit ch in the sam e
direct ion t hat t he vict im is switching.
• Odd Mode Crosstalk - Coupling from a signal or m ult iple
aggressors when all t he aggressors switch in t he opposite
direct ion t hat t he vict im is switching.
Flight Tim e Flight t im e is a ter m in t he t im ing equat ion t hat includes t he
signal propagation delay, any effect s the syst em has on t he TCO
of t he driv er, plu s any adj ust m en t s t o t he signal at t he r eceiv er

I n t e l®9 4 5 GM E Ex pr e ss Ch ip se t —Abo ut T his M a nu a l
I nt el®CoreTM 2 Duo processor wit h t he Mobile I nt el®945GME Express Chipset
Manual May 2007
10 Ord er Num ber : 3 174 43 - 00 1US
needed t o ensure the setup t im e of t he receiver. More precisely,
flight t im e is defined as:
• The tim e difference bet ween a signal at t he input pin of a
r eceiv ing agent cr ossing t he sw it ching v olt age ( adj ust ed t o
m eet t he receiver m anufacturer ’s conditions r equired for
AC tim ing specifications; i.e., ringback, et c.) and t he out put
pin of the driving agent crossing t he switching voltage
when t he driver is driving a test load used t o specify t he
dr iver ’s AC t im ings.
• Maxim um and Minim um Flight Tim e - Flight t im e variations
are caused by m any different param et ers. The m or e
obvious causes include variation of t he board dielect ric
const ant, changes in load condition, crosstalk, power noise,
variat ion in ter m inat ion resistance, and differences in I / O
buffer per for m ance as a funct ion of t em perat ure, voltage,
and m anufact uring process. Som e less obvious causes
include effect s of Sim ult aneous Swit ching Out pu t ( SSO)
and packaging effect s.
• Maxim um flight t im e is the largest accept able flight t im e a
netw ork will experience under all conditions.
• Minim um flight t im e is t he sm allest accept able flight t im e a
netw ork will experience under all conditions.
I n fr a re d D a t a Assoc. The I nfrared Data Associat ion ( I rDA) has outlined a specification
for ser ial com m unicat ion bet ween t wo dev ices via a bi-
directional infrared dat a port . The 945GME plat form has such a
port and it is locat ed on t he rear of the plat form between t he t wo
USB connect ors.
I MVP6 The I nt el Mobile Volt age Posit ioning specification for t he I nt el®
Cor e™ 2 Duo Pr ocessor. I t is a DC- DC conv er t er m odule t hat
supplies t he required volt age and current to a single processor.
I n t e r- Sym bol I n t e rfe r en ce
I n t er - sy m bol in t er ference is t he ef fect of a pr ev ious sign al ( or
t ransit ion) on t he int erconnect delay. For exam ple, w hen a
signal is transm itted down a line and t he reflect ions due to t he
t ransit ion have not com plet ely dissipat ed, t he following dat a
t ransition launched ont o t he bus is affect ed. I SI is dependent
upon frequency, t im e delay of t he line, and t he reflect ion
coefficient at t he driver and receiver. I SI m ay im pact bot h t im ing
and signal integrit y.
Media Ex pa nsion Car d
The Media Expansion Card ( MEC) pr ov ides digit al display opt ions
through t he SDVO interface. The MEC card also incorporat es
video- in .
N e t w or k The net w or k is t he t race of a Print ed Circuit Boar d ( PCB) t hat
com pletes an elect rical connect ion bet ween t wo or m ore
com ponent s.
Over shoot The m axim um volt age observed for a signal at the device pad,
m easur ed w it h r espect t o VCC.
Pa d The elect rical cont act point of a sem iconduct or die t o t he
package subst rat e. A pad is only observable in sim ulat ions.
Pin The contact point of a com ponent package t o the t races on a
su bst r at e, such as t he m ot her board. Signal qualit y and t im in gs
m ay be m easur ed at the pin.

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Pow er - Good “ Pow er - Good,” “ PWRGOOD,” or “ CPUPWRGOOD” ( an act ive h igh
signal) indicat es t h at all of t he sy st em pow er supplies and clock s
are st able. PWRGOOD should go act ive a predet erm ined t im e
after syst em voltages are st able and should go inact ive as soon
as any of these volt ages fail their specificat ions.
Ringback The voltage to which a signal changes aft er reaching it s
m axim um absolut e value. Ringback m ay be caused by
reflections, driver oscillations, or ot her transm ission line
phenom ena.
Syst e m Bu s The Syst em Bus is t he m icroprocessor bus of t he processor.
Se t up W in dow The tim e betw een t he beginning of Set up t o Clock (TSU_MI N)
and t he ar rival of a v alid clock edge. This w indow m ay be
differ ent for each t ype of bus agent in t he syst em .
Sim u lt a n e ou s Sw it ch in g Ou t pu t
Sim ult aneous Sw it ch ing Out put ( SSO) effect s ar e differences in
electr ical t im ing param eter s and degradat ion in signal qualit y
caused by m ult iple signal out put s sim ult aneously switching
volt age levels in t he opposit e direction from a single signal or in
t he sam e direct ion. These are called odd m ode and ev en m ode
sw itching, respect ively. This sim ult aneous swit ching of m ult iple
output s creates higher current swings that m ay cause additional
pr opagat ion delay ( “ push- out ” ) or a decr ease in pr opagat ion
delay ( “ p ull- in” ) . Th ese SSO effect s m ay im pact t he set up and/
or hold tim es and are not always t aken int o account by
sim ulat ions. System tim ing budget s should include m argin for
SSO effect s.
St u b The branch from the bus trunk t erm inating at t he pad of an
agent .
Trunk The m ain connect ion, excluding int er connect branches, from
one end
Syst e m M a na ge m e nt Bus
A t wo- wire int erface t hrough which various system com ponent s
m ay com m unicat e.
Undersh oot The m inim um volt age ext ending below VSS obser ved for a
signal at the device pad.
VCC ( CPU core ) VCC (CPU core) is the core power for t he processor. The syst em
bus is t erm inat ed t o VCC ( CPU core) .
Vict im A netw ork that receives a coupled crosstalk signal from anot her
netw ork is called t he vict im net work.
Ta b l e 1 defines t he acronym s used t hr oughout this docum ent.
Table 1 . Acron ym s ( Sheet 1 of 3 )
Acr onym D e f in it io n
AC Audio Codec
ACPI Advanced Configu rat ion and Pow er I nterface
AGTL Assist ed Gunning Transceiver Logic
AMC Audio/ Modem Codec.
ASF Alert St andar d Form at
AMI Am er ican Megat r en ds I n c. ( BI OS dev eloper )

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ATA Advanced Technology Attachm ent ( disk d riv e int er face)
ATX Advance Tech nology Ex t end ed ( m ot her boar d for m f act or )
BGA Ball Grid Array
BI OS Built- I n Self Test
CK-SSCD Spread Spectrum Differential Clock
CMC Com m on Mode Choke
CMOS Configurat ion Mem ory Operating Sy st em
CPU Cen t ral Processing Un it ( pr ocessor )
DDR Double Data Rat e
DMI Direct Mem ory I n ter face
ECC Error Cor recting Code
EEPROM Elect rically Erasable Progr am m able Read- Only Mem ory
EHCI Enh anced Host Cont r oller I nt er face
EMA Extended Media Access
EMI Elect ro Magnet ic I nt erferen ce
ESD Elect rost at ic Discharge
EV Engineering Validation
EVMC Elect rical Validation Margining Card
FI FO First I n First Out - describes a t ype of buffer
FS Full- speed. Refer s t o USB
FSB Front Side Bus
FWH Fir m ware Hub
GMCH Graphics Mem or y Cont roller Hub
HS High - speed. Refer s t o USB
I CH I / O Cont roller Hub
I DE I nt eg rated Dr iv e Elect ronics
I MVP I ntel Mobile Voltage Positioning
I P/ I Pv6 I nt er net Prot ocol/ I nternet Prot ocol ver sion 6
I rDA I nfrared Dat a Associat ion
I SI I nt er -Sy m bol I nt erferen ce
KBC Keyboard Cont roller
LAI Logic Analyzer I n ter face
LAN Local Area Net work
LED Light Em it t in g Diode
LOM LAN on Mot her board
LPC Low Pin Count
LS Low - speed . Refer s t o USB
LVD S Low Volt age Different ial Signalling
MC Modem Codec
MEC Media Expansion Card
Table 1 . Acron ym s ( Sh eet 2 of 3 )
Acr onym D e f in it io n

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MHz Mega- Her t z
OEM Original Equipm ent Manufactur er
PCI e PCI Express*
PCM Pulse Code Modulat ion
POST Pow e r On Sel f Test
PLC Plat form LAN Connect
RAI D Redundant Array of I nexpensiv e Disks
RTC Real Tim e Clock
SATA Serial ATA
SI O Super I nput / Out put
SMBus Syst em Managem ent Bu s
SODI MM Sm all Out line Dual I n- line Mem ory Module
SPD Serial Presence Det ect
SPI Serial Peripheral I nterface
SSO Sim ult aneous Swit ching Out put
STR Suspend To RAM
TCO Total Cost of Ow nership
TCP Transm ission Cont rol Protocol
TDM Tim e Division Mult iplexed
TDR Tim e Dom ain Ref lect om etry
µBGA Micro Ball Grid Array
UDP User Datagram Prot ocol
UHCI Univer sal Host Cont roller I nt erface
USB Univer sal Serial Bus
VGA Video Graphics Adapter
VI D Volt age I den tificat ion
VREG Voltage Regulator
XDP eXt ended Debug Por t
Table 1 . Acron ym s ( Sheet 3 of 3 )
Acr onym D e f in it io n

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1 .4 Su ppor t Op t ions
1 .4 .1 Elect ronic Su pport Sy st em s
I ntel’s web site ( ht t p: / / www.int el.com / ) prov ides u p- t o- dat e t ech nical in for m at ion and
product support . This inform ation is available 24 hours per day, 7 days per week,
providing technical inform at ion w henever you need it .
Product docum ent at ion is provided online in a v ar iet y of w eb- frien dly for m at s at :
htt p: / / www 3.hibbert group.com / int el/ m ain
1 .4 .2 Addit iona l Tech nical Support
I f you require additional technical support , please cont act your I nt el Representative or
local dist ribut or.
1 .5 Pr oduct Lit e ra t ure
You can order product lit erat ure from t he following I ntel literat ure centers:
Ta ble 2 . I n t e l Lit e r at u r e Ce n t er s
Lo ca t ion Te le ph o ne N u m b er
U. S. and Canad a 1- 8 00 - 548 - 47 25
U. S. ( fr om over seas) 70 8- 2 96- 9 33 3
Europ e ( U.K. ) 44 ( 0) 1 793 - 43 115 5
Germ any 44 ( 0) 1 793 - 42 133 3
Fr an ce 44 ( 0) 1 793 - 42 177 7
Japan ( f ax on ly ) 81 ( 0) 1 20- 4 7- 8 8- 32

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1 .6 Re la t e d D ocu m en t s
The table below provides a sum m ary of publicly available docum ent s relat ed t o t his
developm ent kit . For addit ional docum ent at ion, please cont act your I ntel
Representative.
Ta ble 3 . Re la t e d D ocu m e nt s
D ocu m e n t Tit le Lo ca t ion
Mobile I nt el® 9 45 Expr ess Chipset Fam ily Datasheet ht tp: / / w ww. intel.com / design/ m obile/ datasht s/
309219.htm
I nt el® I / O Cont roller Hub 7 ( I CH7) Fam ily Dat asheet ht t p: / / w ww.intel.com / design/ chipsets/ dat ashts/
307013.htm
Mobile I nt el® 9 45 Express Chipset Fam ily Specificat ion
Updat e
ht t p: / / w ww.intel.com / design/ m obile/ specupdt/
309220.htm
I nt el® Centrino® Duo Processor Tech nology Design
Guide Order Nu m ber 6 549 381
N ot e :
1. Cont act you r I nt el r epr esent at ive for access t o t his docum ent .

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2 .0 Get t ing St a rt e d
This chapt er identifies the evaluat ion kit ’s key com ponent s, feat ures and specifications.
I t also details basic board set up and operat ion.
2 .1 Over view
The evaluat ion board consist s of a baseboard populated wit h t he I nt el®CoreTM 2 Duo
pr ocessor and t he I nt el®9 45 GME Expr ess Chipset , ot her sy st em board com ponent s,
and peripheral connectors.
Note: The evaluation board is shipped as an open sy st em allowing for m axim um flexibility in
changing hardware configuration and peripherals. Since t he board is not in a protect ive
chassis, t ake extra precaut ion w hen handling and operating t he system .
2 .1 .1 I ntel®9 4 5 GME Express Chipset Deve lopm ent Kit
Fe a t ur es
Feat ures of t he developm ent kit board ar e sum m ar ized below:
Pr ocessor
• Intel
®Cor eTM 2 Duo processor with 4 MByte L2 Cache on 65nm process in t he
478 pin Flip Chip Pin Grid Ar ray ( Micr o- FCPGA) package
M ob ile I n t el®9 4 5 GM E Ex pr ess Gr aphics M em or y Co nt r olle r H u b ( 9 4 5 GM E
Ex press GMCH)
• 1466 pin Micr o- FCBGA Package
• Support s a 533/ 667 MHz front side bus
• Support s dual- Channel DDR2 at 400/ 533/ 667 MHz
• Tw o SODI MM slot s ( on e per channel) suppor t DDR2 SODI MMS ( unbuffered, n on -
ECC) m odules
• Support s 128 MBytes to 4 GBytes using 256 Mbit , 512 Mbit , or 1 Gbit t echnology
• x 16 PCI Ex pr ess* Graphics or Ser ial Digit al Video Out ( SDVO) port
• 18 b pp LVDS, VGA & TV- D connect or suppor t
I / O Cont r oller Hu b 7 ( I CH 7 - M )
• 652 pin plastic BGA package
• DMI ( x4) interface wit h GMCH
• Tw o SATA and one I DE ( 4 0 pin) Har d Dr ive int erface
• Two PCI 2.3 com pliant deskt op slot s
• 82802AC8 Fir m war e Hub ( FWH)
• 82573E Gigabit Ethernet Cont roller

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• Two x1 PCI Express* slot s.
Note: There are actually three x1 PCI Express* slots but slot 2 was used for validat ion
purposes. Only slot s 0 and 1 are support ed.
Clock in g
• CK- 410M an d CK-SSCD
• Bat t er y- back ed r eal t im e clock
Con ne ct or I n t er fa ce Sum m a r y
• One x16 PCI Expr ess* Video I nter face, doubles as an MEC connect or to provide
access to dual SDVO port s if PCI Express* is unused
• TwoSATAports
• One Ult ra ATA ( 33/ 66/ 100) I DE connect or supporting up t o t wo I DE devices
• Eight Un iversal Ser ial Bu s ( USB) 2.0 por t s ( Five por t s pr ov ided on r ear - pan el, t hree
pr ov ided via headers ( J6H2, J7E2)
• Two PCI 2.3 com pliant 33 MHz int erface connect ors
• PS/ 2- st y le k ey board and PS/ 2 m ou se ( 6 - pin m ini- DI N) con nect ors
• TV Ou t D- connect or at back panel in t er face
• LVDS connect or on t op of cir cuit boar d near GMCH ( J5F1)
• One VGA connect or prov ides access t o int egrat ed graph ics
• One LAN connect or providing 10/ 100/ 1000 Mbps connect ivity from the I nt el
82573E Gigabit Ethernet Cont roller
• One 9 - pin ser ial port connect or.
• OneIrDAport(U4A1)
• Tw o PCI Ex pr ess* slot s ( x 1)
• Two SODI MM connect ors on rear side of circuit board
D e bu g Fe a t u r e s
• Ex t ended Debug Por t ( XDP) connect or
• On- board Por t 80h display
M isce lla ne ou s Fe a t ur e s
• Configurable for ATX 1.1 Power Supply in deskt op m ode or AC Mobile Brick/ Battery
Pack for Mobile Mode
• ATX Form Factor eight layer PCB
• AMI * system BI OS
• Tw o bu ilt - in fan pow er connect or s: Chassis Fan and CPU Fan
• Power/ Reset but tons
• CMOS clear j um per
• BI OS r ecov er y j u m per
• Boot Block prot ect ion j u m per
• Support for Serial, I rDA, serial m ouse, and keyboard

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2 .2 I nclude d H ar dw are a nd D ocu m en t at ion
The following hardware and docum ent at ion is included in the developm ent k it:
• OneIntel
®945GME Express Chipset Developm ent Kit board
• OneIntel
®Cor eTM 2 Duo pr ocessor with 4 MB L2 Cache on 65nm process in the
478 pin Flip- Chip Pin Gr id Ar ray ( Micro- FCPGA) pack age ( I nst alled)
• OneIntel
®Cor eTM Duo processor wit h 2 MByte L2 Cache on 65 nm process in t he
478 pin Flip Chip Pin Gr id Ar ray ( Micr o- FCPGA) pack ag e ( inclu ded in k it box for
evaluat ion– not populated on board)
• On e Fir m ware Hub ( FWH) ( I nst alled)
• On e GMCH ( 945GME) heat sink ( I n st alled)
• On e Ty pe 2032, socket ed 3 V lit hium coin cell bat t ery ( I n st alled )
• On e DDR2 SODI MM ( 2 00 Pin)
• One CPU t herm al solut ion and CPU back plate (included in kit box – not populat ed
on board)
• One hard drive
• Onecablekit
2 .3 Soft w a r e Ke y Fe at ur es
The driver CD included in t he kit cont ains all of t he software drivers necessary for basic
syst em functionalit y under t he following operat ing system s: Windows* 2000/ XP/ XP
Em bedded, and Linux* .
Note: While every care was taken t o ensure the latest versions of drivers were provided on
t he enclosed CD at t im e of publication, newer revisions m ay be available. Updat ed
dr ivers for I nt el com ponent s can be found at : http: / / developer.intel.com / design/
int arch/ soft ware/ index.htm
For all t hird- par t y com ponent s, please cont act t he appr opriat e vendor f or u pdat ed
drivers.
Note: Software in t he kit is provided free by t he vendor and is only licensed for evaluat ion
purposes. Refer t o t he docum ent ation in your evaluat ion kit for further det ails on any
ter m s and conditions that m ay be applicable t o t he granted licenses. Custom ers using
t he t ools t hat wor k with Microsoft * product s m ust license t hose product s. Any t arget s
cr eat ed by t hose t ools sh ould also h av e appr opriate licenses. Soft ware included in t he
kit is subj ect t o ch an ge.
Refer t o ht tp: / / developer.intel.com / design/ int arch/ devkits for details on additional
soft w ar e f rom ot her t hird- par t y v en dor s.
2 .3 .1 AMI * BI OS
This developm en t k it ships p re- inst alled w it h AMI * BI OS pre- boot fir m ware fr om AMI * .
AMI * BI OS provides an indust ry- st andard BI OS plat form t o run m ost st andar d
operating system s, including Windows* 2000/ XP/ XP Em bedded, Linux* , and others.
The AMI * BI OS Applicat ion Kit ( available t hrough AMI * ) includes com plet e source code,
a reference m anual, and a Windows- b ased ex pert sy st em , BI OSt art * , t o en able easy
and rapid configuration of cust om ized fir m war e for your I nt el®945GME Express
Chipset .

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The following feat ures of AMI * BI OS are enabled in t he I nt el®945GME Expr ess
Chipset:
• DDR2 SDRAM det ection, configuration, and init ializat ion
• Intel
®945GME Express Chipset configuration
• POST codes displayed t o port 80h
• PCI / PCI Express* dev ice enum erat ion and configurat ion
• I nt egrat ed video configurat ion and init ialization
• Super I / O configurat ion
• CPU m icrocode updat e
• Act ive Managem ent Technology
• RAI D 0/ 1 Support
2 .4 Be fore You Begin
Addit ional har dware m ay be necessar y t o successfully set up and operat e t he
evaluat ion board.
V GA M on it or: Any st andard VGA or m ult i- r esolut ion m onitor m ay be used. The set up
inst ructions in t his chapter assum e t he use of a standard VGA m onitor, TV, or flat panel
m onit or.
Keyboard: The evaluat ion board can support either a PS/ 2 or USB style keyboar d.
Mouse : The evaluation boar d can support eit her a PS/ 2 or USB sty le m ouse.
H a rd D r iv e s a n d Opt ica l D isc D r iv es: Up to t wo SATA drives and t wo I DE devices
( m ast er and slave) m ay be connect ed t o t he evaluation board. An opt ical disc dr ive
m ay be used t o load t he OS. All t hese storage devices m ay be at tached t o t he board
sim ultaneously.
Vide o Ada pt e r: I nt egrat ed video is provided on t he back panel of the evaluat ion
board. Alt ernately, a st andard PCI Express* video adapter or an MEC video adapt er
m ay be used for addit ional display flexibilit y. Please cont act t he respect ive vendors for
drivers and necessary soft ware for adapt ers not pr ovided wit h t his developm ent k it.
Check t he BI OS for t he proper video sett ings. See Sect ion 2.6, “ Configuring the BI OS”
on page 21 for m or e infor m at ion.
Note: The enclosed dr iver CD includes driver s necessary for LAN, I nt egrat ed graphics, and
syst em I NF ut ilit ies.
N e t w or k Ad a pt e r : A Gigabit net work int erface is provided on t he evaluat ion board.
The network interface will not be operat ional unt il after all the necessary drivers have
been inst alled. A st andard PCI / PCI Express* adapt er m ay be u sed in conj unct ion w it h ,
or in place of, t he onboard net work adapter. Please contact the respective vendors for
dr ivers and necessary software for adapt ers not pr ovided wit h t his developm ent k it.
You m ust supply appropriat e network cables t o ut ilize t he LAN connector or any other
inst alled netw ork cards.
Pow e r Su pply: The I ntel®9 4 5 GM E Expre ss Chipset has t he opt ion to be power ed
from t wo different power sources: an ATX power supply, or ‘Mobile Brick’. The I ntel®
9 4 5 GME Ex pr ess Chipset contains all of the voltage regulators necessary to power
t he syst em .

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There are two m ain support ed power supply configurations, Deskt op and Mobile. The
Desktop solut ion consists of only using t he ATX power supply. The Mobile solution
consists of only using the AC Brick.
Note: Desk t op per ipherals, in cluding add - in cards, will not work in m obile power m ode. I f
deskt op peripherals are used, t he plat form m ust be pow ered using desktop power
m ode. The AC Brick power supply configurat ion does not pr ov ide t he 12 V supply
required by m ost deskt op peripherals.
Note: Select a power supply t hat com plies w ith t he "ATX12V" 1. 1 specificat ion. For m ore
inform at ion, refer t o http: / / www.form factors.org.
Note: I f the power but t on on the ATX power supply is used t o shut down t he syst em , wait at
least five seconds before t urning t he sy stem on again t o avoid dam aging t he sy stem .
Ot he r D e vice s a n d Ad a pt e r s: The evaluat ion board funct ions m uch like a st andar d
deskt op com puter m other board. Most PC- com pat ible peripherals can be at t ached and
configured to work with t he evaluat ion board.
2 .5 Se t t ing Up t h e Eva lua t ion Boa r d
Once t he necessar y h ar dw are ( described in Section 2.4) has been gathered, follow the
st eps below t o set up t he I ntel®945GME Expr ess Chipset evaluation board.
Note: To locat e it em s discussed in t he procedure below, please refer to Sect ion 4.0.
1. Creat e a safe wor k env ironm ent .
Ensu re a st at ic- f ree w or k env ironm en t befor e r em oving any com ponent s fr om t heir
ant i- st at ic pack aging. Th e evalu at ion b oard is suscept ible to elect rostatic discharge
( ESD) dam age, an d such dam age m ay cause product failure or unpredictable
operation. A flam e ret ardant w or k surface m ust also be used.
Ca ut ion : Be ca u se o f t h is su sce pt ibilit y, it is r e com m e nde d t h a t a n ESD w r ist st r a p be
u se d w h en h an dling t h e b oa r d.
2. I nspect the cont ent s of your kit.
Check for dam age t hat m ay have occurr ed du ring shipm ent . Cont act your sales
represent at ive if any it em s ar e m issing or dam aged.
Ca ut ion : Sin ce t h e boa r d is n ot in a p rot e ct iv e cha ssis, u se ca ut ion w h e n con ne ct in g
ca ble s t o t h is p rodu ct .
Ca ut ion : St a nd by v olt a g e is con st a n t ly a pplie d t o t h e b oa r d. Th er ef or e , do n ot inse rt or
re m ove a ny hardw a re unless t h e sy st em is u n plu gg ed.
Note: The evaluat ion board is a st andard ATX form factor. An ATX chassis m ay be used if a
protect ed environm ent is desired. I f a chassis is not used, standoffs m ust be used to
elevat e the board off t he working surface t o prot ect t he m em or y and t o prot ect from
any accident al cont act t o m et al obj ect s.
3. Check t he j um per default posit ion set t in g. Ref er t o Figure 4 for j um per locat ion.
Jum per J6H1 is used t o clear t he CMOS m em ory. Make sure this j um per is set for
norm al operat ion.
4. Be sure to populat e the following hardware on your evaluation board:
—OneIntel
®Cor eTM 2 Duo processor
— One pr ocessor t herm al solut ion
— On e DDR2 SODI MM ( 2 00 - pin)