IXYS zilog Z8051 Series User manual

PS029902-0212
PRELIMINARY
Copyright ©2012 Zilog®, Inc. All rights reserved.
www.zilog.com
Product Specification
Z8051 Series 8-Bit Microcontrollers
Z51F3220

PS029902-0212 P R E L I M I N A R Y
Z51F3220
Product Specification
ii
DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS.
LIFE SUPPORT POLICY
ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A criti-
cal component is any component in a life support device or system whose failure to perform can be reason-
ably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
Document Disclaimer
©2012 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications,
or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES
NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE
INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO
DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED
IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED
HEREIN OR OTHERWISE. The information contained within this document has been verified according
to the general principles of electrical and mechanical engineering.
Z8051 is a trademark or registered trademark of Zilog, Inc. All other product or service names are the
property of their respective owners.
Warning:

PS029902-0212 P R E L I M I N A R Y Revision History
Z51F3220
Product Specification
iii
Revision History
Each instance in this document’s revision history reflects a change from its previous edi-
tion. For more details, refer to the corresponding page(s) or appropriate links furnished in
the table below.
Date Revision Level Description Page
Feb
2012 02 Removed references to 28-pin SOP package. All
Jan
2012 01 Original Zilog issue. All

Z51F3220
Product Specification
PS029902-0212 P R E L I M I N A R Y 1
Table of Contents
1. Overview...............................................................................................................................................................10
1.1 Description.....................................................................................................................................................10
1.2 Features.........................................................................................................................................................11
1.3 Ordering Information......................................................................................................................................12
1.4 Development Tools........................................................................................................................................13
2. Block Diagram ......................................................................................................................................................16
3. Pin Assignment.....................................................................................................................................................17
4. Package Diagram.................................................................................................................................................19
5. Pin Description......................................................................................................................................................21
6. Port Structures......................................................................................................................................................26
6.1 General Purpose I/O Port..............................................................................................................................26
6.2 External Interrupt I/O Port..............................................................................................................................27
7. Electrical Characteristics......................................................................................................................................28
7.1 Absolute Maximum Ratings...........................................................................................................................28
7.2 Recommended Operating Conditions...........................................................................................................28
7.3 A/D Converter Characteristics.......................................................................................................................29
7.4 Power-On Reset Characteristics...................................................................................................................29
7.5 Low Voltage Reset and Low Voltage Indicator Characteristics....................................................................30
7.6 High Internal RC Oscillator Characteristics...................................................................................................31
7.7 Internal Watch-Dog Timer RC Oscillator Characteristics..............................................................................31
7.8 LCD Voltage Characteristics .........................................................................................................................32
7.9 DC Characteristics.........................................................................................................................................33
7.10 AC Characteristics.......................................................................................................................................35
7.11 SPI0/1/2 Characteristics..............................................................................................................................36
7.12 UART0/1 Characteristics.............................................................................................................................37
7.13 I2C0/1 Characteristics .................................................................................................................................38
7.14 Data Retention Voltage in Stop Mode.........................................................................................................39
7.15 Internal Flash Rom Characteristics.............................................................................................................40
7.16 Input/Output Capacitance............................................................................................................................40
7.17 Main Clock Oscillator Characteristics..........................................................................................................41
7.18 Sub Clock Oscillator Characteristics...........................................................................................................42
7.19 Main Oscillation Stabilization Characteristics .............................................................................................43
7.20 Sub Oscillation Characteristics....................................................................................................................43
7.21 Operating Voltage Range............................................................................................................................44
7.22 Recommended Circuit and Layout..............................................................................................................45
7.23 Typical Characteristics ................................................................................................................................46
8. Memory.................................................................................................................................................................49
8.1 Program Memory...........................................................................................................................................49
8.2 Data Memory .................................................................................................................................................51
8.3 XRAM Memory ..............................................................................................................................................53
8.4 SFR Map........................................................................................................................................................54
9. I/O Ports................................................................................................................................................................63
9.1 I/O Ports.........................................................................................................................................................63
9.2 Port Register..................................................................................................................................................63
9.3 P0 Port...........................................................................................................................................................65
9.4 P1 Port...........................................................................................................................................................67
9.5 P2 Port...........................................................................................................................................................69

Z51F3220
Product Specification
PS029902-0212 P R E L I M I N A R Y 2
9.6 P3 Port...........................................................................................................................................................70
9.7 P4 Port...........................................................................................................................................................71
9.8 P5 Port...........................................................................................................................................................72
9.9 Port Function..................................................................................................................................................73
10. Interrupt Controller..............................................................................................................................................82
10.1 Overview......................................................................................................................................................82
10.2 External Interrupt.........................................................................................................................................83
10.3 Block Diagram .............................................................................................................................................84
10.4 Interrupt Vector Table..................................................................................................................................85
10.5 Interrupt Sequence......................................................................................................................................85
10.6 Effective Timing after Controlling Interrupt Bit ............................................................................................87
10.7 Multi Interrupt...............................................................................................................................................88
10.8 Interrupt Enable Accept Timing...................................................................................................................89
10.9 Interrupt Service Routine Address ..............................................................................................................89
10.10 Saving/Restore General-Purpose Registers.............................................................................................89
10.11 Interrupt Timing..........................................................................................................................................90
10.12 Interrupt Register Overview.......................................................................................................................90
10.13 Interrupt Register Description....................................................................................................................92
11. Peripheral Hardware...........................................................................................................................................99
11.1 Clock Generator...........................................................................................................................................99
11.2 Basic Interval Timer...................................................................................................................................102
11.3 Watch Dog Timer.......................................................................................................................................105
11.4 Watch Timer...............................................................................................................................................108
11.5 Timer 0.......................................................................................................................................................111
11.6 Timer 1.......................................................................................................................................................120
11.7 Timer 2.......................................................................................................................................................130
11.8 Timer 3, 4...................................................................................................................................................141
11.9 Buzzer Driver.............................................................................................................................................170
11.10 SPI 2 ........................................................................................................................................................172
11.11 12-Bit A/D Converter ...............................................................................................................................178
11.12 USI0 (UART + SPI + I2C)........................................................................................................................185
11.13 USI1 (UART + SPI + I2C)........................................................................................................................222
11.15 LCD Driver...............................................................................................................................................260
12. Power Down Operation ....................................................................................................................................272
12.1 Overview....................................................................................................................................................272
12.2 Peripheral Operation in IDLE/STOP Mode ...............................................................................................272
12.3 IDLE Mode.................................................................................................................................................273
12.4 STOP Mode...............................................................................................................................................274
12.5 Release Operation of STOP Mode............................................................................................................275
13. RESET..............................................................................................................................................................277
13.1 Overview....................................................................................................................................................277
13.2 Reset Source.............................................................................................................................................277
13.3 RESET Block Diagram..............................................................................................................................277
13.4 RESET Noise Canceller............................................................................................................................278
13.5 Power on RESET.......................................................................................................................................278
13.6 External RESETB Input.............................................................................................................................281
13.7 Brown Out Detector Processor..................................................................................................................282
13.8 LVI Block Diagram.....................................................................................................................................283
14. On-chip Debug System ....................................................................................................................................287
14.1 Overview....................................................................................................................................................287
14.2 Two-Pin External Interface........................................................................................................................288
15. Flash Memory...................................................................................................................................................293

Z51F3220
Product Specification
PS029902-0212 P R E L I M I N A R Y 3
15.1 Overview....................................................................................................................................................293
16. Configure Option ..............................................................................................................................................304
16.1 Configure Option Control...........................................................................................................................304
17. APPENDIX........................................................................................................................................................305

Z51F3220
Product Specification
PS029902-0212 P R E L I M I N A R Y 4
List of Figures
Figure 1.4 StandAlone Gang8 (for Mass Production)...............................................................................15
Figure 2.1 Block Diagram ..........................................................................................................................16
Figure 3.1 Z51F3220 44MQFP-1010 Pin Assignment..............................................................................17
Figure 3.2 Z51F3220 32SOP Pin Assignment..........................................................................................18
Figure 4.1 44-Pin MQFP Package.............................................................................................................19
Figure 4.2 32-Pin SOP Package................................................................................................................20
Figure 6.1 General Purpose I/O Port.........................................................................................................26
Figure 6.2 External Interrupt I/O Port ........................................................................................................27
Figure 7.1 AC Timing.................................................................................................................................35
Figure 7.2 SPI0/1/2 Timing........................................................................................................................36
Figure 7.3 Waveform for UART0/1 Timing Characteristics.......................................................................37
Figure 7.4 Timing Waveform for the UART0/1 Module.............................................................................37
Figure 7.5 I2C0/1 Timing ...........................................................................................................................38
Figure 7.6 Stop Mode Release Timing when Initiated by an Interrupt......................................................39
Figure 7.7 Stop Mode Release Timing when Initiated by RESETB..........................................................39
Figure 7.8 Crystal/Ceramic Oscillator........................................................................................................41
Figure 7.9 External Clock...........................................................................................................................41
Figure 7.10 Crystal Oscillator ....................................................................................................................42
Figure 7.11 External Clock.........................................................................................................................42
Figure 7.12 Clock Timing Measurement at XIN ........................................................................................43
Figure 7.13 Clock Timing Measurement at SXIN......................................................................................43
Figure 7.14 Operating Voltage Range.......................................................................................................44
Figure 7.15 Recommended Circuit and Layout.........................................................................................45
Figure 7.16 RUN (IDD1 ) Current..............................................................................................................46
Figure 7.17 IDLE (IDD2) Current...............................................................................................................46
Figure 7.18 SUB RUN (IDD3) Current.......................................................................................................47
Figure 7.19 SUB IDLE (IDD4) Current ......................................................................................................47
Figure 7.20 STOP (IDD5) Current.............................................................................................................48
Figure 8.1 Program Memory......................................................................................................................50
Figure 8.2 Data Memory Map....................................................................................................................51
Figure 8.3 Lower 128 Bytes RAM..............................................................................................................52
Figure 8.4 XDATA Memory Area...............................................................................................................53
Figure 10.1 External Interrupt Description.................................................................................................83
Figure 10.2 Block Diagram of Interrupt......................................................................................................84
Figure 10.3 Interrupt Vector Address Table ..............................................................................................86
Figure 10.4 Effective Timing of Interrupt Enable Register .......................................................................87
Figure 10.5 Effective Timing of Interrupt Flag Register.............................................................................87
Figure 10.6 Effective Timing of Interrupt ...................................................................................................88
Figure 10.7 Interrupt Response Timing Diagram ......................................................................................89
Figure 10.8 Correspondence between Vector Table Address and the Entry Address of ISP..................89
Figure 10.9 Saving/Restore Process Diagram and Sample Source.........................................................89
Figure 10.10 Timing Chart of Interrupt Acceptance and Interrupt Return Instruction...............................90
Figure 11.1 Clock Generator Block Diagram.............................................................................................99
Figure 11.2 Basic Interval Timer Block Diagram.....................................................................................102

Z51F3220
Product Specification
PS029902-0212 P R E L I M I N A R Y 5
Figure 11.3 Watch Dog Timer Interrupt Timing Waveform .....................................................................105
Figure 11.4 Watch Dog Timer Block Diagram.........................................................................................106
Figure 11.5 Watch Timer Block Diagram.................................................................................................108
Figure 11.6 8-Bit Timer/Counter Mode for Timer 0 .................................................................................112
Figure 11.7 8-Bit Timer/Counter 0 Example............................................................................................112
Figure 11.8 8-Bit PWM Mode for Timer 0................................................................................................113
Figure 11.9 PWM Output Waveforms in PWM Mode for Timer 0...........................................................114
Figure 11.10 8-Bit Capture Mode for Timer 0..........................................................................................115
Figure 11.11 Input Capture Mode Operation for Timer 0........................................................................116
Figure 11.12 Express Timer Overflow in Capture Mode.........................................................................116
Figure 11.13 8-Bit Timer 0 Block Diagram ..............................................................................................117
Figure 11.14 16-Bit Timer/Counter Mode for Timer 1 .............................................................................121
Figure 11.15 16-Bit Timer/Counter 1 Example........................................................................................121
Figure 11.16 16-Bit Capture Mode for Timer 1........................................................................................122
Figure 11.17 Input Capture Mode Operation for Timer 1........................................................................123
Figure 11.18 Express Timer Overflow in Capture Mode.........................................................................123
Figure 11.19 16-Bit PPG Mode for Timer 1.............................................................................................124
Figure 11.20 16-Bit PPG Mode Timming chart for Timer 1.....................................................................125
Figure 11.21 16-Bit Timer/Counter Mode for Timer 1 and Block Diagram .............................................126
Figure 11.22 16-Bit Timer/Counter Mode for Timer 2 .............................................................................131
Figure 11.23 16-Bit Timer/Counter 2 Example........................................................................................132
Figure 11.24 16-Bit Capture Mode for Timer 2........................................................................................133
Figure 11.25 Input Capture Mode Operation for Timer 2........................................................................134
Figure 11.26 Express Timer Overflow in Capture Mode.........................................................................134
Figure 11.27 16-Bit PPG Mode for Timer 2.............................................................................................135
Figure 11.28 16-Bit PPG Mode Timming chart for Timer 2.....................................................................136
Figure 11.29 16-Bit Timer/Counter Mode for Timer 2 and Block Diagram .............................................137
Figure 11.30 8-Bit Timer/Counter Mode for Timer 3, 4 ...........................................................................142
Figure 11.31 16-Bit Timer/Counter Mode for Timer 3 .............................................................................143
Figure 11.32 8-Bit Capture Mode for Timer 3, 4.....................................................................................145
Figure 11.33 16-Bit Capture Mode for Timer 3.......................................................................................146
Figure 11.34 10-Bit PWM Mode (Force 6-ch) ........................................................................................148
Figure 11.35 10-Bit PWM Mode (Force All-ch) ......................................................................................149
Figure 11.36 Example of PWM at 4 MHz...............................................................................................150
Figure 11.37 Example of Changing the Period in Absolute Duty Cycle at 4 MHz..................................150
Figure 11.38 Example of PWM Output Waveform..................................................................................151
Figure 11.39 Example of PWM waveform in Back-to-Back mode at 4 MHz ..........................................151
Figure 11.40 Example of Phase Correction and Frequency correction of PWM....................................152
Figure 11.41 Example of PWM External Synchronization with BLNK Input...........................................152
Figure 11.42 Example of Force Drive All Channel with A-ch..................................................................153
Figure 11.43 Example of Force Drive 6-ch Mode....................................................................................154
Figure 11.44 Example of PWM Delay .....................................................................................................157
Figure 11.45 Two 8-Bit Timer 3, 4 Block Diagram ..................................................................................157
Figure 11.46 16-Bit Timer 3 Block Diagram ............................................................................................158
Figure 11.47 10-Bit PWM Timer 4 Block Diagram .................................................................................158
Figure 11.48 Buzzer Driver Block Diagram.............................................................................................170
Figure 11.49 SPI 2 Block Diagram ..........................................................................................................172
Figure 11.50 SPI 2 Transmit/Receive Timing Diagram at CPHA = 0 .....................................................174
Figure 11.51 SPI 2 Transmit/Receive Timing Diagram at CPHA = 1 .....................................................174

Z51F3220
Product Specification
PS029902-0212 P R E L I M I N A R Y 6
Figure 11.52 12-bit ADC Block Diagram .................................................................................................179
Figure 11.53 A/D Analog Input Pin with Capacitor..................................................................................179
Figure 11.54 A/D Power (AVREF) Pin with Capacitor ............................................................................179
Figure 11.55 ADC Operation for Align Bit................................................................................................180
Figure 11.56 A/D Converter Operation Flow...........................................................................................182
Figure 11.57 USI0 UART Block Diagram................................................................................................187
Figure 11.58 Clock Generation Block Diagram (USI0) ...........................................................................188
Figure 11.59 Synchronous Mode SCK0 Timing (USI0) ..........................................................................189
Figure 11.60 Frame Format (USI0) .........................................................................................................190
Figure 11.61 Asynchronous Start Bit Sampling (USI0)...........................................................................194
Figure 11.62 Asynchronous Sampling of Data and Parity Bit (USI0) .....................................................194
Figure 11.63 Stop Bit Sampling and Next Start Bit Sampling (USI0) .....................................................195
Figure 11.64 USI0 SPI Clock Formats when CPHA0=0 .........................................................................197
Figure 11.65 USI0 SPI Clock Formats when CPHA0=1 .........................................................................198
Figure 11.66 USI0 SPI Block Diagram....................................................................................................199
Figure 11.67 Bit Transfer on the I2C-Bus (USI0)....................................................................................200
Figure 11.68 START and STOP Condition (USI0)..................................................................................201
Figure 11.69 Data Transfer on the I2C-Bus (USI0).................................................................................201
Figure 11.70 Acknowledge on the I2C-Bus (USI0) .................................................................................202
Figure 11.71 Clock Synchronization during Arbitration Procedure (USI0)..............................................203
Figure 11.72 Arbitration Procedure of Two Masters (USI0)....................................................................203
Figure 11.73 Formats and States in the Master Transmitter Mode (USI0).............................................205
Figure 11.74 Formats and States in the Master Receiver Mode (USI0).................................................207
Figure 11.75 Formats and States in the Slave Transmitter Mode (USI0)...............................................209
Figure 11.76 Formats and States in the Slave Receiver Mode (USI0)...................................................211
Figure 11.77 USI0 I2C Block Diagram ....................................................................................................212
Figure 11.78 USI1 UART Block Diagram................................................................................................224
Figure 11.79 Clock Generation Block Diagram (USI1) ...........................................................................225
Figure 11.80 Synchronous Mode SCK1 Timing (USI1) ..........................................................................226
Figure 11.81 Frame Format (USI1) .........................................................................................................227
Figure 11.82 Asynchronous Start Bit Sampling (USI1)...........................................................................231
Figure 11.83 Asynchronous Sampling of Data and Parity Bit (USI1) .....................................................231
Figure 11.84 Stop Bit Sampling and Next Start Bit Sampling (USI1) .....................................................232
Figure 11.85 USI1 SPI Clock Formats when CPHA1=0 .........................................................................234
Figure 11.86 USI1 SPI Clock Formats when CPHA1=1 .........................................................................235
Figure 11.87 USI1 SPI Block Diagram....................................................................................................236
Figure 11.88 Bit Transfer on the I2C-Bus (USI1)....................................................................................237
Figure 11.89 START and STOP Condition (USI1)..................................................................................238
Figure 11.90 Data Transfer on the I2C-Bus (USI1).................................................................................238
Figure 11.91 Acknowledge on the I2C-Bus (USI1) .................................................................................239
Figure 11.92 Clock Synchronization during Arbitration Procedure (USI1)..............................................240
Figure 11.93 Arbitration Procedure of Two Masters (USI1)....................................................................240
Figure 11.94 Formats and States in the Master Transmitter Mode (USI1).............................................242
Figure 11.95 Formats and States in the Master Receiver Mode (USI1).................................................244
Figure 11.96 Formats and States in the Slave Transmitter Mode (USI1)...............................................246
Figure 11.97 Formats and States in the Slave Receiver Mode (USI1)...................................................248
Figure 11.98 USI1 I2C Block Diagram ....................................................................................................249
Figure 11.99 LCD Circuit Block Diagram.................................................................................................261
Figure 11.100 LCD Signal Waveforms (1/2Duty, 1/2Bias)......................................................................262

Z51F3220
Product Specification
PS029902-0212 P R E L I M I N A R Y 7
Figure 11.101 LCD Signal Waveforms (1/3Duty, 1/3Bias)......................................................................263
Figure 11.102 LCD Signal Waveforms (1/4Duty, 1/3Bias)......................................................................264
Figure 11.103 LCD Signal Waveforms (1/8Duty, 1/4Bias)......................................................................265
Figure 11.104 Internal Resistor Bias Connection....................................................................................266
Figure 11.105 External Resistor Bias Connection...................................................................................267
Figure 11.106 LCD Circuit Block Diagram...............................................................................................268
Figure 12.1 IDLE Mode Release Timing by External Interrupt ...............................................................273
Figure 12.2 STOP Mode Release Timing by External Interrupt..............................................................274
Figure 12.3 STOP Mode Release Flow...................................................................................................275
Figure 13.1 RESET Block Diagram.........................................................................................................277
Figure 13.2 Reset noise canceller timer diagram....................................................................................278
Figure 13.3 Fast VDD Rising Time..........................................................................................................278
Figure 13.4 Internal RESET Release Timing On Power-Up...................................................................278
Figure 13.5 Configuration Timing when Power-on..................................................................................279
Figure 13.6 Boot Process WaveForm .....................................................................................................279
Figure 13.7 Timing Diagram after RESET...............................................................................................281
Figure 13.8 Oscillator generating waveform example.............................................................................281
Figure 13.9 Block Diagram of BOD .........................................................................................................282
Figure 13.10 Internal Reset at the power fail situation............................................................................282
Figure 13.11 Configuration timing when BOD RESET............................................................................283
Figure 13.12 LVI Diagram........................................................................................................................283
Figure 14.1 Block Diagram of On-Chip Debug System...........................................................................288
Figure 14.2 10-bit Transmission Packet..................................................................................................288
Figure 14.3 Data Transfer on the Twin Bus ............................................................................................289
Figure 14.4 Bit Transfer on the Serial Bus ..............................................................................................289
Figure 14.5 Start and Stop Condition......................................................................................................290
Figure 14.6 Acknowledge on the Serial Bus ...........................................................................................290
Figure 14.7 Clock Synchronization during Wait Procedure ....................................................................291
Figure 14.8 Connection of Transmission.................................................................................................292
Figure 15.1 Flash Program ROM Structure.............................................................................................294

Z51F3220
Product Specification
PS029902-0212 P R E L I M I N A R Y 8
List of Tables
Table 1-1 Ordering Information of Z51F3220............................................................................................12
Table 5-1 Normal Pin Description..............................................................................................................21
Table 7-1 Absolute Maximum Ratings.......................................................................................................28
Table 7-2 Recommended Operating Conditions.......................................................................................28
Table 7-3 A/D Converter Characteristics...................................................................................................29
Table 7-4 Power-on Reset Characteristics................................................................................................29
Table 7-5 LVR and LVI Characteristics.....................................................................................................30
Table 7-6 High Internal RC Oscillator Characteristics...............................................................................31
Table 7-7 Internal WDTRC Oscillator Characteristics...............................................................................31
Table 7-8 LCD Voltage Characteristics.....................................................................................................32
Table 7-9 DC Characteristics.....................................................................................................................33
Table 7-10 AC Characteristics...................................................................................................................35
Table 7-11 SPI0/1/2 Characteristics..........................................................................................................36
Table 7-12 UART0/1 Characteristics.........................................................................................................37
Table 7-13 I2C0/1 Characteristics.............................................................................................................38
Table 7-14 Data Retention Voltage in Stop Mode.....................................................................................39
Table 7-15 Internal Flash Rom Characteristics.........................................................................................40
Table 7-16 Input/Output Capacitance........................................................................................................40
Table 7-17 Main Clock Oscillator Characteristics......................................................................................41
Table 7-18 Sub Clock Oscillator Characteristics.......................................................................................42
Table 7-19 Main Oscillation Stabilization Characteristics .........................................................................43
Table 7-20 Sub Oscillation Stabilization Characteristics...........................................................................43
Table 8-1 SFR Map Summary...................................................................................................................54
Table 8-2 SFR Map Summary...................................................................................................................55
Table 8-3 SFR Map....................................................................................................................................56
Table 9-1 Port Register Map......................................................................................................................64
Table 10-1 Interrupt Group Priority Level..................................................................................................82
Table 10-2 Interrupt Vector Address Table ...............................................................................................85
Table 10-3 Interrupt Register Map.............................................................................................................92
Table 11-1 Clock Generator Register Map..............................................................................................100
Table 11-2 Basic Interval Timer Register Map........................................................................................103
Table 11-3 Watch Dog Timer Register Map............................................................................................106
Table 11-4 Watch Timer Register Map....................................................................................................109
Table 11-5 Timer 0 Operating Modes......................................................................................................111
Table 11-6 Timer 0 Register Map............................................................................................................118
Table 11-7 Timer 1 Operating Modes......................................................................................................120
Table 11-8 Timer 2 Register Map............................................................................................................126
Table 11-9 Timer 2 Operating Modes......................................................................................................130
Table 11-10 Timer 3 Register Map..........................................................................................................137
Table 11-11 Timer 3, 4 Operating Modes................................................................................................141
Table 11-12 PWM Frequency vs. Resolution at 8 MHz..........................................................................147
Table 11-13 PWM Channel Polarity ........................................................................................................147
Table 11-14 Timer 3, 4 Register Map......................................................................................................159

Z51F3220
Product Specification
PS029902-0212 P R E L I M I N A R Y 9
Table 11-15 Buzzer Frequency at 8 MHz................................................................................................170
Table 11-16 Buzzer Driver Register Map................................................................................................171
Table 11-17 SPI 2 Register Map .............................................................................................................175
Table 11-18 ADC Register Map...............................................................................................................182
Table 11-19 Equations for Calculating USI0 Baud Rate Register Setting..............................................188
Table 11-20 CPOL0 Functionality............................................................................................................196
Table 11-21 USI0 Register Map ..............................................................................................................213
Table 11-22 Equations for Calculating USI1 Baud Rate Register Setting..............................................225
Table 11-23 CPOL1 Functionality............................................................................................................233
Table 11-24 USI1 Register Map ..............................................................................................................250
Table 11-25 Examples of USI0BD and USI1BD Settings for Commonly Used Oscillator Frequencies 259
Table 11-26 LCD Register Map...............................................................................................................268
Table 12-1 Peripheral Operation during Power Down Mode ..................................................................272
Table 12-2 Power Down Operation Register Map .................................................................................276
Table 13-1 Reset State............................................................................................................................277
Table 13-2 Boot Process Description......................................................................................................280
Table 13-3 Reset Operation Register Map..............................................................................................284
Table 15-1Flash Memory Register Map..................................................................................................295

Z51F3220
Product Specification
PS029902-0212 P R E L I M I N A R Y 10
Z51F3220
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH 12-BIT A/D CONVERTER
1. Overview
1.1 Description
The Z51F3220 is advanced CMOS 8-bit microcontroller with 32k bytes of Flash. This is powerful microcontroller
which provides a highly flexible and cost effective solution to many embedded control applications. This provides
the following features : 32k bytes of Flash, 256 bytes of IRAM, 768 bytes of XRAM , general purpose I/O, basic
interval timer, watchdog timer, 8/16-bit timer/counter, 16-bit PPG output, 8-bit PWM output, 10-bit PWM output,
watch timer, buzzer driving port, SPI, USI, 12-bit A/D converter, LCD driver, on-chip POR, LVR, LVI, on-chip
oscillator and clock circuitry. The Z51F3220 also supports power saving modes to reduce power consumption.
Device Name Flash XRAM IRAM ADC I/O PORT Package
Z51F3220FNX 32k bytes 768 bytes 256 bytes 16 channel 42 44-pin MQFP
Z51F3220SKX 12 channel 30 32-pin SOP

Z51F3220
Product Specification
PS029902-0212 P R E L I M I N A R Y 11
1.2 Features
•CPU
- 8 Bit CISC Core (8051 Compatible)
•ROM (Flash) Capacity
- 32k Bytes
- Flash with self read/write capability
- On chip debug and In-system programming (ISP)
- Endurance : 100,000 times
•256 Bytes IRAM
•768 Bytes XRAM
- (27 Bytes including LCD display RAM)
•General Purpose I/O (GPIO)
- Normal I/O : 9 Ports
(P0[2:0], P5[5:0])
- LCD shared I/O : 33 Ports
(P0[7:3], P1, P2, P3, P4)
•Basic Interval Timer (BIT)
- 8Bit × 1ch
- Watch Dog Timer (WDT)
- 8Bit × 1ch
- 5kHz internal RC oscillator
•Timer/ Counter
- 8Bit × 1ch (T0), 16Bit × 2ch (T1/T2)
- 8Bit × 2ch (T3/T4) or 16 Bit × 1ch (T3)
•Programmable Pulse Generation
- Pulse generation (by T1/T2)
- 8Bit PWM (by T0)
- 6-ch 10Bit PWM for Motor (by T4)
•Watch Timer (WT)
- 3.91mS/0.25S/0.5S/1S/1M interval at 32.768kHz
•Buzzer
- 8Bit × 1ch
•SPI 2
- 8Bit × 1ch
•USI0/1 (UART + SPI + I2C)
- 8Bit UART × 2ch, 8Bit SPI × 2ch and I2C × 2ch
•12 Bit A/D Converter
- 16 Input channels
•LCD Driver
- 21 Segments and 8 Common terminals
- Internal or external resistor bias
- 1/2, 1/3, 1/4, 1/5, 1/6 and 1/8 duty selectable
- Resistor Bias and 16-step contrast control
•Power On Reset
- Reset release level (1.4V)
•Low Voltage Reset
- 14 level detect (1.60V/ 2.00V/ 2.10V/ 2.20V/
2.32V/ 2.44V/ 2.59V/ 2.75V/ 2.93V/ 3.14V/
3.38V/ 3.67V/ 4.00V/ 4.40V)
•Low Voltage Indicator
- 13 level detect (2.00V/ 2.10V/ 2.20V/ 2.32V/
2.44V/ 2.59V/ 2.75V/ 2.93V/ 3.14V/ 3.38V/
3.67V/ 4.00V/ 4.40V)
•Interrupt Sources
- External Interrupts
(EXINT0~7, EINT8, EINT10, EINT11, EINT12)
(12)
- Timer(0/1/2/3/4) (5)
- WDT (1)
- BIT (1)
- WT (1)
- SPI 2 (1)
- USI0/1 (6)
- ADC (1)
•Internal RC Oscillator
- Inernal RC frequency: 16MHz ±0.5% (T
A
= 25°C)
•Power Down Mode
- STOP, IDLE mode
•Operating Voltage and Frequency
- 1.8V ~ 5.5V (@32 ~ 38kHz with X-tal)
- 1.8V ~ 5.5V (@0.4 ~ 4.2MHz with X-tal)
- 2.7V ~ 5.5V (@0.4 ~ 10.0MHz with X-tal)
- 3.0V ~ 5.5V (@0.4 ~ 12.0MHz with X-tal)
- 1.8V ~ 5.5V (@0.5 ~ 8.0MHz with Internal RC)
- 2.0V ~ 5.5V (@0.5 ~ 16.0MHz with Internal RC)
- Voltage dropout converter included for core
•Minimum Instruction Execution Time
- 125nS (@ 16MHz main clock)
- 61μS (@t 32.768kHz sub clock)
•Operating Temperature: – 40 ~ + 85℃
•Oscillator Type
- 0.4-12MHz Crystal or Ceramic for main clock
- 32.768kHz Crystal for sub clock
•Package Type
- 44 MQFP-1010
- 32 SOP
- 28 SOP
- Pb-free package

Z51F3220
Product Specification
PS029902-0212 P R E L I M I N A R Y 12
1.3 Ordering Information
Table 1-1 Ordering Information of Z51F3220
Device Name ROM Size IRAM Size XRAM Size Package
Z51F3220FNX 32k bytes Flash 256 bytes 768 bytes 44-pin MQFP
Z51F3220SKX 32-pin SOP

Z51F3220
Product Specification
PS029902-0212 P R E L I M I N A R Y 13
1.3.1 Part Number Suffix Designation
Zilog part numbers consist of a number of components, as indicated in the following example.
Example: Part number Z51F3220FNX is an 8-bit MCU with 32 KB of Flash memory and 1 KB of RAM in a 44-pin
MQFP package and operating within a –40°C to +85°C temperature range. In accordance with RoHS standards,
this device has been built using lead-free solder.
Z51 F 32 20 F N X
Temperature Range
X = –40°C to +85°C
Pin Count
N = 44 pins
S = 32 pins
Package
F = MQFP
J = SOP
Device Type
Flash Memory Size
32 = 32 KB Flash
Flash Memory
F = General-Purpose Flash
Device Family
Z51 = Z8051 8-Bit Core MCU
1.4 Development Tools
1.4.1 Compiler
We do not provide the compiler. Please contact the third parties.
The core of Z51F3220 is Mentor 8051. And, device ROM size is smaller than 32k bytes. Developer can use all
kinds of third party’s standard 8051 compiler.
1.4.2 OCD Emulator and Debugger
The OCD (On Chip Debug) emulator supports Zilog’s 8051 series MCU emulation.
The OCD interface uses two-wire interfacing between PC and MCU which is attached to user’s system. The
OCD can read or change the value of MCU internal memory and I/O peripherals. And the OCD also controls
MCU internal debugging logic, it means OCD controls emulation, step run, monitoring, etc.
The OCD Debugger program works on Microsoft-Windows NT, 2000, XP, Vista (32bit) operating system.

Z51F3220
Product Specification
PS029902-0212 P R E L I M I N A R Y 14
If you want to see more details, please refer to OCD debugger manual. You can download debugger S/W and
manual from our web-site.
Connection:
- SCLK (Z51F3220 P01 port)
- SDATA (Z51F3220 P00 port)
OCD connector diagram: Connect OCD with user system

Z51F3220
Product Specification
PS029902-0212 P R E L I M I N A R Y 15
1.4.3 Programmer
Single programmer:
PGMplus USB: It programs MCU device directly.
OCD emulator: It can write code in MCU device too, because OCD debugging supports ISP (In System
Programming).
It does not require additional H/W, except developer’s target system.
Gang programmer:
It programs 8 MCU devices at once.
So, it is mainly used in mass production line.
Gang programmer is standalone type, it means it does not require host PC, after a program is
downloaded from host PC to Gang programmer.
Figure 1.1 StandAlone Gang8 (for Mass Production)

Z51F3220
Product Specification
PS029902-0212 P R E L I M I N A R Y 16
2. Block Diagram
VDD VSS
M8051 Core
IRAM
(256 Bytes)
8 –Bit Timer 0
12 –Bit
A/D Converter
AN0-AN5/P02-P07
AN6-AN13/P17-P10
32k Bytes Flash
T0O/PWM0O/P53
EINT10/P54
EC0/P52
P51/XIN
P52/EINT8/EC0/BLNK
SXIN/P53/T0O/PWM0O
Watch Timer
MOSI2/P14
MISO2/P15
SCK2/P16
SPI2 SS2/P17
Buzzer BUZO/P13/SEG17/AN10/EC1
XRAM
(768 Bytes)
16 –Bit Timer1
T1O/PWM1O/P12
EINT11/P12
EC1/P13
T2O/PWM2O/P11
EINT12/P11 16 –Bit Timer2
P0Port
P00/EC3/DSDA
P01/T3O/DSCL
P02/AN0/AVREF/EINT0/T4O/PWM4AA
P03/SEG26/AN1/EINT1/PWM4AB
P04/SEG25/AN2/EINT2/PWM4BA
P05/SEG24/AN3/EINT3/PWM4BB
P06/SEG23/AN4/EINT4/PWM4CA
P07/SEG22/AN5/EINT5/PWM4CB
USI0
UART0
SPI0
I2C0
TXD0/P41
RX0/P40
MOSI0/P41
MISO0/P40
SCK0/P42
SS0/P43
SDA0/P41
SCL0/P40
TXD1/P20
RXD1/P10
MOSI1/P20
MISO1/P10
SCK1/P21
SS1/P22
SDA1/P20
SCL1/P10
Watchdog Timer
5kHz INT-RC OSC
Basic Interval Timer
Power On Reset
Low Voltage Reset LCD Driver/
Controller
COM0-COM1/P37-P36
COM2-COM7/SEG0-SEG5/P35-P30
SEG6-SEG29/P27-P03
VLC0-VLC3/P43-P40
P5 Port
P50/XOUT
Low Voltage
Indicator
USI1
UART1
SPI1
I2C1
On-Chip Debug
DSDA DSCL
INT-RC OSC
16MHz
Voltage
Down
Converter
RESETB/P55
SXOUT/P54/EINT10
SXIN/P53/T0O/PWM0O
XIN/P51
XOUT/P50
CLOCK/
SYSTEM
CONTROL
SXOUT/P54/EINT10
P55/RESETB
P1Port
P10/SEG14/AN13/RXD1/SCL1/MISO1
P11/SEG15/AN12/EINT12/T2O/PWM2O
P12/SEG16/AN11/EINT11/T1O/PWM1O
P13/SEG17/AN10/EC1/BUZO
P14/SEG18/AN9/MOSI2
P15/SEG19/AN8/MISO2
P16/SEG20/AN7/EINT7/SCK2
P17/SEG21/AN6/EINT6/SS2
P2Port
P20/SEG13/AN14/TXD1/SDA1/MOSI1
P21/SEG12/AN15//SCK1
P22/SEG11/SS1
P23-P27/SEG10-SEG6
P3Port
P30-P33/COM7-COM4/SEG5-SEG2
P34-P35/COM3-COM2/SEG1-SEG0
P36-P37/COM1-COM0
AN14-AN15/P20-P21
P41/VLC2/TXD0/SDA0/MOSI0
P42/VLC1/SCK0
P43/VLC0/SS0
P4 Port P40/VLC3/RXD0/SCL0/MISO0
T3O/P01
EC3/P00 8 –Bit
Timer 3
8 –Bit
Timer 4 16 –Bit
Timer3
EINT0/P02
T4O/P02
EINT1/P03
PWM4AA/P02
PWM4AB/P03
PWM4BA/P04
PWM4BB/P05 6-ch PWM
PWM4CA/P06
PWM4CB/P07
EINT8/BLNK/P52
AVREF/P02
Figure 2.1 Block Diagram
NOTE) The P14–P17, P23–P25, P34–P37, and P43 are not in the 32-pin package.

Z51F3220
Product Specification
PS029902-0212 P R E L I M I N A R Y 17
3. Pin Assignment
=)
(44MQFP-1010)
1
2
12 13
8
9
10
11
3
4
5
6
7
14 15 16 17 18 19 20 21 22
33
32
26
25
24
23
31
30
29
28
27
44 43 42 41 40 39 38 37 36 35 34
P55/RESETB
P40/VLC3/RXD0/SCL0/MISO0
P41/VLC2/TXD0/SDA0/MOSI0
P52/EINT8/EC0/BLNK
P05/SEG24/AN3/EINT3/PWM4BB
P04/SEG25/AN2/EINT2/PWM4BA
P54/SXOUT/EINT10
P53/SXIN/T0O/PWM0O
P11/SEG15/AN12/EINT12/T2O/PWM2O
P12/SEG16/AN11/EINT11/T1O/PWM1O
P17/SEG21/AN6/EINT6/SS2
P07/SEG22/AN5/EINT5/PWM4CB
P15/SEG19/AN8/MISO2
P16/SEG20/AN7/EINT7/SCK2
P13/SEG17/AN10/EC1/BUZO
P14/SEG18/AN9/MOSI2
P06/SEG23/AN4/EINT4/PWM4CA
P25/SEG8 P24/SEG9 P23/SEG10 P22/SEG11/SS1 P21/SEG12/AN15/SCK1 P20/SEG13/AN14/TXD1/SDA1/MOSI1 P10/SEG14/AN13/RXD1/SCL1/MISO1 P27/SEG6 P26/SEG7 P31/COM6/SEG4 P30/COM7/SEG5
P51/XIN
P50/XOUT
P02/AN0/AVREF/EINT0/T4O/PWM4AA
P01/T3O/DSCL
P00/EC3/DSDA
VDD
P03/SEG26/AN1/EINT1/PWM4AB
VSS
P32/COM5/SEG3
P33/COM4/SEG2
P37/COM0
P36/COM1
P35/COM2/SEG0
P34/COM3/SEG1
P42/VLC1/SCK0
P43/VLC0/SS0
Figure 3.1 Z51F3220 44MQFP-1010 Pin Assignment
NOTE) On On-Chip Debugging, ISP uses P0[1:0] pin as DSDA, DSCL.