JYTEK PXIe-63988 User manual

PXIe-63988
PXI Express Embedded Controller
User’s Manual
Manual Rev.: 1.0
Revision Date: July 04, 2021
Part No: 50M-00028-1000

ii Revision History
Revision History
Revision Release Date Description of Change(s)
1.0 2021-07-04 Initial release

Preface iii
Preface
Copyright © 2021 JYTEK Technology Inc.
This document contains proprietary information protected by copy-
right. All rights are reserved. No part of this manual may be repro-
duced by any mechanical, electronic, or other means in any form
without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior
notice in order to improve reliability, design, and function and does
not represent a commitment on the part of the manufacturer.
In no event will the manufacturer be liable for direct, indirect,
special, incidental, or consequential damages arising out of the
use or inability to use the product or documentation, even if
advised of the possibility of such damages.
JYTEK is committed to fulfill its social responsi-
bility to global environmental preservation
through compliance with the European Union's
Restriction of Hazardous Substances (RoHS)
directive and Waste Electrical and Electronic
Equipment (WEEE) directive. Environmental
protection is a top priority for JYTEK . We have
enforced measures to ensure that our products,
manufacturing processes, components, and raw
materials have as little impact on the environment as possible.
When products are at their end of life, our customers are encour-
aged to dispose of them in accordance with the product disposal
and/or recovery programs prescribed by their nation or company.
Battery Labels (for products with battery)
California Proposition 65 Warning
ᘄ㟁ụㄳᅇᨲ
PXIe-63988

iv Preface
WARNING: This product can expose you to chemicals
including acrylamide, arsenic, benzene, cadmium,
Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Diox-
ane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and
vinyl materials, which are known to the State of California to cause
cancer, and acrylamide, benzene, cadmium, lead, mercury,
phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and
vinyl materials, which are known to the State of California to cause
birth defects or other reproductive harm. For more information go
to www.P65Warnings.ca.gov.
Trademarks
Product names mentioned herein are used for identification pur-
poses only and may be trademarks and/or registered trademarks
of their respective companies.
Conventions
Take note of the following conventions used throughout this
manual to make sure that users perform certain tasks and
instructions properly.
NOTE:
NOTE:
Additional information, aids, and tips that help users perform
tasks.
CAUTION:
Information to prevent minor physical injury, component dam-
age, data loss, and/or program corruption when trying to com-
plete a task.
WARNING:
Information to prevent serious physical injury, component
damage, data loss, and/or program corruption when trying to
complete a specific task.

v
Table of Contents
Revision History...................................................................... ii
Preface.................................................................................... iii
List of Figures........................................................................ ix
List of Tables.......................................................................... xi
1 Introduction ........................................................................ 1
1.1 Features............................................................................... 2
1.2 Specifications....................................................................... 3
1.3 I/O and Indicators ................................................................ 7
1.3.1 Front Panel ................................................................. 7
1.3.2 GPIB Connector ....................................................... 10
1.3.3 Reset Button............................................................. 11
1.3.4 LED Indicators .......................................................... 11
1.3.5 USB 2.0 Ports........................................................... 12
1.3.6 Gigabit Ethernet Ports .............................................. 13
1.3.7 USB 3.0 Ports........................................................... 14
1.3.8 COM Port.................................................................. 14
1.3.9 Onboard Connections and Settings.......................... 15
2 Getting Started ................................................................. 17
2.1 Package Contents ............................................................. 17
2.2 Operating System Installation............................................ 18
2.2.1 Installation Environment ........................................... 19
2.2.2 Installing the PXIe-63988 ......................................... 20
2.2.3 Replacing the Hard Drive or Solid State Drive ......... 23
2.2.4 Replacing the Battery Backup .................................. 24
2.2.5 Clearing CMOS ........................................................ 25
PXIe-63988

vi
3 Driver Installation.............................................................. 27
A Appendix: PXI Trigger I/O Functions...............................29
A.1 Data Type .......................................................................... 29
A.2 Function Library ................................................................. 31
A.2.1 TRIG_Init .................................................................. 31
A.2.2 TRIG_Close .............................................................. 32
A.2.3 TRIG_SetSoftTrg ...................................................... 33
A.2.4 TRIG_Trigger_Route ................................................ 34
A.2.5 TRIG_Trigger_Clear ................................................. 36
A.2.6 TRIG_GetSoftTrg...................................................... 37
A.2.7 TRIG_Trigger_Route_Query .................................... 38
A.2.8 TRIG_GetDriverRevision .......................................... 40
B Appendix: BIOS Setup.......................................................41
B.1 Entering the BIOS .............................................................. 41
B.2 Navigation .......................................................................... 42
B.3 Menu Structure .................................................................. 43
B.4 Main ................................................................................... 44
B.4.1 BIOS Information ...................................................... 44
B.4.2 System Information................................................... 44
B.4.3 System Date and Time ............................................. 45
B.5 Advanced ........................................................................... 46
B.5.1 CPU Configuration.................................................... 46
B.5.2 Memory Configuration .............................................. 48
B.5.3 Graphics Configuration ............................................. 48
B.5.4 USB Configuration .................................................... 49
B.5.5 TPM 2.0 Configuration.............................................. 50
B.5.6 Onboard Devices Configuration................................ 51
B.5.7 PCI and PCIe Configuration ..................................... 51
B.5.8 Advanced Power Management ................................ 52
B.5.9 Network Stack Configuration .................................... 52

vii
B.5.10 System Management................................................ 53
B.5.11 Flags......................................................................... 53
B.5.12 Power Consumption ................................................. 54
B.5.13 Hardware Health Configuration ................................ 55
B.5.14 PXIe Links Control Configuration ............................. 55
B.6 Chipset............................................................................... 56
B.6.1 System Agent (SA) Configuration............................. 56
B.6.2 PCH-IO Configuration............................................... 57
B.7 Security.............................................................................. 59
B.7.1 Secure Boot.............................................................. 59
B.8 Boot ................................................................................... 60
B.8.1 CSM.......................................................................... 61
B.8.2 UEFI Hard Disk Drive BBS Priorities ........................ 61
B.9 Save & Exit ........................................................................ 62
C Appendix: Dual BIOS........................................................63
D Appendix: Legacy Boot Mode Settings...........................65
Important Safety Instructions.............................................. 67
Getting Service...................................................................... 69
PXIe-63988

viii
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List of Figures ix
List of Figures
Figure 1-1: Functional Block Diagram................................................ 3
Figure 1-2: Front Panel ...................................................................... 7
Figure 1-3: PXI Trigger SMB Jack ..................................................... 8
Figure 1-4: DisplayPort Connector..................................................... 9
Figure 1-5: GPIB Connector............................................................. 10
Figure 1-6: LED Indicators ............................................................... 11
Figure 1-7: COM Port....................................................................... 14
Figure 1-8: Onboard Configuration .................................................. 15
Figure B-1: BIOS Setup Navigation.................................................. 42
PXIe-63988

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List of Tables xi
List of Tables
Table 1-1: Front Panel Legend ......................................................... 7
Table 1-2: DisplayPort Pin Assignment ............................................ 9
Table 1-3: GPIB Pin Description..................................................... 10
Table 1-4: LED Indicator Legend .................................................... 11
Table 1-5: USB 2.0 Port Pin Assignment........................................ 12
Table 1-6: Ethernet Port Pin Assignments...................................... 13
Table 1-7: Ethernet Status LED Descriptions ................................. 13
Table 1-8: D-sub COM Port Signal Functions................................. 14
Table 1-9: Onboard Configuration Legend ..................................... 15
Table A-1: Data Type ...................................................................... 29
Table B-1: BIOS Hot Key Functions................................................ 42
PXIe-63988

xii List of Tables
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Introduction 1
1 Introduction
The JYTEK PXIe-63988 PXI Express embedded controller is
based on the Intel®Xeon® E processor (formerly Coffee Lake)
specifically designed for PXI Express-based testing systems. A
rugged and stable operating environment is provided for a variety
of testing and measurement applications.
Combining state-of-the-art Intel®Core™ processors and up to
64GB of DDR4 2400MHz memory, the PXIe-63988 utilizes
multiple computing engines on a single processor, enabling
execution of four independent tasks simultaneously. With a
configurable PCIe switch, the PXIe-63988 can support four links
x4 or two links x8 x16 PXI Express link capability, with maximum
system throughput of up to 16 GB/s (PCI Express 3.0).
PXI Express-based testing systems typically make up a PXI
Express platform and diversified standalone instruments for com-
plex testing tasks. The PXIe-63988 series provides ample
inter-faces, including two DisplayPort connectors, allowing
connection to two monitors, dual USB 3.0 connections for high
speed periph-eral devices, dual Gigabit Ethernet ports, one for
LAN connection and the other for controlling LXI instruments,
four USB 2.0 ports for peripheral devices and USB instrument
control, an SMB con-nector for configurable input/output routing
of signal to/from PXI Trigger Bus on PXI Express chassis, and a
Micro-D GPIB connec-tor for GPIB instrument connection, for
hybrid PXI-based testing system control.
NOTE:
NOTE:
Memory addressing over 4 GB is OS-dependent, such that a
32-bit operating system may be unable to address memory
space over 4GB. To fully utilize memory, 64-bit operating sys-
tems are required.
PXIe-63988

2 Introduction
1.1 Features
PXI-5 PXI Express Hardware Specification Rev.1.0
Intel® Xeon® E processor E-2276ME (formerly Coffee
Lake) 820EQ 2.8/4.5 GHz (Turbo), 45W (cTDP, 6C/GT2)
Dual Channel DDR4 SO-DIMM
Up to 64 GB 2400 MHz
Maximum System Throughput 16 GB/s
PXI Express Link Capability
4-link Configuration: x4 x4 x4 x4
2-link Configuration: x16 x8
SATA Storage (built-in 2.5” 500 GB or 240 GB SATA solid
state hard drive)
Supports 2.5” HDD or SSD
SATA 6.0 Gb/s
Supports AHCI
Integrated I/O
Dual Gigabit Ethernet ports
Two USB 3.0 Ports
Four USB 2.0 Ports
Built-in GPIB (IEEE488) controller
Dual DisplayPort connectors
One COM port (D-sub9 serial)
Trigger I/O for advanced PXI™ trigger functions
OS
Microsoft Windows 10 64-bit

Introduction 3
1.2 Specifications
Figure 1-1: Functional Block Diagram
Processor
Intel® Xeon® E processor (formerly Coffee Lake)
DMI (Direct Media Interface) 3.0 with 8 GT/s bandwidth in
each direction
Chipset
Intel®CM246 chipset
Front Panel
Connectors
DisplayPort
Connector x2
GPIB
Connector
GbE
Connector
GbE
Connector
USB3.0
Connector x2
USB2.0
Connector x4
COM Port
Connector
(RS-232/42 2/485)
Intel® Xeon® E
Processor
(formerly “Coffee Lake”)
Intel® CM246 Chipset
GPIB Controller
GbE Controller
I219
GbE Controller
I210
LCP-COM Port
Programmable MUX
SMBus Controller
DP/HDMI Dual Mode
PCIe x1
PCIe x1
PCIe x1
USB 3.0
USB 2.0
LPC
PCIe x1
DMI 3.0Intel FDI
Trigger Signal
SMB
Connector
SATA 2.5" SATA
Storage
PCI Express
Switch
(PCI Express 3.0)
DDR4 2133/2400
MHz SODIMM x2
Memory
Bus
PCIe 3.0 x16
Rear
Connectors to
PXI Express
Chassis
PCIe 3.0
2LinkMode
(x16 x8)
OR
PCIe 3.0
4LinkMode
(x4 x4 x4 x4)
SMBus
Trigger Bus
PXIe-63988

4 Introduction
Memory
Two standard 260-pin DDR4 SO-DIMM sockets
Supports 2133/2400 MHz RAM up to 64 GB total
Supports non-ECC, unbuffered memory
Video
DisplayPort resolution up to 3840 x 2160 @ 60 Hz
DVI (with passive DisplayPort-to-DVI adapter) resolution up
to 1920 x 1200 @ 60 Hz
Storage
Built-in 2.5” 500 GB or 240 GB SATA solid state hard drive.
Ethernet Connectivity
Dual Gigabit Ethernet controllers through two RJ-45 connectors
with speed/link/active LED on the faceplate, with both supporting
Wake on LAN.
USB
Four USB 2.0 and two USB 3.0 ports on the faceplate.
GPIB
Onboard IEEE488 GPIB controller through Micro-D 25-pin con-
nector on the faceplate.
NOTE:
NOTE:
The externally accessible SO-DIMM socket can accept
replacement DDR4 DRAM DIMM modules.
PXIe-63988 specifications and stability guarantees are only
sup-ported when JYTEK -provided DDR4 DRAM SO-DIMM
mod-ules are used.
NOTE:
NOTE:
DisplayPort adapters for other standards are available, with
maximum available resolution dependent on the adapter

Introduction 5
Trigger I/O
One SMB connector on the faceplate to route an external trigger
signal to/from PXI trigger bus.
Dimensions (3U PXI module)
3U/4-slot PXI standard
Weight
1.0 kg (exclusive of packaging)
Environmental
Shock and Vibration
Functional shock 30 G, half-sine, 11 ms pulse duration
Random vibration:
Operating: 5 to 500 Hz, 0.21 Grms, 3 axes
Non-operating: 5 to 500 Hz, 2.46 Grms, 3 axes
Condition Range
Operating temperature with SSD 0 to 55°C
Operating temperature with HDD 0 to 50°C
Storage temperature -20 to 70°C
Relative humidity, non-condensing 5 to 95%
NOTE:
NOTE:
Environmental, shock, and vibration values are only valid with
use of an JYTEK -provided SSD/HDD
PXIe-63988

6 Introduction
Certifications
Electromagnetic compatibility:
EN 55011:2016+A1: 2017 (Group 1, Class A)
CISPR 11:2009+A1: 2010 (Group 1, Class A)
EN 61000-3-2:2014: Class A
EN 61000-3-3:2013: Class A
EN 61326-1: 2013, Table 2 (Industrial)
FCC 47 CFR Part 15 Subpart B (Class B)
ICES-003 Issue 7-2020
AS/NZS CISPR 11: Group 1, Class A emissions
The PXIe-63988 meets the essential requirements of
applicable European Directives.
Power Requirements
Typical Consumption DC +3.3V DC +12V
Typical operation
(Measured while W10 is idle) 3A 6A
Heavy operation
(Measured while W10 is under heavy
CPU and storage utilization)
3A 11A

Introduction 7
1.3 I/O and Indicators
1.3.1 Front Panel
Figure 1-2: Front Panel
Table 1-1: Front Panel Legend
AReset Button FGPIB Connector
(Micro D-Sub 25P)
B2X DisplayPort G2X Gigabit Ethernet
C2X USB 3.0 HPXI Trigger
D4X Type-A USB 2.0 ILED indicators
ECOM port (D-sub9 serial)
PXIe-63988
A
C
G
B
D
F
H
E
I

8 Introduction
PXI Trigger Connector
Figure 1-3:PXI Trigger SMB Jack
The PXI trigger connector is an SMB jack, used to route external
trigger signals to or from the PXI backplane. Trigger signals are
TTL-compatible and edge sensitive. The PXIe-63988 provides
four trigger routing modes from/to the PXI trigger connector to
synchro-nize PXI modules, including
From a selected trigger bus line to PXI trigger connector
From the PXI trigger connector to a selected trigger bus line
From software trigger to a selected trigger bus line
From software trigger to PXI trigger connector
All trigger modes are programmable by the provided driver.
Trigger
Ground