LG G5500 User manual

REVISED HISTORY
DATE ISSUE CONTENTS OF CHANGES S/W VERSION
13/MAY/2003 ISSUE 0.1 Initial Release
01/Sep./2003 ISSUE 0.2
The information in this manual is subject to change without notice and should not be construed as
a commitment by LGE Inc. Furthermore, LGE Inc. reserves the right, without notice, to make
changes to equipment design as advances in engineering and manufacturing methods warrant.
This manual provides the information necessary to install, program, operate and maintain the
G5500/7050.
-1-

-3-
Table of Contents
1. INTRODUCTION.................................. 5
1.1 Purpose ............................................….
1.2 Regulatory Information ..........................
1.3 Abbreviations .........................................
2. General Performance .....................… 8
2.1 Product Name ................................…….
2.2 Supporting Standard ……………………..
2.3 Main Parts …………………………………
2.4 H/W Features …………………………….
2.5 S/W Features …………………………….
3. H/W Circuit Description ....................13
3.1 RF Transceiver General Description ……
3.2 Receiver Part …………………………….
3.3 Digital Baseband (DBB) Processor ………
3.4 Analog Baseband (ABB) Processor …...…
3.5 Camera Circuit ……..………………………
5
5
7
8
8
8
9
11
13
13
20
25
44
4. TROUBLE SHOOTING ................… 51
4.1 Main Components Placement(G5500) ...
Main Components Placement(G7050) ...
4.2 Main Components .....................…..........
4.3 Keypad Components Placement ............
4.4 Baseband Components ..……………..…
4.5 Power On Trouble …..........…………..….
4.6 Charging Trouble ........................…..…..
4.7 LCD Display Trouble ………....................
4.8 Receiver Trouble ………….....................
4.9 Microphone Trouble ………………………
4.10 Vibrator Trouble ……….…………………
4.11 Keypad Backlight Trouble …….…………
4.12 Slide Open/Close Trouble ……….………
4.13 SIM Detect Trouble …….....……………..
51
52
53
54
55
56
57
59
61
65
68
70
72
74
5. ASSEMBLY INSTRUCTION ………....102
5.1 Disassembly (G5500) .............................
5.2 Disassembly (G7050) …........………….
102
108
8. CIRCUIT DIAGRAM .............………... 129
8.1 BB ………..…………….........................
8.2 MEMORY, etc. …………………………….
8.3 MIDI, AUDIO ………….………………….
8.4 I/O, Connector ……….…………….……
8.5 RF ………………………..….……..…….
8.6 CAMERA ………………………………...
8.7 KEYPAD ………………………………….
129
130
131
132
133
134
135
6. DOWNLOAD ……………………...……114
6.1 Download Setup .....................................
6.2 Download Procedure ………...….……….
114
115
7. SERVICE AND CALIBRATION …….. 122
4.14 Earphone Trouble ……….……………….
4.15 Infrared Data Association Trouble ……
4.16 Camera Trouble ………………………….
76
81
84
7.1 Service S/W ……....................................
7.2 Calibration ……………….…...….……….
122
125
9. PCB LAYOUT .............……………..... 137

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Table of Contents
10. ENGINEERING MODE ................... 141
11.1 Setting Method .................................….
142
11. STANDALONE TEST ..................... 142
12.1 Exploded View .................................….
12.2 Accessory ………………………………..
12.3 Replacement Parts
<Mechanic components> ………………..
Replacement Parts
<Main components>………………………
143
145
146
148
12. EXPLODED VIEW &
REPLACEMENT PART LIST.......... 143

1. Introduction
1.1 Purpose
This manual provides the information necessary to repair, calibration, description and download the
features of the G5500/7050.
1.2 Regulatory Information
Toll fraud, the unauthorized use of telecommunications system by an unauthorized part (for example,
persons other than your company’s employees, agents, subcontractors, or person working on your
company’s behalf) can result in substantial additional charges you’re your telecommunications
services. System users are responsible for the security of own system. There are may be risks of toll
fraud associated with your telecommunications system. System users are responsible for
programming and configuring the equipment to prevent unauthorized use. LGE does not warrant that
this product is immune from the above case but will prevent unauthorized use of common-carrier
telecommunication service of facilities accessed through or connected to it. LGE will not be
responsible for any charges that result from such unauthorized use.
A. Security
If a telephone company determines that the equipment provided to customer is faulty and possibly
causing harm or interruption in service to the telephone network, it should disconnect telephone
service until repair can be done. A telephone company may temporarily disconnect service as long as
repair is not done.
B. Incidence of Harm
A local telephone company may make changes in its communications facilities or procedure. If these
changes could reasonably be expected to affect the use of the G5500/7050 or compatibility with the
network, the telephone company is required to give advanced written notice to the user, allowing the
user to take appropriate steps to maintain telephone service.
C. Changes in Service
Maintenance limitations on the G5500/7050 must be performed only by the LGE or its authorized
agent. The user may not make any changes and/or repairs expect as specifically noted in this manual.
Therefore, note that unauthorized alternations or repair may affect the regulatory status of the system
and may void any remaining warranty.
D. Maintenance Limitations
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The G5500/7050 complies with rules regarding radiation and radio frequency emission as defined by
local regulatory agencies. In accordance with these agencies, you may be required to provide
information such as the following to the end user.
E. Notice of Radiated Emissions
The pictures in this manual are for illustrative purposes only; your actual hardware may look slightly
different.
F. Pictures
An G5500/7050 may interfere with sensitive laboratory equipment, medical equipment, etc.
Interference from unsuppressed engines or electric motors may cause problems.
G. Interference and Attenuation
H. Electrostatic Sensitive Devices
Boards, which contain Electrostatic Sensitive Device (ESD), are indicated by the sign.
Following information is ESD handling:
• Service personnel should ground themselves by using a wrist strap when exchange
system boards.
• When repairs are made to a system board, they should spread the floor with anti-static mat
which is also grounded.
• Use a suitable, grounded soldering iron.
• Keep sensitive parts in these protective packages until these are used.
• When returning system boards or parts like EEPROM to the factory, use the protective
package as described.
ATTENTION
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1.3 Abbreviations
For the purposes of this manual, following abbreviations apply:
APC Automatic Power Control
BB Baseband
BER Bit Error Ratio
CC-CV Constant Current – Constant Voltage
DAC Digital to Analog Converter
DCS Digital Communication System
dBm dB relative to 1 milliwatt
DSP Digital Signal Processing
EEPROM Electrical Erasable Programmable Read-Only Memory
EL Electroluminescence
ESD Electrostatic Discharge
FPCB Flexible Printed Circuit Board
GMSK Gaussian Minimum Shift Keying
GPIB General Purpose Interface Bus
GSM Global System for Mobile Communications
IPUI International Portable User Identity
IF Intermediate Frequency
LCD Liquid Crystal Display
LDO Low Drop Output
LED Light Emitting Diode
OPLL Offset Phase Locked Loop
PAM Power Amplifier Module
PCB Printed Circuit Board
PGA Programmable Gain Amplifier
PLL Phase Locked Loop
PSTN Public Switched Telephone Network
RF Radio Frequency
RLR Receiving Loudness Rating
RMS Root Mean Square
RTC Real Time Clock
SAW Surface Acoustic Wave
SIM Subscriber Identity Module
SLR Sending Loudness Rating
SRAM Static Random Access Memory
STMR Side Tone Masking Rating
TA Travel Adapter
TDD Time Division Duplex
TDMA Time Division Multiple Access
UART Universal Asynchronous Receiver/Transmitter
VCO Voltage Controlled Oscillator
VCTCXO Voltage Control Temperature Compensated Crystal Oscillator
WAP Wireless Application Protocol
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2. General Performance
2.1 Product Name
Item Feature Comment
Supporting Standard
E-GSM/ DCS Dual Band
with seamless handover
Phase 2+
SIM Toolkit : Class 1,2,3,A~E
Frequency Range
E-GSM TX : 880 – 915 MHz
E-GSM RX : 925 – 960 MHz
DCS 1800 TX : 1710 – 1785 MHz
DCS 1800 RX : 1805 – 1880 MHz
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G5500/7050: Support GPRS (Class 10)
2.2 Supporting Standard
Application
Standard
WAP 2.0 : Yes
MMS : Yes
JAVA : MIDP v1.0.3
IrDA 1.3
G5500/7050
2.3 Main Parts: GSM Solution
Digital Baseband CALYPSO @39MHz (D751992GHH)
Analog Baseband IOTA (TWL3014CGGM)
RF Chip Aero (Multi slot) (Si4200-BM, Si4201-BM, Si4133T-BM)

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2.4 H/W Features
Item Feature Comment
Form Factor Slide Down LCD (65K Color)
Battery
Capacity
Standard: Li-Ion, 860mAh
Packing Type: Hard Pack
Cell Size: Standard
55(L)×33.7(W)×49.5(H)mm
Size Standard: 94×44×21.5mm L×W×H
Weight 89g With Battery
PCB Main PCB: 8Layers, 1t
Keypad PCB: 2Layers, 0.6t
AVG TCVR
current (mA)
Max : 260 mA (Power Level 5)
Max : 120 mA (Power Level 19) Estimated
Standby Current 4.6mA @ Paging Period 9
Standby time Up to 150 hours @ Paging Period 9
Charging time Below 3 hr. @ Power Off / 860mAh
Talk time Min : 4hr @Power Level 7
Min : 6hr @Power Level 12 @ 860mAh
RX sensitivity GSM 900 : -105 dBm
DCS 1800 : -105 dBm
TX output power GSM 900 : 32 dBm
DCS 1800 : 29 dBm
Class4 (GSM)
Class1 (DCS)
GPRS compatibility GPRS Class 10
SIM card type Plug-In SIM - 3V
Display
- LCD : 65K Color-STN (128 X160)
- Pixels : 0.219 x 0.219 mm
- View Area : 30.54 x 36.04 mm
- Active Area : 28.02 x 35.028 mm
- Backlight : White LED
Status Indicator Yes (Red, Green)
Keypad
Alphanumeric Key : 12
Function Key : 12
Side Key : 2
Total Number of Keys : 26
Function Key:
4 Key Navigation & OK,
F1, F2, SND, END/PWR,
Clear, Book Mark (Camera),
Voice Recording

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Item Feature Comment
Antenna Fixed Type
System connector 24 Pin
Ear Phone Jack 3 Pole (φ2.5mm)
PC synchronization Yes CDROM
Memory Flash : 128Mbit / SRAM : 64Mbit AMD
Speech coding FR, EFR, HR
Data & Fax Built in Data & Fax support
Vibrator Built in Vibrator
IrDA Built in IrDA PC sync support
MIDI (for Buzzer
Function) 40 Poly Buzzer Function By Using
MIDI IC
Voice Recording up to 90 sec 30sec x 3
Travel Adapter Yes
Camera Sensor VGA / CIS G7050 only
Options
Travel Adapter
Ear-Microphone
Hand Strap
Cigarette Lighter Adapter
Data Cable
Handsfree Car Kit
Simple Hands Free kit
TBD
TBD

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2.5 S/W Features
Item Feature Comment
RSSI 0~5 level Antenna
Quick Access Mode Schedule/Ring Tone/Phonebook
Camera/GPRS/Phonebook(G7050)
Battery Charging 0~3 level
Key Volume 0~5 level
Keypad Volume 0~5 level
Effect sound volume 0~5 level
Ring Volume 1~5 level
Time/Date Display Yes
Text Input T9
Multi-language Yes
PC Sync Schedule/Phonebook/SMS MS Scheduler & Outlook
Speed Dial Yes (2~9) Voice mail center →1 key
Profile Yes
CLIP/CLR Yes
Phonebook 3 Number + 1 Memo + 1 e-mail Phone (Up to 255 entries)
Last Dial Number Yes (20)
Last Received
Number Yes (20)
Last Missed Number Yes (10)
Search Number/Name Yes
Group 7 / User Editor
Fixed Dial Number Yes
Voice Memo 30 secs * 3
Call Remainder Yes
Network Selection Automatic / Manual

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Item Feature Comment
Mute Yes
Call Divert Yes
Call Barring Yes
Call Charge Yes
Call Duration Yes
SMS (EMS) 100
EMS
Send/Receive/Save Yes Melody/Picture/Animation
MMS Yes
WAP Browser WAP 2.0
Java CLDC v1.0.3 / MIDP v1.0.3
Wall Paper Yes Max. 10 preset
Download Melody/
Wallpaper (MMS) Over the WAP
Long Message Mac. 918 Character(6page*153)
Cell Broadcast Yes
Calendar Yes
Memo 20
World Clock Yes
Unit Convert Length/Surface/Volume/Weight
Fax & Data Yes
SIM Lock Yes Operator Dependent
SIM Toolkit Class 1,2,3
Camera
Image resolution : 640 x 480
300 KB dynamic memory for
images : Max 100 photos (128 x 96)
Max 4x zoom
G7050 only
Phone lock/Key lock Yes
Security DRM (Forward-lock only)
CPHS Yes
IM Yes G7050 for T-Mobile only

3. H/W Circuit Description
3.1 RF Transceiver General Description
The RF parts consist of a transmitter part, a receiver part, a frequency synthesizer part, a voltage
supply part, and a VC-TCXO part.
The Aero transceiver is composed of three RF chipsets, Si4200-BM[U502], Si4133T-BM[U505] and
Si4201-BM[U503] which is a dual and triple-band GSM/GPRS wireless communications.
This device integrated a receiver based on a low IF (100KHz) architecture and a transmitter based on
modulation loop architecture. And, the synthesizer[U505] part employed the Silicon Labs Si4133T-BM,
a complete dual band synthesizer with built in VCOs.
The transceiver employed a 3 wire serial interface to allow an external system controller to write the
control registers for dividers, receive path gain, power down setting, and other controls.
3.2 Receiver Part
The receiver part uses a low-IF receiver architecture that allows for the on-chip integration of the
channel selection filters, eliminating the external RF image reject filters and the IF SAW filter
required in conventional super-heterodyne architecture. The Si4200-BM[U502] integrates three
differential input LNAs that are matched to the 200 Ohm balanced-output SAW filters through
external LC matching networks. A quadrature image-rejection mixer downconverts the RF signal
to a 100kHz intermediate frequency (IF) with the RFLO from the Si4133T-BM[U505]. The mixer
output is amplified with an analog programmable gain amplifier (PGA) and quadrature IF signal is
digitized with high resolution A/D converters (ADCs). The Si4201-BM[U503] downconverts the ADC
output to baseband with a digital 100kHz quadrature LO signal. Digital decimation and IIR filters
perform channel selection to remove blocking and reference interference signals. After channel
selection, the digital output is scaled with digital PGA, which is controlled with the DGAIN[5:0] bits
in register 05h.The amplified digital output signal go through with DACs that drive a differential
analog signal onto the RXIP,RXIN,RXQP and RXQN pins to interface to standard analog ADC
input baseband ICs.
Antenna Bar Number
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Power (dBm)
Antenna Display
5≥-85
4≥-90
3≥-95
2≥-100
2≥-105
1< -105

Figure 1. RF Receiver Block
3.2.1. RF Front End
RF front end consists of Antenna Switch(FL501), dual band LNAs integrated in transceiver(U502).
The Received RF signals (EGSM 925MHz ~ 960MHz, DCS 1805MHz ~ 1880MHz) are fed into the
antenna or mobile switch. An antenna matching circuit is between the antenna and the mobile switch.
The Antenna Switch(FL501) is used for control the Rx and TX paths. And, the input signals VC1 and
VC2 of a FL501 are directly connected to baseband controller to switch either TX or RX path on. Ant
S/W module(FL501) is an antenna switch module for dual band phone. The logic and current is given
below Table 3-1.
-14-
Table 3-1. The Logic and Current
VC1
EGSM TX 0 V
DCS TX 2.5~3.0 V
EGSM/DCS RX 0 V
VC2
2.5~3.0 V
0 V
0 V
Current
10.0 mA max
10.0 mA max
< 0.1 mA
The receiver part uses a low-IF receiver architecture that allows for the on-chip integration of the
channel selection filters, eliminating the external RF image reject filters and the IF SAW filter required
in conventional super-heterodyne architecture. The Si4200-BM[U502] integrates three differential
input LNAs that are matched to the 200 ohm balanced-output SAW filters through external LC
matching networks.
ADC
ADC
ADC
ADC
RF
PLL
RF
PLL
IF
PLL
IF
PLL
Channel Filter
Channel Filter
DAC
DAC
DAC
DAC
100KHz
100KHz
D
I
P
D
I
P
EGSM
DCS
PAM
U504
RF3133
FL501
Antenna Switch
13MHz
I
Q
U502/Si4200 U503/Si4201
U505/Si4133T
÷2:GSM
÷2:GSM
÷1:DCS
÷1:DCS
0˚/
90˚
0˚/
90˚
RF1
RF2 IF
PGA PGA
U506
VC-TCXO
EGSM
DCS
PCS
LNA
FL502
FL503
Baseband
(TI)
U102
IOTA
+
U101
Calypso
(CO35)
Baseband
(TI)
U102
IOTA
+
U101
Calypso
(CO35)

A quadrate image-rejection mixer downconverts the RF signal to a 100kHz intermediate frequency (IF)
with the RFLO from the Si4133T-BM[U505]. The RFLO frequency is between 1849.8 and 1918.8 MHz,
and is divided by two in the Si4200 for EGSM modes. The RFLO frequency is between 1804.9 and
1879.9 MHz, and is divided by one in the Si4200 for DCS modes. The mixer output is amplified with
an analog programmable gain amplifier (PGA), which is controlled with the AGAIN[2:0] bits in register
05h.
The quadrate IF signal is digitized with high resolution A/D converters (ADCs).
The Si4201-BM[U503] down-converts the ADC output to baseband with a digital 100kHz quadrate LO
signal. Digital decimation and IIR filters perform channel selection to remove blocking and reference
interference signals. The response of the IIR filter is programmable to a high selectivity
setting(CSEL=0) or a low selectivity setting (CSEL=1). After channel selection, the digital output is
scaled with digital PGA, which is controlled with the DGAIN[5:0] bits in register 05h.
3.2.2. IF
The amplified digital output signal go through with DACs that drive a differential analog signal onto the
RXIP, RXIN, RXQP and RXQN pins to interface to standard analog ADC input baseband ICs.
No special processing is required in the baseband for offset compensation or extended dynamic range.
Compared to a direct-conversion architecture, the low-IF architecture has a much greater degree of
immunity to dc offsets that can arise from RF local oscillator(RFLO) self-mixing, 2nd order distortion of
blockers, and device 1/f noise.
3.2.3. Demodulator and Baseband Processing
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3.2.4. Synthesizer Part
The synthesizer IC, the Si4133T-BM[U505] is a monolithic CMOS integrated circuit that performs IF
and RF synthesis. Two complete PLLs are integrated including VCOs, varactors, resonators, loop
filters, reference and VCO dividers, and phase detectors. Differential outputs for the IF and RF PLLs
are provided for direct connection to the Si4200-BM[U502] transceiver IC. The RF PLL uses two
multiplexed VCOs.
The RF1 VCO is used for Receive mode, and the RF2 VCO is used for Transmit mode. The IF PLL is
used only during Transmit mode and uses a single VCO. The center frequency of each of the three
VCOs on the Si4133T is set by connection of an external inductance(Lext). The IF and RF output
frequencies are set by programming the N-Divider registers, N[RF1], N[RF2] and N[IF]. Programming
the N-Divider register for either RF1 or RF2 automatically selects the proper VCO. The output
frequency of each PLL is as follows:
fout = N * fø
A programmable divider at the XIN pin allows either a 13 or 26MHz from the external applied crystal
oscillator. The RF PLL phase detector update rate(fø) can be programmed with the RFUP bit in
register 31h to either fø = 100kHz or fø= 200kHz. The IF PLL always uses fø = 200kHz. Receive
mode should use fø = 100kHz in DCS1800 and PCS1900 bands, and fø = 200kHz in the GSM850 and
E-GSM 900 bands.

Transmit modes should always use fø = 200kHz. The IF and RF output frequencies are set by
programming the N-Divider registers and also programmed via 3-wire interface with external system
controller.
Figure 2. Synthesizer Block
-16-
3.2.5. Transmitter Part
The Transmitter part contains Si4200-BM[U502] active parts, Power Amp Module[U504] and Antenna
switch[FL501].
The transmit section of Si4200-BM [U502] consists of an I/Q baseband upconverter, an offset phase-
locked loop (OPLL) and two 50 ohm output buffers that can drive external power amplifiers.
The RF GMSK outputs from the transmit VCO are fed directly to the RF power amplifiers.
The peak output power and the profile of the transmitted burst are controlled by means of incorporated
power control circuits inside of PA and DAC output. from the Baseband Controller. The PA outputs
pass to the antenna connector via Antenna Switch.
IF
PLL
IF
PLL
Baseband
(TI)
U102
IOTA
+
U101
Calypso
(CO35)
Baseband
(TI)
U102
IOTA
+
U101
Calypso
(CO35)
13MHz
U505/Si4133T
RF1
RF2 IF
U506
VC-TCXO
IF_Lo(Tx)
RF_Lo(Tx)
RF_Lo(Rx)

Figure 3. RF Transmit Block
The baseband converter(BBC) within the GSM chipset generates I and Q baseband signals for the
Transmit vector modulator. The modulator provides more than 40dBc of carrier and unwanted side-
band. Rejection and produces a GMSK modulated signal. The baseband software is able to cancel out
differential DC offsets in the I/Q baseband signals caused by imperfections in the D/A converters.
The TX-Modulator implements a quadrature modulator. A quadrature mixer upconverts the differential
I/Q signals with the IFLO to generate a SSB IF signal, which is filtered and used as the reference input
to the OPLL. The Si4133T[U706] generates the IFLO frequency. The IFLO is divided by two to
generate the quadrature LO signals for the quadrature modulator.
3.2.6. IF Modulator
-17-
3.2.7. OPLL
The OPLL consists of a feedback mixer, a phase detector, a loop filter, and a fully integrated TXVCO.
The TXVCO is centered between the DCS 1800 and PCS 1900 bands, and its output is divided by 2
for the GSM 850 and E-GSM 900 bands. The Si4133T generates the RFLO frequency between 1327
and 1402 MHz. To allow a single VCO to be used for the RFLO, high-side injection is used for the
GSM 850 and E-GSM 900 bands, and low-side injection is used for the DCS 1800 and PCS 1900
bands. Low-pass filters before the OPLL phase detector reduce the harmonic content of the quadrature
modulator and feedback mixer outputs. The cutoff frequency of the filters is programmable with the
FIF[3:0] bits in register 04h. The OPLL requires no external duplexer to attenuate transmitter noise
and spurious signals in the receive band. Additionally, the output of the transmit VCO (TXVCO) is a
constant-envelope signal which reduces the problem of spectral spreading caused by non-linearity in
the PA.
Φ
DET
Φ
DET
÷2
÷2
D
I
P
D
I
PPAM
U504
RF3133
EGSM
DCS
I
Q
FL501
Antenna Switch
Baseband
(TI)
U102
IOTA
+
U101
Calypso
(CO35)
Baseband
(TI)
U102
IOTA
+
U101
Calypso
(CO35)
÷1
÷1
÷2
÷2
RF_Lo(Tx) IF_Lo(Tx)
PA_BAND
GATE_VC1
GATE_VC2

3.2.8. Power Amplifier
-18-
The RF3133 [U504] is a triple-band GSM/DCS/PCS power amplifier module that incorporates an
indirect closed loop method of power control. The indirect closed loop is fully self-contained and it
does not require loop optimization. It can be driven directly from the DAC output in the baseband
circuit. On-board power control provides over 37 dB of control range with an analog voltage input
(Vramp). Efficiency is 55% at GSM and 52% at DCS.
Figure 4. Power Amp
3.2.9. 13MHz Clock
The 13 MHz clock(U506) consists of a TCXO(Temperature Compensated Crystal Oscillator) which
oscillates at a frequency of 13 MHz. It is used within the Si4133T/Si4201 RF Main Chip, BB Analog
chip-set(IOTA), Digital chip-set(Calypso G2).
Figure 5. VC-TCXO Circuit

3.2.10. Power Supplies and Control Signals
An external regulator(U508) is used to provide DC power to RF part. Every RF component except
power amp module uses this external regulator.
Figure 6 External regulator Circuit
-19-

3.3 Digital Baseband (DBB) Processor
Figure 7. Top level block diagram of the Calypso G2(HERCROM400G2)
CALYPSO is a chip implementing the digital base-band processes of a GSM/GPRS mobile phone.
This chip combines a DSP sub-chip (LEAD2 CPU) with its program and data memories, a Micro- -
Controller core with emulation facilities (ARM7TDMIE), internal 8Kb of Boot ROM memory, 4M bit
SRAM memory, a clock squarer cell, several compiled single-port or 2-ports RAM and CMOS gates.
The chip will fully support the Full-Rate, Enhanced Full-Rate and Half-Rate speech coding.
CALYPSO implements all features for the structural test of the logic (full-SCAN, BIST, PMT, JTAG
boundary-SCAN).
3.3.1. General Description
-20-

CALYPSO architecture is based on two processor cores ARM7 and DSP using the generic RHEA bus
standard as interface with their associated application peripherals.
CALYPSO is composed from the following blocks:
• ARM7TDMIE : ARM7TDMI CPU core
• DSP subchip
• ARM peripherals:
3.3.2. Block Description
General purpose peripherals
• ARM Memory Interface for external RAM, Flash or ROM
• 4 Mbit Static RAM with write-buffer
Application peripherals
• ARM General purposes I/O with keyboard interface and two PWM modulation signals
• UART 16C750 interface (UART_IRDA) with
→IRDA control capabilities (SIR)
→Software flow control (UART mode).
• UART 16C750 interface (UART_MODEM) with
→Hardware flow protocol (DCD, CTS/RTS)
→Autobaud function
• SIM Interface.
• TPU(Time Processing Unit) : Processing for GSM time base
• TSP(Time Serial Port) : GSM data interface with RF and ABB
Memory Interface : External/Internal Memory Interface
nCS0 : FLASH1, 16bit access, 3 wait state
nCS1 : FLAHS2, 16bit access, 3 wait state
nCS2 : Ext SRAM, 16bit access, 3 wait state
nCS3 : Main LCD(16bit access), OEL(8bit access) addressing, 3 wait state
nCS4 : MIDI(8bit access), USB(8bit access) addressing, 3 wait state
nCS6 : Int SRAM, 32bit access, 0 wait state
* Calypso is internally 39MHz machine (25ns machine cycle), so it requires 3 wait-state for 80ns
access(25*4 = 100 ns).
-21-