LSI LS7280 User manual

BRUSHLESS DC MOTOR COMMUTATOR/CONTROLLER
FEATURES:
• Direct drive of P-Channel and N-Channel FETs (LS7280)
•Direct drive of PNP and NPN transistors (LS7282)
• Six outputs drive power switching bridge directly
•Open or closed loop motor speed control.
•+5V to +40V operation (VDD - VSS)
•Externally selectable input to output code for 60°,
120°, 240°, or 300° electrical sensor spacing.
• Three-phase or four-phase operation
•Analog Speed control
•Direction control
•Output Enable control
•Positive Static Braking
• Overcurrent Sensing
• LS7280, LS7282 (DIP); LS7280-S, LS7282-S (SOIC);
LS7280-TS, LS7282-TS (TSSOP)
- See Connection Diagram -
DESCRIPTION:
The LS7280/LS7282 are MOS integrated circuits de-
signed to generate the signals necessary to control a
three phase or four phase brushless DC motor. They
are the basic building blocks of a brushless DC motor
controller. The circuits respond to changes at the
SENSE inputs, originating at the motor position sensors,
to provide electronic commutation of the motor wind-
ings. Pulse Width Modulation of outputs for motor speed
control is accomplished through either the ENABLE in-
put or through the Analog input (VTRIP) in conjunction
with the OSCILLATOR input. Overcurrent circuitry is
provided to protect the windings, associated drivers and
power supply. The overcurrent circuitry causes the ex-
ternal output drivers to switch off immediately upon
sensing the overcurrent condition and on again only
when the overcurrent condition disappears and the pos-
itive edge of either the ENABLE input or the sawtooth
OSCILLATOR occurs. This limits the overcurrent sense
cycling to the chopping rate of the ENABLE input or the
sawtooth OSCILLATOR.
A positive braking feature is provided to effect rapid de-
celeration. While the LS7282 is designed for driving
NPN and PNP transistors (See Fig. 2), the LS7280 is
designed to drive both NMOS and PMOS Power FETs
and develops a full 12V drive for both the N-Channel
and P-Channel devices (See Fig. 1) when using a 12V
power supply.
LSI
CS1
OUT 1
OUT 2
OUT 3
OUT 4
COMMON
OUT 5
OUT 6
BRAKE
ENABLE
CS2
FWD/REV
V
SS (-V)
S3
S2
S1
OSCILLATOR
V TRIP
OVERCURRENT SENSE
V DD (+V)
CONNECTION DIAGRAM - TOP VIEW
1
2
3
4
5
6
7
8
9
10
20
11
12
13
14
15
16
17
18
19
INPUT/OUTPUT DESCRIPTION:
COMMUTATION SELECTS (Pins 1, 20)
These inputs are used to select the proper sequence of outputs
based on the electrical separation of the motor position sensors.
See Table 3. Note that in all cases the external output drivers
are disabled for invalid SENSE input codes. Internal pull down
resistors are provided at Pins 1 and 20 causing a logic zero
when these pins are left open.
FORWARD/REVERSE (Pin 19)
This input is used to select the proper sequence of Outputs for
the desired direction of rotation for the Motor (See Table 3). An
internal pull-up resistor holds the input high when left open.
SENSE INPUTS (Pins 15, 16, 17)
These inputs provide control of the output commutation
sequence as shown in Table 3. S1, S2, S3 originate in the posi-
tion sensors of the motor and must sequence in cycle code or-
der. Hall Switch pull-up resistors are provided at Pins 15, 16 and
17. The positive supply of the Hall devices should be common
to the chip VDD.
BRAKE (Pin 9)
For the LS7282, a high level at this input unconditionally turns
off Outputs 1, 2 and 3 and turns on Outputs 4, 5 and 6 (See Fig.
2). For the LS7280, a high level at this input turns on Outputs 1,
2 and 3 and Outputs 4, 5 and 6 (See Fig. 1). In both cases,
transistors Q101, Q102 and Q103 cut off and transistors Q104,
Q105 and Q106 turn on, shorting the windings together.
The BRAKE has priority over all other inputs.
7280-011705-1
LSI/CSI
LSI ComputerSystems,Inc.1235WaltWhitman Road,Melville,NY11747(631)271-0400FAX [phone]
LS7280
LS7282
UL
®
A3800 January 2005
- PRELIMINARY -

BRAKE (Pin 9)
An internal pull-down resistor holds the input low when left
open. (Center- tapped motor configuration requires a power
supply disconnect transistor controlled by the BRAKE signal
- See Figure 2A).
ENABLE (Pin 10)
A high level at this input permits the output to sequence as
in Table 3, while a low disables all external output drivers.
An internal pull-up resistor holds the input high when left
open. Positive edges at this input will reset the overcurrent
flip-flop.
OVERCURRENT SENSE (Pin 12)
This input provides the user a way of protecting the motor
winding, drivers and power supply from an overload condi-
tion. The user provides a fractional-ohm resistor between
the negative supply and the common emitters of the NPN
drivers or common sources of N-Channel FET drivers. This
point is connected to one end of a potentiometer (e.g. 100k
ohms), the other end of which is connected to the positive
supply. The wiper pickoff is adjusted so that all outputs are
disabled for currents greater than the limit. The action of the
input is to disable all external output drivers. When BRAKE
exists, OVERCURRENT SENSE will be overridden. The
overcurrent circuitry latches the overcurrent condition. The
latch may be reset by the positive edge of either the saw-
tooth OSCILLATOR or the ENABLE input. When using the
ENABLE input as a chopped input, the OSC input should be
held at VDD. When the ENABLE input is held high, the OSC-
must be used to reset the overcurrent latch.
VTRIP (Pin 13)
This input is used in conjunction with the sawtooth OSC in-
put. When the voltage level applied to VTRIP is more neg-
ative than the waveform at the OSC input, the Outputs will
be enabled as shown in Table 3. When VTRIP is more pos-
itive than the sawtooth OSCILLATOR waveform the external
output drivers are disabled.
The sawtooth waveform at the OSC input typically varies
approximately from 0.4VDD to VDD - 2V. The purpose of
the VTRIP input in conjunction with the OSCILLATOR is to
provide variable speed adjustment for the motor by means
of PWM.
OSCILLATOR (Pin 14)
An R and C connected to this input (See Figure 6) provide
the timing components for a sawtooth OSCILLATOR. The
signal generated is used in conjunction with VTRIP to pro-
vide PWM for variable speed applications and to reset the
overcurrent condition.
OUTPUTS 1, 2, 3 (Pins 2, 3, 4)
For the LS7282, these open drain Outputs are enabled as
shown in Table 3 and provide base current to PNP tran-
sistors or gate drive to P-Channel FET drivers when COM-
MON is floating. If COMMON is held at VDD, these Out-
puts can provide drive to NPN transistors or N-Channel
FET drivers. For the LS7280, these Outputs provide drive
to P-Channel FET drivers if COMMON is held at VDD.
OUTPUTS 4, 5, 6 (Pins 6, 7, 8)
These open drain Outputs are enabled as in Table 3 and
provide base current to NPN transistors or gate drive to
N-Channel FET drivers.
COMMON (Pin 5)
The COMMON may be connected to VDD when using a
center-tapped motor configuration or when using all NPN
or N-Channel drivers. For the LS7280, the COMMON is
tied to VDD.
VDD (Pin 11)
Supply voltage positive terminal.
VSS (Pin 18)
Supply voltage negative terminal (ground).
MAXIMUM RATINGS:
PARAMETER SYMBOL VALUE UNIT
DC Supply Voltage VDD - VSS +40 V
Any Input Voltage to VSS Vin +40 to -0.5 V
Storage Temperature TSTG -65 to +150 °C
Operating Temperature TA -25 to +125 °C
DC ELECTRICAL CHARACTERISTICS:
(All Voltages Referenced to VDD, TA= 25°C unless otherwise specified)
SYMBOL MIN TYP MAX UNIT
Supply Voltage VDD 5 - 40 V
Supply Current (Outputs not loaded) IDD - 1.5 3 mA
7280-121604-2
Input Specifications:
BRAKE, ENABLE, CS1, CS2 RIN - 150 - kΩ
S1, S2, S3, FWD/REV
Voltage (Logic1) VIH VDD - 1.5 - VDD V
(Logic 0) VIL 0 - VDD - 4.0 V
Voltage (Logic1) VIH VDD - 1.0 - VDD V
(Logic 0) VIL 0 - VDD - 4.0 V
Voltage (Logic 1) VIH VDD - 1.5 - VDD V
(Logic 0) VIL 0 - VDD - 6.0 V
OVERCURRENT SENSE (See Note)
Threshold Voltage VTH (VDD/2) - 0.25 - (VDD/2) + 0.25 V
9 ≤VDD ≤24
VDD > 24
VDD < 9
}
}
}

TABLE 2
For Power Supply 5V to 40V
R1 (k ohms) Output Voltage
6.8 VDD - 0.5
3.3 VDD - 1.0
1.8 VDD - 2.0
TYPICAL CIRCUIT OPERATION:
The oscillator is used for motor speed control as explained
under VTRIP. Both upper and lower motor drive transistors are
pulse width modulated (See Fig. 1 or 2) during speed control.
For the LS7282, the outputs turn on in pairs (See Table 3). For
example (See dotted line, Fig. 2): Q8 and Q4 are on, thus ena-
bling a path from the positive supply through the emitter-base
junction of Q101, Q8, Q4, R5, the base emitter junction of
Q105 and the fractional-ohm resistor to ground. The current in
the above described path is determined by the power supply
voltage, the voltage drops across the base-emitter junctions of
Q101 and Q105 (1.4V for single transistor or 2.8V for Darling-
ton pairs), the impedance of Q8 and Q4 and the value of R5.
Table 1 provides the recommended value for R5. R4 and R6
are the same value.
7280-011705-3
Oscillator:
Frequency Range Fosc 0 1/RC 100 kHz
External Resistor Range Rosc 22 - 1000 kΩ
NOTE: Theoretical switching point of the OVERCURRENT SENSE input is one half of the power supply determined by an internal bias
network in manufacturing. Tolerances cause the switching point to vary plus or minus 0.25V. After manufacture, the switching point
remains fixed within 10mV over time and temperature. The input switching sensivity is a maximum of 50mV. There is no hysteresis on
the OVERCURRENT SENSE input.
TABLE 3. OUTPUT COMMUTATION SEQUENCE FOR THREE-PHASE OPERATION
SEQUENCE SELECT CS1 CS2 CS1 CS2 CS1 CS2 CS1 CS2 FWD/REV = 1 FWD/REV = 0
0 0 0 1 1 0 1 1
ELECTRICALSEPARATION (-60°-) (-120°-) (-240°-) (-300°-) OUTPUTS DRIVERS OUTPUTS DRIVERS
SENSEINPUTS S1 S2 S3 S1 S2 S3 S1 S2 S3 S1 S2 S3 ENABLED A B C ENABLED A B C
0 0 0 0 0 1 0 1 0 0 1 1 O1, O5 + - Off O2, O4 - + Off
1 0 0 1 0 1 1 1 0 1 1 1 O3, O5 Off - + O2, O6 Off + -
1 1 0 1 0 0 1 0 0 1 1 0 O3, O4 - Off + O1, O6 + Off -
1 1 1 1 1 0 1 0 1 1 0 0 O2, O4 - + Off O1, O5 + - Off
0 1 1 0 1 0 0 0 1 0 0 0 O2, O6 Off + - O3, O5 Off - +
0 0 1 0 1 1 0 1 1 0 0 1 O1, O6 + Off - O3, O4 - Off +
0 1 0 0 0 0 0 0 0 0 1 0 ALL DISABLED ALL DISABLED
1 0 1 1 1 1 1 1 1 1 0 1 ALL DISABLED ALL DISABLED
The OVERCURRENT input (BRAKE low) enables external output drivers in normal sequence when more negative than VDD/2 and disables
all external output drivers when more positive than VDD/2. The OVERCURRENT is sensed continuously, and sets a flip flop which is reset
by the rising edge of the ENABLE input or the sawtooth OSCILLATOR. (See description under OVERCURRENT SENSE.)
The VTRIP Input (BRAKE low) enables the outputs in normal sequence when more negative than the OSC input and disables all outputs
when more positive than the OSC input. The VTRIP input may be disabled by connecting it to VSS and the OSC input to VDD.
(See description under VTRIP)
For the LS7280, (See Fig.1) the external drivers also turn
on in pairs. Internal operation is somewhat different than
the LS7282. For example, external transistors Q101 and
Q105 will turn on when internal transistor Q8 turns off
and Q4 turns on enabling full power supply drive on
Q101 and Q105. Since Pin 5 is tied to VDD, the gate of P-
channel Driver Q101 is brought to ground by R1 and the
Gate of N-Channel driver Q105 is brought to VDD by Q4.
Other external output pairs turn on similarly and the
commutation sequence is identical to that of the LS7282
(Table 3). Table 2 indicates the minimum value of
R1 (= R2 = R3 = R4 = R5 = R6) needed as a function of
output drive voltage for Fig. 1.
* * *
*
*
See Figures 1 and 2.
For the LS7280,
Outputs O1, O2, O3 are
the logical inversions of
the corresponding Out-
puts of the LS7282.
20mA 15mA 10mA 7.5mA 5mA 2.5mA 2mA 1.5mA
6V ** ** ** ** ** ** ** 1.3k
9V ** ** ** ** 0.62k 2.4k 3.3k 4.3k
12V ** ** 0.43k 1k 1.8k 3.9k 4.7k 6.2k
15V ** 0.47k 1k 1.6k 2.4k 5.1k 6.2k 8.2k
18V 0.15k 0.82k 1.5k 1.8k 3k 6.2k 7.5k 10k
21V 0.75k 1.1k 1.8k 2.4k 3.6k 7.5k 9.1k 12k
24V 0.91k 1.3k 2k 2.7k 4.3k 8.2k 11k 13k
28V 1.2k 1.6k 2.4k 3.3k 5.1k 10k 13k 16k
32V 1.3k 1.8k 2.7k 3.9k 5.6k 12k 15k 20k
36V 1.6k 2k 3.3k 4.3k 6.8k 13k 16k 22k
40V 1.8k 2.4k 3.6k 4.7k 7.5k 15k 18k 24k
** Exceeds maximum current possible for this voltage
TABLE 1. OUTPUT CURRENT LIMITING RESISTOR SELECTION TABLE

6
Output
Encoder
7
8
5
4
3
2
Q106Q105Q104
AL1 BL2
L3
Q103Q102Q101
R1
Q6
Q7
Q8
Q3Q4Q5
Fractional
Ohm
Resistor
TO
OVERCURRENT
ADJUSTMENT
VDD
VDD
O4
O5
O6
O3
O2
O1
M
O
T
O
R
FIGURE 1. LS7280 THREE PHASE OUTPUT DRIVER CIRCUITRY
C
R2 R3
NNN
PPP
R4 R5 R6
12
6
12
Output
Encoder
7
8
5
4
3
2
Q106
Q105
Q104
AL1 BL2
L3
Q103
Q102Q101
R1
R6
R5
R4
Q6
Q7
Q8
Q3Q4Q5
BRAKE
11
Fractional
Ohm
Resistor
TO OVERCURRENT
ADJUSTMENT
Direction of Current Flow
O4
O5
O6
O3
O2
O1
M
O
T
O
R
FIGURE 2. LS7282 THREE PHASE OUTPUT DRIVER CIRCUITRY
C
R2 R3
R7 R8 R9
VDD
VDD
7280-121504-4

TABLE 4. OUTPUT COMMUTATION SEQUENCE FOR FOUR-PHASE OPERATION
CS1 = CS2 = 0 OUTPUTS ENABLED
S1 S2,S3 FWD/REV = 1 FWD/REV = 0
0 0 O1 O4
1 0 O3 O6
1 1 O4 O1
0 1 O6 O3
7280-121504-5
BRAKE
MOTOR
SUPPLY
O6 8
5
COMMON
BRAKE
INPUT
7
O4 6
9
O5
LS7282
V
DD
FIGURE 2A.
SINGLE-ENDED
DRIVER CIRCUIT
This configuration requires only
one base current limiting resistor
connected from the COMMON
pin to VDD.
For four-phase commutation (See Fig. 3), the COMMUTA-
TION SELECT inputs must both be tied low. The S1 input
is driven from one motor position sensor while the S2 and
S3 inputs are connected together and driven by the
second position sensor. The COMMON input must be
connected to VDD. The sensors have an electrical
separation of 90°. Figure 3A indicates the use of Bipolar
Transistors. Figure 3B indicates the use of FETs. In both
cases, the LS7282 is used.
COMMON
BRAKE INPUT
MOTOR SUPPLY
BRAKE
VDD
OVERCURRENT
SENSE
L4
L3
L2
L1
V
DD
FIGURE 3A
5
9
2
4
6
8
12
O1
O3
O4
O6
LS7282
BRAKE
COMMON
OVERCURRENT
SENSE
VDD
VDD
12
5
9
2
4
6
8
L4
L3
L2
L1
BRAKE
MOTOR SUPPLY
O1
O3
O4
O6
FIGURE 3B
LS7282
FIGURE 3. FOUR-PHASE OUTPUT DRIVER CIRCUITRY
The information included herein is believed to be
accurate and reliable. However, LSI Computer Systems,
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.

V
DD
-
+
13 V TRIP
OSCILLATOR
R6
R2
C1
S1
R1
15
VDD
C3
V
DD
R3
R4 R5
D1
C2
VDD
R8
LS7280
or
LS7282
FROM MOTOR
POSITION
SENSOR
14
C4
R7
FIGURE 4
CLOSED-LOOP SPEED CONTROLLER
A closed loop system can be configured by differentiating
one of the motor position sense inputs and integrating only
the negative pulses to form a DC voltage that is applied to
the inverting input of an op-amp. The non-inverting input
voltage is adjusted with a potentiometer until the resultant
voltage at VTRIP causes the motor to run at desired
speed. The R2-C1 differentiator, the R3-D1 negative pulse
transmitter and the R4-C2 integrator form a frequency to
voltage converter. An increase in motor speed above the
desired speed causes VTRIP to increase which lowers the
PWM and the resultant motor speed. A decrease in speed
lowers VTRIP and raises the PWM and the resultant mo-
tor speed. For proper operation, both R5 and R6 should
be greater than R4, and R4 in turn should be greater than
both R2 and R3. Also, the R4-C2 time constant should be
greater than the R2-C1 time constant. C3 may be added
across R6 for additional VTRIP smoothing.
7280-121504-6
OUTPUT
DRIVERS
OUTPUT
ENCODER
INPUT
DECODER
SAWTOOTH
OSCILLATOR
-
+
COMMUTATION
SEQUENCE
SELECT LOGIC 5
6
8
11 VDD
18 VSSGND
COMMON
4
+V
1
20
19
15
16
17
9
10
12
13
14
CS1
CS2
FWD/REV
S1
S2
S3
BRAKE
ENABLE
OVERCURRENT
SENSE
V TRIP
.001µF
33K
+V
+V
FIGURE 5. LS7280 AND LS7282 BLOCK DIAGRAM
R
R
+V
2
3
4
6
7
8
O1
O2
O3
O4
O5
O6
+
-
R
S
Q
POSITIVE
EDGE
DETECTOR
NOTE : With indicated components,
oscillator frequency is approximately 30KHz.
POSITIVE EDGE
DETECTOR