LSI LSISAS1068 User manual

®
DB14-000287-03
LSISAS1068 PCI-X to
8-Port Serial Attached
SCSI/SATA Controller
TECHNICAL
MANUAL
February 2005
Version 2.0

ii Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
Document DB14-000287-03, Version 2.0 (February 2005)
This document describes the LSI Logic Corporation’s LSISAS1068 Serial
Attached SCSI Controller and will remain the official reference source for all
revisions/releases of this product until rescinded by an update.
LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.
Purchase of I2C components of LSI Logic Corporation, or one of its sublicensed
Associated Companies, conveys a license under the Philips I2C Patent Rights to
use these components in an I2C system, provided that the system conforms to
the I2C standard Specification as defined by Philips.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
LSI Logic, the LSI Logic logo design, Fusion-MPT, Gflx, GigaBlaze,
Integrated Mirroring, Integrated RAID, and Integrated Striping are trademarks or
registered trademarks of LSI Logic Corporation. ARM and Multi-ICE are
registered trademarks of ARM Ltd., used under license. CompactPCI is a
registered trademark of the PCI Industrial Computer Manufacturers Group. All
other brand and product names may be trademarks of their respective
companies.
DB
To receive product literature, visit us at http://www.lsilogic.com.
For a current list of our distributors, sales offices, and design resource
centers, view our web page located at
http://www.lsilogic.com/contacts/index.html

LSISAS1068 PCI-X to 8-Port Serial Attached SCSI/SATA Controller iii
Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Preface
This book is the primary reference and technical manual for the
LSISAS1068 PCI-X to 8-Port Serial Attached SCSI/SATA Controller. It
contains a complete functional description for the LSISAS1068, as well
as the physical and electrical specifications for the LSISAS1068.
Audience
This document assumes that you are familiar with microprocessors and
related support devices. The people who benefit from this book are:
•Engineers and managers who are evaluating the LSISAS1068 for
use in a system
•Engineers who are designing the LSISAS1068 into a system
Organization
This document has the following chapters and appendixes:
•Chapter 1, Introduction, provides an overview of the LSISAS1068
features and capabilities.
•Chapter 2, Functional Description, provides a detailed functional
description of the LSISAS1068 operation. This chapter describes the
LSISAS1068 implementations of the PCI, PCI-X, and SAS
specifications.
•Chapter 3, Signal Description, provides a detailed signal
description for the LSISAS1068.
•Chapter 4, PCI Host Register Description, provides a bit level
description of the host interface registers.
•Chapter 5, Specifications, provides the electrical and physical
specifications for the LSISAS1068.

iv Preface
Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
•Appendix A, Register Summary, provides a register map for the
LSISAS1068.
•Appendix B, Reference Specifications, lists several specifications
that may benefit the reader.
Related Publications
LSI Logic Documents
Fusion-MPT™ Device Management User’s Guide, Version 2.0,
DB15-000186-02
LSI Logic World Wide Web Home Page
www.lsilogic.com
ANSI
11 West 42nd Street
New York, NY 10036
[phone]
InterNational Committee on Information Technology Standards
(INCITS) T10 Technical Committee
http://www.t10.org
Global Engineering Documents
15 Inverness Way East
Englewood, CO 80112
[phone] or [phone] (outside U.S.) FAX [phone]
PCI Special Interest Group
2575 N. E. Katherine
Hillsboro, OR 97214
[phone]; [phone] (International); FAX [phone]
Serial ATA Working Group
http://www.serialata.org
Email: [e-mail]
Philips I2C Bus Specification
http://www.semiconductors.philips.com
SFF-8485 Serial GPIO Bus Specification
http://www.sffcommittee.org

Preface v
Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Conventions Used in This Manual
The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive. Signals that are active
LOW end with a “/.”
Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.
Revision History
Revision Date Remarks
Advance Version 0.2 7/2004 Initial release of document.
Advance Version 0.3 7/2004 Pin AC6 changed in Figure 5.4.
Version 1.0 1/2005 Preliminary Release. Modified text regarding IM and IS drive sup-
port (page 1-4); identified throughout the Manual that the
LSISAS1068 PCI interface is not tolerant of 5V PCI; corrected
typo on page 3-2 regarding 636 Ball Grid Array; changed accu-
racy requirement for Reference Clock signal to +/- 50ppm (Table
3.9); corrected typo in Mode Select bus description (Table 3.13)
to “0b000000”; corrected two typos in value of Subsystem ID reg-
ister to 0x9000 (pages 4-13 and 4-14); added statement “The
LSISAS1068 sets this register to 0x0A...” to Maximum Latency
register description (page 4-17); updated Write I/O Key descrip-
tion (page 4-34) to include an additional write of “0x00FF” at
beginning of sequence; updated Operating Conditions (Table 5-2);
provided GigaBlaze characteristics (Tables 5.3 to 5.5); provided
External Memory Timing Diagrams (Section 5.3). Various addi-
tional editorial changes throughout document.
Version 2.0 2/2005 Final Release. Added references to Philips I2C and SFF-8485
Serial GPIO bus specifications on page iv. Clarified support for
SAS and SATA features in Section 1.1. Changed description of
MAD[29] in Table 3.16 to “Reserved”. Changed ESD specification
in Table 5.2 from TBD to 2000 V.

vi Preface
Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.

Contents vii
Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Contents
Chapter 1
Introduction 1.1 General Description 1-1
1.2 Benefits of SAS 1-5
1.3 Benefits of the Fusion-MPT Architecture 1-5
1.4 Benefits of PCI-X 1-6
1.5 Benefits of GigaBlaze®Transceivers 1-7
1.6 Summary of LSISAS1068 Features 1-8
1.6.1 SAS Features 1-8
1.6.2 SATA Features 1-8
1.6.3 PCI Performance 1-9
1.6.4 Integration 1-10
1.6.5 Usability 1-10
1.6.6 Flexibility 1-10
1.6.7 Reliability 1-11
1.6.8 Testability 1-11
Chapter 2
Functional Description
2.1 Block Diagram Description 2-2
2.1.1 Host Interface Module Description 2-4
2.1.2 Quad Port 2-6
2.1.3 Context RAM 2-8
2.2 Fusion-MPT Architecture Overview 2-8
2.3 PCI Functional Description 2-9
2.3.1 PCI Addressing 2-9
2.3.2 PCI Commands and Functions 2-11
2.3.3 PCI Arbitration 2-16
2.3.4 PCI Cache Mode 2-16

viii Contents
Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
2.3.5 PCI Interrupts 2-16
2.3.6 Power Management 2-17
2.4 SAS Functional Description 2-17
2.5 External Memory Interface 2-20
2.5.1 Memory Requirements 2-20
2.5.2 Flash ROM Controller 2-21
2.5.3 NVSRAM Controller 2-23
2.6 Serial EEPROM Interface 2-24
2.7 Zero Channel RAID 2-25
2.8 Universal Asynchronous Receiver/Transmitter (UART) 2-26
2.9 Multi-ICE Test Interface 2-27
Chapter 3
Signal Description3.1 Signal Organization 3-1
3.2 PCI Signals 3-4
3.2.1 PCI System Signals 3-4
3.2.2 PCI Address and Data Signals 3-4
3.2.3 PCI Interface Control Signals 3-5
3.2.4 PCI Arbitration Signals 3-5
3.2.5 PCI Error Reporting Signals 3-5
3.2.6 PCI Interrupt Signals 3-6
3.3 PCI-Related Signals 3-6
3.4 CompactPCI Signals 3-7
3.5 SAS Signals 3-7
3.6 Memory Interface Signals 3-8
3.7 Communication Signals 3-9
3.8 SIO Signals 3-10
3.9 Configuration and General Purpose Signals 3-11
3.10 JTAG and Test Signals 3-12
3.11 Power Signals 3-13
3.12 Power-On Sense Pins Description 3-15
3.13 Internal Pull-Ups and Pull-Downs 3-18
Chapter 4
PCI Host Register Description
4.1 PCI Configuration Space Register Description 4-1

Contents ix
Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
4.2 PCI I/O Space and Memory Space Register Description 4-32
Chapter 5
Specifications 5.1 DC Characteristics 5-1
5.2 AC Characteristics 5-9
5.2.1 Reset and Interrupt Timing 5-10
5.3 External Memory Timing Diagrams 5-11
5.4 Pinout 5-17
5.5 Package Drawings 5-24
Appendix A
Register Summary
Appendix B
Reference Specifications
Index
Customer Feedback

x Contents
Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.

Contents xi
Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Figures 1.1 LSISAS1068 Direct-Connect Example Application 1-3
1.2 LSISAS1068 Controller and LSISASx12 Expander Example
Application 1-3
2.1 LSISAS1068 Controller Block Diagram 2-3
2.2 Transceivers within a Phy 2-18
2.3 Narrow and Wide Links 2-19
2.4 SSP, STP, and SMP Protocol Usage 2-20
2.5 Flash ROM Block Diagram 2-22
2.6 NVSRAM Block Diagram 2-23
2.7 ZCR Circuit Diagram for the LSISAS1068 2-26
3.1 LSISAS1068 Functional Signal Grouping 3-3
5.1 External Clock 5-9
5.2 Reset Input 5-10
5.3 Interrupt Output 5-10
5.4 Flash Write, 1 FlashAddrCs, 7 FlashCSWidth,
2 FlashWrRecover (Always only one Written) 5-11
5.5 Flash Read, 0 FlashAddrCs, 7 FlashCSWidth,
1 FlashRdRecover (4 Bytes always Read) 5-12
5.6 Flash Read, 1 FlashAddrCs, 7 FlashCSWidth,
2 FlashRDRecover (4 Bytes always Read) 5-13
5.7 NV Read, 0 NVAddrCs, 7 NVCSWidth, 1 NVRdRecover
(Bytes Read as Selected by BEs) 5-14
5.8 NV Read, 1 NVAddrCs, 7 NVCSWidth, 2 NVRdRecover
(Bytes Read as Selected by BEs) 5-15
5.9 NV Write, 1 NVAddrCs, 7 NVCSWidth, 2 NVWrRecover
(Bytes Written as Selected by BEs 5-16
5.10 LSISAS1068 636 EPBGA-T Diagram (Top View) 5-23
5.11 JZ02-000015-00 (5Y) Mechanical Drawing 5-25

xii Contents
Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.

Contents xiii
Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Tables 2.1 PCI/PCI-X Bus Commands and Encodings 2-11
2.2 Flash ROM Signature Value 2-22
2.3 Serial EEPROM Structure 2-24
2.4 ARM Multi-ICE Header Pinout 2-27
3.1 PCI System Signals 3-4
3.2 PCI Address and Data Signals 3-4
3.3 PCI Interface Control Signals 3-5
3.4 PCI Arbitration Signals 3-5
3.5 PCI Error Reporting Signals 3-5
3.6 PCI Interrupt Signals 3-6
3.7 PCI-Related Signals 3-6
3.8 CompactPCI Signals 3-7
3.9 SAS Interface Signals 3-7
3.10 Memory Interface Signals 3-8
3.11 Serial EEPROM and I2C Signals 3-9
3.12 SIO Signals 3-10
3.13 Configuration and General Purpose Signals 3-11
3.14 Test and JTAG Signals 3-12
3.15 Power and Ground Signals 3-13
3.16 Power-On Sense Pin Definitions 3-16
3.17 Pull-Up and Pull-Down Conditions 3-18
4.1 LSISAS1068 PCI Configuration Space Address Map 4-2
4.2 Subsystem ID Register Download Conditions and Values 4-14
4.3 Multiple Message Enable Field Bit Encoding 4-22
4.4 BIR Field Definitions 4-26
4.5 Maximum Outstanding Split Transactions 4-28
4.6 Maximum Memory Read Count 4-29
4.7 PCI I/O Space Address Map 4-32
4.8 PCI Memory [0] Address Map 4-33
4.9 PCI Memory [1] Address Map 4-33
4.10 Interrupt Signal Routing 4-39
5.1 Absolute Maximum Stress Ratings 5-2
5.2 Operating Conditions 5-2
5.3 GigaBlaze Transmitter Voltage Characteristics—TX[7:0] 5-3
5.4 GigaBlaze Receiver Voltage Characteristics—RX[7:0] 5-3
5.5 GigaBlaze Transceiver Rise/Fall Characteristics—TX[7:0],

xiv Contents
Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
RX[7:0] 5-3
5.6 PCI-X Input Signals—CLK, RST/, GNT/, IDSEL, ALT_GNT/,
CPCI64_EN/ 5-4
5.7 PCI-X Output Signals—REQ/, INTA/, ALT_INTA/ 5-4
5.8 PCI-X Bidirectional Signals—AD[63:0], C_BE[7:0]/,
CPCI_ENUM/, PAR, PAR64, ACK64/, REQ64/, FRAME/,
IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, SERR/ 5-4
5.9 Inputs—ZCR_EN/, CPCI_EN/, TN/, UART_RX 5-4
5.10 Inputs—CPCI_SWITCH, MODE[5:0], SCAN_ENABLE,
SCAN_MODE, FSEL_A 5-5
5.11 Schmitt Trigger Inputs—TST_RST/, TCK, TRST/, TDI, TMS,
TCK_ICE, TRST_ICE/, TDI_ICE, TMS_ICE 5-5
5.12 Schmitt Trigger Inputs—REFCLK_B, SIO_DIN_A,
SIO_DIN_B 5-5
5.13 10 mA, 3-State Outputs—CPCI_LED/, HB_LED/ 5-5
5.14 5 mA, 3-State Outputs—TDO, TDO_ICE, RTCK_ICE,
SIO_CLK_A, SIO_CLK_B, SIO_DOUT_A, SIO_DOUT_B,
SIO_END_A, SIO_END_B 5-6
5.15 8 mA Outputs—MCLK, ADSC/, ADV/, BWE[3:0]/,
MWE[1:0]/, MOE[1:0]/, PSBRAM_CS/, FLASH_CS/,
NVSRAM_CS/ 5-6
5.16 5 mA Outputs—UART_TX 5-6
5.17 4 mA Outputs—PROCMON 5-6
5.18 8 mA Bidirectional Signals—MAD[31:0] 5-7
5.19 8 mA Bidirectional Signals—MADP[3:0] 5-7
5.20 5 mA Bidirectional Signals—SERIAL_CLK, SERIAL_DATA,
ISTWI_CLK, ISTWI_DATA, GPIO[3:0], FAULT_LED[7:0]/,
ACTIVE_LED[7:0]/ 5-7
5.21 PECL Buffer Signals—REFCLK_P, REFCLK_N 5-8
5.22 Capacitance 5-8
5.23 External Clock 5-9
5.24 Reset Input 5-10
5.25 Interrupt Output 5-10
5.26 Listing by Signal Name 5-17
5.27 Listing by Pin Number 5-20
A.1 LSISAS1068 PCI Configuration Space Registers A-1
A.2 LSISAS1068 PCI I/O Space Registers A-3
A.3 LSISAS1068 PCI Memory [0] Space Registers A-4
B.1 Reference SpecifIcations B-1

LSISAS1068 PCI-X to 8-Port Serial Attached SCSI/SATA Controller 1-1
Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Chapter 1
Introduction
The LSISAS1068 is an eight-port, 3.0 Gbit/s SAS/SATA controller that is
compliant with the Fusion-MPT™architecture, provides a PCI-X
interface, and supports the Integrated RAID™solution. This chapter
contains the following sections:
•Section 1.1, “General Description”
•Section 1.2, “Benefits of SAS”
•Section 1.3, “Benefits of the Fusion-MPT Architecture”
•Section 1.4, “Benefits of PCI-X”
•Section 1.5, “Benefits of GigaBlaze® Transceivers”
•Section 1.6, “Summary of LSISAS1068 Features”
1.1 General Description
The LSISAS1068 controller brings 3.0 Gbit/s Serial Attached SCSI (SAS)
performance to host adapter, workstation, and server designs, making it
easy to add a SAS interface to any PCI or PCI-X1system. The
LSISAS1068 integrates eight high-performance SAS/SATA phys and a
64-bit, 133 MHz PCI-X bus master DMA core. Each of the eight phys on
the LSISAS1068 is capable of 3.0 Gbit/s and 1.5 Gbit/s SAS link rates,
and 3.0 Gbit/s and 1.5 Gbit/s SATA link rates. The LSISAS1068 supports
the SAS protocol as described in the Serial Attached SCSI Standard,
version 1.0, as well as SAS 1.1 features, such as support for the
BROADCAST (SES) primitive and support for SATA port selectors. The
controller also supports the Serial ATA (SATA) protocol defined by the
1. In some instances, this manual references PCI-X explicitly. References to the PCI bus may
be inclusive of both the PCI specification and PCI-X addendum, or may only refer to the PCI
bus depending on the operating mode of the device.

1-2 Introduction
Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Serial ATA specification, version 1.0a. SATA II is an extension to SATA
1.0a. LSI Logic SAS/SATA controllers also support the following SATA II
features:
•3 Gbit/s SATA
•Staggered spin-up
•Hot Plug
•Native Command Queuing
•Activity and fault indicators per phy
•Port Selector (for dual-port drives)
Supporting both the SAS and SATA interfaces, the LSISAS1068 is a
versatile controller that provides the backbone of both server and high-
end workstation environments. LSI Logic produces the LSISAS1068
using the Gflx™process technology.
Each port on the LSISAS1068 supports SAS and SATA devices using the
SAS Serial SCSI Protocol (SSP), Serial Management Protocol (SMP),
Serial Tunneling Protocol (STP), and SATA. The SSP protocol enables
communication with other SAS devices. SATA enables the LSISAS1068
to communicate with other SATA devices. The SMP protocol
communicates topology management information directly with an
attached SAS expander device, such as the LSISASx12. STP enables
the LSISAS1068 to communicate with a SATA device through an
attached expander.
The LSISAS1068 supports a 133 MHz, 64-bit PCI-X bus. With the
exception that the PCI interface is not tolerant of 5 V PCI, the interface
is backward compatible with previous revisions of the PCI/PCI-X bus. The
LSISAS1068 supports PCI-X split completion cycles and 32-bit or 64-bit
data bursts with variable burst length. The LSISAS1068 supports the
PCI-X Addendum to the Peripheral Components Interface Specification,
Revision 2.0, and the Peripheral Components Interface Specification,
Revision 3.0.
Figure 1.1 shows a direct-connect configuration. Figure 1.2 provides an
example of the LSISAS1068 configured with an LSISASx12 expander.

General Description 1-3
Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Figure 1.1 LSISAS1068 Direct-Connect Example Application
Figure 1.2 LSISAS1068 Controller and LSISASx12 Expander
Example Application
Flash ROM/
LSISAS1068
64-Bit, 133 MHz
PCI-X
SAS/SATA Device 32-bit Memory
Address/Data
Bus PSBRAM/
Tx , Rx
I
2
C
SAS/SATA Device Tx , Rx
SAS/SATA Device Tx , Rx
SAS/SATA Device Tx , Rx
PCI/PCI-X Interface
NVSRAM
Controller I
2
C
Interface
LSISAS1068
LSISASx12
Flash ROM/
32-bit Memory
Address/Data
Bus PSBRAM/
I
2
C
NVSRAM
LSISASx12
SAS/SATA
Drives
PCI/PCI-X Interface
SAS/SATA
Drives SAS/SATA
Drives
SAS/SATA
Drives
I
2
C
Interface

1-4 Introduction
Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
The LSISAS1068 employs an ARM966 processor to meet the data
transfer flexibility requirements of the host interface PCI-X specifications.
The LSISAS1068 is based on the Fusion-MPT (Message Passing
Technology) architecture, which features a performance based message
passing protocol that off loads the host CPU by completely managing all
I/Os and minimizes system bus overhead by coalescing interrupts. The
Fusion-MPT architecture requires only a thin, easy to develop device
drivers that is independent of the I/O bus. LSI Logic provides these
device drivers.
The LSISAS1068 supports a 32-bit external memory bus and a standard
serial EEPROM interface. The external memory controller block provides
an interface for Flash ROM, NVSRAM, and PSBRAM devices. Typical
system configurations do not require a serial EEPROM. Most
configurations use a Flash ROM to store firmware, configuration
information, and persistent data information.
The LSISAS1068 supports the Integrated RAID solution, which is a
highly integrated, low cost RAID implementation. It is designed for
systems requiring redundancy and high availability, but not needing a full-
featured RAID implementation. The Integrated RAID solution includes
Integrated Mirroring™(IM) technology and Integrated Striping™(IS)
technology. IM provides physical mirroring of two physical drives. IM
requires an NVSRAM to support write journaling. IS enables data striping
across up to eight physical drives. The Integrated RAID solution is OS
independent, easy to install and configure, supports up to eight drives at
RAID Level 0, and does not require a special driver. The runtime
operation of the Integrated RAID solution is transparent to the operating
system. A single firmware build supports all Integrated RAID capabilities.
The LSISAS1068 also provides Zero Channel RAID (ZCR) support.
The IR firmware requires a configuration mechanism, which enables
configuration of the mirroring attributes during initial setup or
reconfiguration after hardware failures or changes in the system
environment. Use the LSI Logic BIOS Configuration Utility or the IM DOS
Configuration Utility to configure the IR firmware attributes. Host based
status software monitors the state of the mirrored drives and reports error
conditions as they arise.

Benefits of SAS 1-5
Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
1.2 Benefits of SAS
SAS is a serial, point-to-point, enterprise-level device interface that
leverages the proven SCSI protocol set. SAS is a convergence of the
advantages of SATA, SCSI, and FC, and is the future mainstay of the
enterprise and high-end workstation storage markets. SAS offers a
higher bandwidth per pin than parallel SCSI, and improves signal and
data integrity.
The SAS interface uses the proven SCSI command set to ensure reliable
data transfers, while providing the connectivity and flexibility of point-to-
point serial data transfers. The serial transmission of SCSI commands
eliminates clock skew challenges. The SAS interface provides improved
performance, simplified cabling, smaller connectors, lower pin count, and
lower power requirements when compared to parallel SCSI.
SAS controllers leverage a common electrical and physical connection
interface that is compatible with Serial ATA technology. The SAS and
SATA protocols use a thin, 7-wire connector instead of the 68-wire SCSI
cable or 26-wire ATA cable. The SAS/SATA connector and cable are
easier to manipulate, allow connections to smaller devices, and do not
inhibit airflow. The point-to-point SATA architecture eliminates inherent
difficulties created by the legacy ATA master-slave architecture, while
maintaining compatibility with existing ATA firmware.
The LSISAS1068 can function as an SSP initiator, an SSP target, an
SMP initiator, an STP initiator, or a SATA initiator. The LSISAS1068 uses
SSP to communicate with other SAS devices, and uses SMP to
communicate topology management information with other SAS devices.
STP communicates with SATA devices by tunneling through SAS
expanders directly to the SATA device or by using the SATA protocol to
communicate directly with the SATA device.
1.3 Benefits of the Fusion-MPT Architecture
The Fusion-MPT architecture provides an open architecture that is ideal
for SAS, SATA, SCSI, Fibre Channel, and other emerging interfaces. The
I/O interface is interchangeable at the system and application level;
embedded software uses the same device interface for different bus

1-6 Introduction
Version 2.0 Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
implementations, just as application software uses the same storage
management interfaces for different bus implementations. LSI Logic
provides Fusion-MPT device drivers that are binary compatible between
SAS, SATA, Fibre Channel, and Ultra320 SCSI interfaces.
The Fusion-MPT architecture improves overall system performance by
requiring only a thin device driver, which off loads the intensive work of
managing I/Os from the system processor to the LSISAS1068. The use
of thin, easy to develop, common OS device drivers accelerates time to
market by reducing device driver development and certification times.
The Fusion-MPT architecture provides an interrupt coalescing feature.
Interrupt coalescing allows an I/O controller to send multiple reply
messages in a single interrupt to the host processor. Sending multiple
reply messages per interrupt reduces context switching of the host
processor and maximizes the host processor efficiency, which results in
a significant improvement of system performance. To use the interrupt
coalescing feature, the host processor must be able to accept and
manage multiple replies per interrupt.
The Fusion-MPT architecture also provides built-in device driver stability
since the device driver need not change for each revision of the
LSISAS1068 silicon or firmware. This architecture is a reliable, constant
interface between the host device driver and the LSISAS1068. Changes
within the LSISAS1068 are transparent to the host device driver,
operating system, and user. The Fusion-MPT architecture also saves the
user significant development and maintenance effort since it is not
necessary to alter or redevelop the device driver when a revision of the
LSISAS1068 device or firmware occurs.
1.4 Benefits of PCI-X
PCI-X doubles the maximum clock frequency of the conventional PCI
bus. The PCI-X Addendum to the PCI Local Bus Specification,
Revision 2.0, defines enhancements to the proven PCI Local Bus
Specification, Revision 3.0. PCI-X provides more efficient data transfers
by enabling registered inputs and outputs, improves buffer management
by including transaction information with each data transfer, and reduces
bus overhead by restricting the use of wait states and disconnects. PCI-X