LSI LSI53C895A User manual

®
S14028.B
LSI53C895A
PCI to Ultra2
SCSI Controller
TECHNICAL
MANUAL
April 2001
Version 2.2

ii
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.
Document DB14-000089-03, Fourth Edition (April 2001)
This document describes the LSI Logic LSI53C895A PCI to Ultra2 SCSI
Controller and will remain the official reference source for all revisions/releases
of this product until rescinded by an update.
To receive product literature, visit us at http://www.lsilogic.com.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.
Ultra SCSI is the term used by the SCSI Trade Association (STA) to describe
Fast-20 SCSI, as documented in the SCSI-3 Fast-20 Parallel Interface standard,
X3,277-199X.
Ultra2 SCSI is the term used by the SCSI Trade Association (STA) to describe
Fast-40 SCSI, as documented in the SCSI Parallel Interface-2 standard, (SPI-2)
X3710-1142D.
Copyright © 1998–2001 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design, TolerANT, LVDlink, and SCRIPTS are registered
trademarks or trademarks of LSI Logic Corporation. All other brand and product
names may be trademarks of their respective companies.
SR/HH

Preface iii
Preface
This book is the primary reference and technical manual for the
LSI53C895A PCI to Ultra2 SCSI Controller. It contains a complete
functional description for the product and also includes complete physical
and electrical specifications.
Audience
This manual provides reference information on the LSI53C895A PCI to
Ultra2 SCSI Controller. It is intended for system designers and
programmers who are using this device to design an Ultra2 SCSI port for
PCI-based personal computers, workstations, servers or embedded
applications.
Organization
This document has the following chapters and appendixes:
•Chapter 1, General Description,includes general information about
the LSI53C895A.
•Chapter 2, Functional Description, describes the main functional
areas of the chip in more detail, including interfaces to the SCSI bus
and external memory.
•Chapter 3, Signal Descriptions, contains pin diagrams and signal
descriptions.
•Chapter 4, Registers, describes each bit in the operating registers,
and is organized by register address.
•Chapter 5, SCSI SCRIPTS Instruction Set, defines all of the SCSI
SCRIPTS instructions that are supported by the LSI53C895A.

iv Preface
•Chapter 6, Electrical Specifications, contains the electrical
characteristics and AC timing diagrams.
•Appendix A, Register Summary, is a register summary.
•Appendix B, External Memory Interface Diagram Examples,
contains several example interface drawings for connecting the
LSI53C895A to external ROMs.
Related Publications
For background information, please contact:
ANSI
11 West 42nd Street
New York, NY 10036
[phone]
Ask for document number X3.131-199X (SCSI-2)
Global Engineering Documents
15 Inverness Way East
Englewood, CO 80112
[phone] or [phone] (outside U.S.) FAX [phone]
Ask for document number X3.131-1994 (SCSI-2); X3.253
(SCSI-3 Parallel Interface)
ENDL Publications
14426 Black Walnut Court
Saratoga, CA 95070
[phone]
Document names: SCSI Bench Reference, SCSI Encyclopedia,
SCSI Tutor
Prentice Hall
113 Sylvan Avenue
Englewood Cliffs, NJ 07632
[phone]
Ask for document number ISBN 0-13-796855-8, SCSI: Understanding
the Small Computer System Interface

Preface v
LSI Logic World Wide Web Home Page
www.lsilogic.com
PCI Special Interest Group
2575 N.E. Katherine
Hillsboro, OR 97214
[phone]; [phone] (International); FAX [phone]
Conventions Used in This Manual
The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive.
Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.
Revision Record
Revision Date Remarks
0.5 4/99 Advance information version of the manual.
1.0 7/99 Preliminary version of the manual.
1.1 9/99 PCI timings corrected in Chapter 6, Table 6.3, and Figure 6.41 corrected.
2.0 2/00 Final version.
2.1 7/00 Added Figure 6.43.
2.2 4/01 All product names changed from SYM to LSI. Updated DC electrical
specifications and test conditions.

vi Preface

Contents vii
Contents
Chapter 1 General Description
1.1 New Features in the LSI53C895A 1-3
1.2 Benefits of Ultra2 SCSI 1-4
1.3 Benefits of LVDlink 1-4
1.4 TolerANT®Technology 1-5
1.5 LSI53C895A Benefits Summary 1-6
1.5.1 SCSI Performance 1-6
1.5.2 PCI Performance 1-7
1.5.3 Integration 1-8
1.5.4 Ease of Use 1-8
1.5.5 Flexibility 1-9
1.5.6 Reliability 1-9
1.5.7 Testability 1-10
Chapter 2 Functional Description
2.1 PCI Functional Description 2-2
2.1.1 PCI Addressing 2-2
2.1.2 PCI Bus Commands and Functions Supported 2-4
2.1.3 PCI Cache Mode 2-9
2.2 SCSI Functional Description 2-18
2.2.1 SCRIPTS Processor 2-19
2.2.2 Internal SCRIPTS RAM 2-20
2.2.3 64-Bit Addressing in SCRIPTS 2-21
2.2.4 Hardware Control of SCSI Activity LED 2-21
2.2.5 Designing an Ultra2 SCSI System 2-22
2.2.6 Prefetching SCRIPTS Instructions 2-23
2.2.7 Opcode Fetch Burst Capability 2-24
2.2.8 Load and Store Instructions 2-24
2.2.9 JTAG Boundary Scan Testing 2-25

viii Contents
2.2.10 SCSI Loopback Mode 2-26
2.2.11 Parity Options 2-26
2.2.12 DMA FIFO 2-29
2.2.13 SCSI Bus Interface 2-34
2.2.14 Select/Reselect During Selection/Reselection 2-39
2.2.15 Synchronous Operation 2-40
2.2.16 Interrupt Handling 2-43
2.2.17 Interrupt Routing 2-50
2.2.18 Chained Block Moves 2-51
2.3 Parallel ROM Interface 2-55
2.4 Serial EEPROM Interface 2-57
2.4.1 Default Download Mode 2-57
2.4.2 No Download Mode 2-58
2.5 Alternative SSVID/SSID Loading Mechanism 2-58
2.6 Power Management 2-60
2.6.1 Power State D0 2-61
2.6.2 Power State D1 2-61
2.6.3 Power State D2 2-62
2.6.4 Power State D3 2-62
Chapter 3 Signal Descriptions
3.1 LSI53C895A Functional Signal Grouping 3-2
3.2 Signal Descriptions 3-3
3.2.1 Internal Pull-ups on LSI53C895A Signals 3-3
3.3 PCI Bus Interface Signals 3-4
3.3.1 System Signals 3-4
3.3.2 Address and Data Signals 3-5
3.3.3 Interface Control Signals 3-6
3.3.4 Arbitration Signals 3-8
3.3.5 Error Reporting Signals 3-8
3.3.6 Interrupt Signals 3-9
3.3.7 SCSI GPIO Signals 3-10
3.4 SCSI Bus Interface Signals 3-11
3.4.1 SCSI Bus Interface Signal 3-11
3.4.2 SCSI Signals 3-12
3.4.3 SCSI Control Signals 3-13
3.5 Flash ROM and Memory Interface Signals 3-14

Contents ix
3.6 Test Interface Signals 3-16
3.7 Power and Ground Signals 3-17
3.8 MAD Bus Programming 3-19
Chapter 4 Registers
4.1 PCI Configuration Registers 4-1
4.2 SCSI Registers 4-19
4.3 64-Bit SCRIPTS Selectors 4-104
4.4 Phase Mismatch Jump Registers 4-108
Chapter 5 SCSI SCRIPTS Instruction Set
5.1 Low Level Register Interface Mode 5-1
5.2 High Level SCSI SCRIPTS Mode 5-2
5.2.1 Sample Operation 5-3
5.3 Block Move Instruction 5-5
5.3.1 First Dword 5-6
5.3.2 Second Dword 5-12
5.4 I/O Instruction 5-13
5.4.1 First Dword 5-13
5.4.2 Second Dword 5-21
5.5 Read/Write Instructions 5-22
5.5.1 First Dword 5-22
5.5.2 Second Dword 5-23
5.5.3 Read-Modify-Write Cycles 5-23
5.5.4 Move To/From SFBR Cycles 5-24
5.6 Transfer Control Instructions 5-26
5.6.1 First Dword 5-26
5.6.2 Second Dword 5-32
5.7 Memory Move Instructions 5-32
5.7.1 First Dword 5-33
5.7.2 Read/Write System Memory from SCRIPTS 5-34
5.7.3 Second Dword 5-34
5.7.4 Third Dword 5-35
5.8 Load and Store Instructions 5-35
5.8.1 First Dword 5-36
5.8.2 Second Dword 5-37

xContents
Chapter 6 Electrical Specifications
6.1 DC Characteristics 6-1
6.2 TolerANT Technology Electrical Characteristics 6-8
6.3 AC Characteristics 6-12
6.4 PCI and External Memory Interface Timing Diagrams 6-14
6.4.1 Target Timing 6-15
6.4.2 Initiator Timing 6-22
6.4.3 External Memory Timing 6-39
6.5 SCSI Timing Diagrams 6-56
6.6 Package Diagrams 6-64
6.6.1 LSI53C895A vs. LSI53C895 Pin/Ball Differences 6-71
Appendix A Register Summary
Appendix B External Memory Interface Diagram Examples
Index
Customer Feedback
Figures 1.1 Typical LSI53C895A System Application 1-2
1.2 Typical LSI53C895A Board Application 1-3
2.1 LSI53C895A Block Diagram 2-2
2.2 Parity Checking/Generation 2-29
2.3 DMA FIFO Sections 2-30
2.4 LSI53C895A Host Interface SCSI Data Paths 2-31
2.5 8-Bit HVD Wiring Diagram for Ultra2 SCSI 2-37
2.6 Regulated Termination for Ultra2 SCSI 2-39
2.7 Determining the Synchronous Transfer Rate 2-41
2.8 Block Move and Chained Block Move Instructions 2-52
3.1 LSI53C895A Functional Signal Grouping 3-2
5.1 SCRIPTS Overview 5-5
6.1 LVD Driver 6-3
6.2 LVD Receiver 6-4

Contents xi
6.3 Rise and Fall Time Test Condition 6-9
6.4 SCSI Input Filtering 6-9
6.5 Hysteresis of SCSI Receivers 6-10
6.6 Input Current as a Function of Input Voltage 6-10
6.7 Output Current as a Function of Output Voltage 6-11
6.8 External Clock 6-12
6.9 Reset Input 6-13
6.10 Interrupt Output 6-14
6.11 PCI Configuration Register Read 6-16
6.12 PCI Configuration Register Write 6-17
6.13 32-Bit Operating Register/SCRIPTS RAM Read 6-18
6.14 64-Bit Address Operating Register/SCRIPTS RAM Read 6-19
6.15 32-Bit Operating Register/SCRIPTS RAM Write 6-20
6.16 64-Bit Address Operating Register/SCRIPTS RAM Write 6-21
6.17 Nonburst Opcode Fetch, 32-Bit Address and Data 6-23
6.18 Burst Opcode Fetch, 32-Bit Address and Data 6-25
6.19 Back to Back Read, 32-Bit Address and Data 6-27
6.20 Back to Back Write, 32-Bit Address and Data 6-29
6.21 Burst Read, 32-Bit Address and Data 6-31
6.22 Burst Read, 64-Bit Address and Data 6-33
6.23 Burst Write, 32-Bit Address and Data 6-35
6.24 Burst Write, 64-Bit Address and 32-Bit Data 6-37
6.25 External Memory Read 6-40
6.26 External Memory Write 6-44
6.27 Normal/Fast Memory (≥128 Kbytes) Single Byte
Access Read Cycle 6-46
6.28 Normal/Fast Memory (≥128 Kbytes) Single Byte
Access Write Cycle 6-47
6.29 Normal/Fast Memory (≥128 Kbytes) Multiple Byte
Access Read Cycle 6-48
6.30 Normal/Fast Memory (≥128 Kbytes) Multiple Byte
Access Write Cycle 6-50
6.31 Slow Memory (≤128 Kbytes) Read Cycle 6-52
6.32 Slow Memory (≤128 Kbytes) Write Cycle 6-53
6.33 ≤64 Kbytes ROM Read Cycle 6-54
6.34 ≤64 Kbyte ROM Write Cycle 6-55
6.35 Initiator Asynchronous Send 6-56
6.36 Initiator Asynchronous Receive 6-57

xii Contents
6.37 Target Asynchronous Send 6-58
6.38 Target Asynchronous Receive 6-59
6.39 Initiator and Target Synchronous Transfer 6-63
6.40 LSI53C895A 272-Pin BGA Top View 6-65
6.41 LSI53C895A 208-Pin Plastic Quad Flat Pack 6-68
6.42 LSI53C895A 208 PQFP Mechanical Drawing
(Sheet 1 of 2) 6-74
6.43 LSI53C895A 272 PBGA Mechanical Drawing 6-76
B.1 16KbyteInterfacewith200nsMemory B-1
B.2 64KbyteInterfacewith150nsMemory B-2
B.3 128 Kbytes, 256 Kbytes, 512 Kbytes, or 1 Mbyte
Interface with 150 ns Memory B-3
B.4 512 Kbyte Interface with 150 ns Memory B-4
Tables 2.1 PCI Bus Commands and Encoding Types for the
LSI53C895A 2-4
2.2 PCI Cache Mode Alignment 2-13
2.3 Bits Used for Parity Control and Generation 2-27
2.4 SCSI Parity Control 2-28
2.5 SCSI Parity Errors and Interrupts 2-28
2.6 HVD Signals 2-35
2.7 Parallel ROM Support 2-56
2.8 Mode A Serial EEPROM Data Format 2-58
2.9 Power States 2-61
3.1 LSI53C895A Internal Pull-ups 3-3
3.2 System Signals 3-4
3.3 Address and Data Signals 3-5
3.4 Interface Control Signals 3-6
3.5 Arbitration Signals 3-8
3.6 Error Reporting Signals 3-8
3.7 Interrupt Signals 3-9
3.8 SCSI GPIO Signals 3-10
3.9 SCSI Bus Interface Signal 3-11
3.10 SCSI Signals 3-12
3.11 SCSI Control Signals 3-13
3.12 Flash ROM and Memory Interface Signals 3-14
3.13 Test Interface Signals 3-16

Contents xiii
3.14 Power and Ground Signals 3-17
3.15 Decode of MAD Pins 3-20
4.1 PCI Configuration Register Map 4-2
4.2 SCSI Register Address Map 4-20
4.3 Examples of Synchronous Transfer Periods and Rates
for SCSI-1 4-33
4.4 Example Transfer Periods and Rates for Fast SCSI-2,
Ultra, and Ultra2 4-34
4.5 Maximum Synchronous Offset 4-35
4.6 SCSI Synchronous Data FIFO Word Count 4-45
5.1 SCRIPTS Instructions 5-3
5.2 SCSI Information Transfer Phase 5-11
5.3 Read/Write Instructions 5-24
5.4 Transfer Control Instructions 5-26
5.5 SCSI Phase Comparisons 5-29
6.1 Absolute Maximum Stress Ratings 6-2
6.2 Operating Conditions 6-2
6.3 LVD Driver SCSI Signals—SD[15:0]+, SDP[1:0]/, SREQ/,
SREQ2/, SACK/, SACK2/, SMSG/, SIO/, SCD/, SATN/,
SBSY/, SSEL/, SRST/ 6-3
6.4 LVD Receiver SCSI Signals—SD[15:0]/, SDP[1:0]/,
SREQ/, SREQ2/, SACK/, SACK2/, SMSG/, SIO/, SCD/,
SATN/, SBSY/, SSEL/, SRST/ 6-3
6.5 DIFFSENS SCSI Signal 6-4
6.6 Input Capacitance 6-4
6.7 Bidirectional Signals—MAD[7:0], MAS/[1:0], MCE/,
MOE/, MWE/ 6-5
6.8 Bidirectional Signals—GPIO0_FETCH/,
GPIO1_MASTER/, GPIO[2:8] 6-5
6.9 Bidirectional Signals—AD[31:0], C_BE[3:0]/, FRAME/,
IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR 6-6
6.10 InputSignals—CLK,GNT/,IDSEL,RST/,SCLK,TCK,
TDI, TEST_HSC, TEST_RST, TMS, TRST/ 6-6
6.11 Output Signal—TDO 6-7
6.12 Output Signals—ALT_IRQ/, IRQ/, MAC/_TESTOUT,
REQ/ 6-7
6.13 Output Signal—SERR/ 6-7
6.14 TolerANT Technology Electrical Characteristics for SE
SCSI Signals 6-8

xiv Contents
6.15 External Clock 6-12
6.16 Reset Input 6-13
6.17 Interrupt Output 6-14
6.18 PCI Configuration Register Read 6-16
6.19 PCI Configuration Register Write 6-17
6.20 32-Bit Operating Register/SCRIPTS RAM Read 6-18
6.21 64-Bit Address Operating Register/SCRIPTS RAM Read 6-19
6.22 32-Bit Operating Register/SCRIPTS RAM Write 6-20
6.23 64-Bit Address Operating Register/SCRIPTS RAM Write 6-21
6.24 Nonburst Opcode Fetch, 32-Bit Address and Data 6-22
6.25 Burst Opcode Fetch, 32-Bit Address and Data 6-24
6.26 Back to Back Read, 32-Bit Address and Data 6-26
6.27 Back to Back Write, 32-Bit Address and Data 6-28
6.28 Burst Read, 32-Bit Address and Data 6-30
6.29 Burst Read, 64-Bit Address and Data 6-32
6.30 Burst Write, 32-Bit Address and Data 6-34
6.31 Burst Write, 64-Bit Address and 32-Bit Data 6-36
6.32 External Memory Read 6-39
6.33 External Memory Write 6-43
6.34 Normal/Fast Memory (≥128 Kbytes) Single Byte Access
Read Cycle 6-46
6.35 Normal/Fast Memory (≥128 Kbytes) Single Byte Access
Write Cycle 6-47
6.36 Slow Memory (≤128 Kbytes) Read Cycle 6-52
6.37 Slow Memory (≤128 Kbytes) Write Cycle 6-53
6.38 ≤=64 Kbytes ROM Read Cycle 6-54
6.39 ≤64 Kbyte ROM Write Cycle 6-55
6.40 Initiator Asynchronous Send 6-56
6.41 Initiator Asynchronous Receive 6-57
6.42 Target Asynchronous Send 6-58
6.43 Target Asynchronous Receive 6-59
6.44 SCSI-1 Transfers (SE 5.0 Mbytes) 6-59
6.45 SCSI-1 Transfers (Differential 4.17 Mbytes) 6-60
6.46 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or
20.0 Mbytes (16-Bit Transfers) 40 MHz Clock 6-60
6.47 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or
20.0 Mbytes (16-Bit Transfers) 50 MHz Clock 6-61

Contents xv
6.48 Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers) or
40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock 6-61
6.49 Ultra SCSI High Voltage Differential Transfers 20.0 Mbytes
(8-Bit Transfers) or 40.0 Mbytes (16-Bit Transfers) 80 MHz
Clock 6-62
6.50 Ultra2 SCSI Transfers 40.0 Mbytes (8-Bit Transfers) or
80.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock 6-63
6.51 272 BGA Pin List by Location 6-66
6.52 BGA Pin List Alphabetically 6-67
6.53 Signal Names vs. Pin Number: 208-Pin Plastic Quad
Flat Pack 6-69
6.54 LSI53C895A vs. LSI53C895 Pin/Ball Differences 6-72
A.1 LSI53C895A PCI Register Map A-1
A.2 LSI53C895A SCSI Register Map A-2

xvi Contents

LSI53C895A PCI to Ultra2 SCSI Controller 1-1
Chapter 1
General Description
Chapter 1 is divided into the following sections:
•Section 1.1, “New Features in the LSI53C895A”
•Section 1.2, “Benefits of Ultra2 SCSI”
•Section 1.3, “Benefits of LVDlink”
•Section 1.4, “TolerANT® Technology”
•Section 1.5, “LSI53C895A Benefits Summary”
The LSI53C895A PCI to Ultra2 SCSI Controller brings Ultra2 SCSI
performance to host adapter, workstation, and general computer designs,
making it easy to add a high-performance SCSI bus to any PCI system.
It supports Ultra2 SCSI transfer rates and allows increased SCSI
connectivity and cable length with Low Voltage Differential (LVD)
signaling for SCSI devices. The LSI53C895A is packaged in a
208 Plastic Quad Flat Pack (PQFP) and a 272 Ball Grid Array (BGA).
The LSI53C895A can be used as a drop-in replacement for the
LSI53C895.
The LSI53C895A has a local memory bus for local storage of the
device’s BIOS ROM in flash memory or standard EEPROMs. The
LSI53C895A supports programming of local flash memory for updates to
BIOS. Appendix B, “External Memory Interface Diagram Examples,” has
system diagrams showing the connections of the LSI53C895A with an
external ROM or flash memory.
LVDlink™ technology is the LSI Logic implementation of LVD. LVDlink
transceivers allow the LSI53C895A to perform either Single-Ended (SE)
or LVD transfers. It also supports external High Voltage Differential (HVD)
transceivers. The LSI53C895A integrates a high-performance SCSI core,
a 64-bit PCI bus master DMA core, and the LSI Logic SCSI SCRIPTS™
processor to meet the flexibility requirements of SCSI-3 and Ultra2 SCSI

1-2 General Description
standards. It implements multithreaded I/O algorithms with a minimum of
processor intervention, solving the protocol overhead problems of
previous intelligent and nonintelligent adapter designs.
Figure 1.1 illustrates a typical LSI53C895A system and Figure 1.2
illustrates a typical LSI53C895A board application.
Figure 1.1 Typical LSI53C895A System Application
PCI Bus
Interface
Controller
LSI53C895A
PCItoWideUltra2
SCSI Controller
PCI Graphic Accelerator
PCI Fast Ethernet
Memory
Controller
Memory
Fixed Disk, Optical Disk
Printer, Tape, and Other
Peripherals
Central
Processing
Unit
(CPU)
PCI Bus
Processor Bus
Typical PCI
Computer System
Architecture
SCSI Bus

New Features in the LSI53C895A 1-3
Figure 1.2 Typical LSI53C895A Board Application
1.1 New Features in the LSI53C895A
The LSI53C895A is a drop-in replacement for the LSI53C895 PCI to
Ultra2 SCSI Controller, with these additional benefits:
•Supports 32-bit PCI Interface with 64-bit addressing.
•Handles SCSI phase mismatches in SCRIPTS without interrupting
the CPU.
•Supports JTAG boundary scanning.
•Supports RAID ready alternative interrupt signaling.
•Supports PC99 Power Management.
– Automatically downloads Subsystem Vendor ID, Subsystem ID,
and PCI power management levels D0, D1, D2, and D3.
•Improves PCI bus efficiency through improved PCI caching design.
•Transfers Load/Store data to or from 8 Kbytes of internal SCRIPTS
RAM.
68 Pin
SCSI
Wide
Connector
LSI53C895A
32-Bit PCI to
SCSI Controller
Memory Control
Block
Flash EEPROM
Serial EEPROM
PCI Interface
PCI Address, Data, Parity and Control Signals
SCSI Data,
Parity and
Control
Signals
Memory
Address/Data
Bus
GPIO[1:0]

1-4 General Description
Additional features of the LSI53C895A include:
•Hardware control of SCSI activity LED.
•Nine GPIO Pins.
•32-bit ISTAT registers (Interrupt Status Zero (ISTAT0),Interrupt
Status One (ISTAT1),Mailbox Zero (MBOX0), and Mailbox One
(MBOX1)).
•Optional 944 byte DMA FIFO supports large block transfers at Ultra2
SCSI speeds. The default FIFO size of 112 bytes is also supported.
1.2 Benefits of Ultra2 SCSI
Ultra2 SCSI is an extension of the SPI-2 draft standard that allows faster
synchronous SCSI transfer rates. It also defines a new physical layer,
LVD SCSI, that provides an incremental evolution from SCSI-2 and Ultra
SCSI. When enabled, Ultra2 SCSI performs 40 megatransfers per
second, resulting in approximately twice the synchronous transfer rates
of Ultra SCSI. The LSI53C895A can perform 16-bit, Ultra2 SCSI
synchronous transfers as fast as 80 Mbytes/s. This advantage is most
noticeable in heavily loaded systems or with applications with large block
requirements, such as video on-demand and image processing.
An advantage of Ultra2 SCSI is that it significantly improves SCSI
bandwidth while preserving existing hardware and software investments.
The primary software changes required enable the chip to perform
synchronous negotiations for Ultra2 SCSI rates and to enable the clock
quadrupler. Ultra2 SCSI uses the same connectors as Ultra SCSI, but
can operate with longer cables and more devices on the bus.
Chapter 2, “Functional Description,” contains more information on
migrating an Ultra SCSI design to support Ultra2 SCSI.
1.3 Benefits of LVDlink
The LSI53C895A supports LVD for SCSI. This signaling technology
increases the reliability of SCSI data transfers over longer distances than
are supported by SE SCSI. The low current output of LVD allows the I/O
transceivers to be integrated directly onto the chip. LVD provides the
reliability of HVD SCSI without the added cost of external differential