LSI LSI53C1030 User manual

®
DB14-000156-04
LSI53C1030 PCI-X to
Dual Channel Ultra320
SCSI Multifunction
Controller
TECHNICAL
MANUAL
June 2003
Version 2.1

ii Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.
Document DB14-000156-04, Version 2.1 (June 2003)
This document describes LSI Logic Corporation’s LSI53C1030 PCI-X to
Dual Channel Ultra320 SCSI Multifunction Controller and will remain the official
reference source for all revisions/releases of this product until rescinded by an
update.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.
Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
LSI Logic, the LSI Logic logo design, Fusion-MPT, Integrated Mirroring, LVDlink,
SDMS, SureLINK, and TolerANT are trademarks or registered trademarks of LSI
Logic Corporation. ARM and Multi-ICE are registered trademarks of ARM Ltd.,
used under license. Windows is a registered trademarks of Microsoft
Corporation. NetWare is a registered trademarks of Novell Corporation. Linux is
a registered trademark of Linus Torvalds. Solaris is a trademark of Sun
Microsystems, Inc. SCO Openserver is a trademark of Caldera International, Inc.
UnixWare is a trademark of The Open Group. All other brand and product names
may be trademarks of their respective companies
AP
To receive product literature, visit us at http://www.lsilogic.com.
For a current list of our distributors, sales offices, and design resource
centers, view our web page located at
http://www.lsilogic.com/contacts/index.html

LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller iii
Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Preface
This book is the primary reference and technical manual for the
LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction
Controller. It contains a functional description for the LSI53C1030 and
the physical and electrical specifications for the LSI53C1030.
Audience
This document assumes that you have some familiarity with
microprocessors and related support devices. The people who benefit
from this book are:
•Engineers and managers who are evaluating the LSI53C1030 for
use in a system
•Engineers who are designing the LSI53C1030 into a system
Organization
This document has the following chapters and appendixes:
•Chapter 1, Introduction, provides an overview of the LSI53C1030
features and capabilities.
•Chapter 2, Functional Description, provides a detailed functional
description of the LSI53C1030 operation. This chapter describes
how the LSI53C1030 implements the PCI, PCI-X, and SCSI bus
specifications.
•Chapter 3, Signal Description, provides a detailed signal
description for the LSI53C1030.
•Chapter 4, PCI Host Register Description, provides a bit level
description of the host register set of the LSI53C1030.

iv Preface
Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
•Chapter 5, Specifications, provides the electrical and physical
specifications for the device.
•Appendix A, Register Summary, provides a register map for the
LSI53C1030.
Related Publications
LSI Logic Documents
Fusion-MPT Device Management User’s Guide, Version 2.0,
DB15-000186-02
LSI Logic World Wide Web Home Page
www.lsilogic.com
ANSI
11 West 42nd Street
New York, NY 10036
[phone]
Global Engineering Documents
15 Inverness Way East
Englewood, CO 80112
[phone] or [phone] (outside U.S.) FAX [phone]
ENDL Publications
14426 Black Walnut Court
Saratoga, CA 95070
[phone]
Document names: SCSI Bench Reference, SCSI Encyclopedia, SCSI
Tutor
Prentice Hall
113 Sylvan Avenue
Englewood Cliffs, NJ 07632
[phone]
Ask for document number ISBN 0-13-796855-8, SCSI: Understanding
the Small Computer System Interface
SCSI Electronic Bulletin Board
[phone]

Preface v
Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
PCI Special Interest Group
2575 N. E. Katherine
Hillsboro, OR 97214
[phone]; [phone] (International); FAX [phone]
Conventions Used in This Manual
The first time a word or phrase is defined in this manual, it is italicized.
The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive. Signals that are active
LOW end with a “/.”
Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.
Revision History
Revision Date Remarks
Version 2.1 6/2003 Updated the external memory timing diagrams.
Updated the default Subsystem ID value.
Updated the ZCR behavior description.
Updated the Multi-ICE test interface description.
Version 2.0 4/2002 Added register summary appendix.
Updated the electrical characteristics.
Updated the Index.
Preliminary
Version 1.0 12/2001 Updated the description of Fusion-MPT architecture in Chapter 1. Updated External Memory Interface descriptions in Chapter 2.
Added Test Interface description to Chapter 2.
Added Zero Channel RAID interface description to Chapters 2 and 3.
Updated the MAD Power-On Sense pin description in Chapter 3.
Updated signal descriptions and lists to include the ZCR-related pins.
Updated electrical and environmental characteristics in Chapter 5.
Removed figures relating to SE SCSI electrical and timing characteristics
from Chapter 5.
Removed SCSI timing information from Chapter 5 and referred readers to
the SCSI specification.
Removed PSBRAM interface and all related information.
Advance
Version 0.1 2/2001 Initial release of document.

vi Preface
Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller vii
Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Contents
Chapter 1
Introduction 1.1 General Description 1-1
1.2 Benefits of the Fusion-MPT Architecture 1-5
1.3 Benefits of PCI-X 1-6
1.4 Benefits of Ultra320 SCSI 1-6
1.5 Benefits of SureLINK (Ultra320 SCSI Domain Validation) 1-7
1.6 Benefits of LVDlink Technology 1-8
1.7 Benefits of TolerANT®Technology 1-8
1.8 Summary of LSI53C1030 Features 1-9
1.8.1 SCSI Performance 1-9
1.8.2 PCI Performance 1-10
1.8.3 Integration 1-11
1.8.4 Flexibility 1-11
1.8.5 Reliability 1-12
1.8.6 Testability 1-12
Chapter 2
Functional Description
2.1 Block Diagram Description 2-2
2.1.1 Host Interface Module Description 2-3
2.1.2 SCSI Channel Module Description 2-6
2.2 Fusion-MPT Architecture Overview 2-6
2.3 PCI Functional Description 2-7
2.3.1 PCI Addressing 2-8
2.3.2 PCI Commands and Functions 2-9
2.3.3 PCI Arbitration 2-15
2.3.4 PCI Cache Mode 2-15
2.3.5 PCI Interrupts 2-15

viii Contents
Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
2.3.6 Power Management 2-16
2.4 Ultra320 SCSI Functional Description 2-18
2.4.1 Ultra320 SCSI Features 2-18
2.4.2 SCSI Bus Interface 2-23
2.5 External Memory Interface 2-24
2.5.1 Flash ROM Interface 2-24
2.5.2 NVSRAM Interface 2-26
2.6 Serial EEPROM Interface 2-27
2.7 Zero Channel RAID 2-28
2.8 Multi-ICE Test Interface 2-30
Chapter 3
Signal Description3.1 Signal Organization 3-2
3.2 PCI Bus Interface Signals 3-4
3.2.1 PCI System Signals 3-4
3.2.2 PCI Address and Data Signals 3-5
3.2.3 PCI Interface Control Signals 3-6
3.2.4 PCI Arbitration Signals 3-7
3.2.5 PCI Error Reporting Signals 3-7
3.2.6 PCI Interrupt Signals 3-8
3.3 PCI-Related Signals 3-9
3.4 SCSI Interface Signals 3-10
3.4.1 SCSI Channel [0] Signals 3-10
3.4.2 SCSI Channel [1] Signals 3-13
3.5 Memory Interface 3-14
3.6 Zero Channel RAID Interface 3-16
3.7 Test Interface 3-17
3.8 GPIO and LED Signals 3-19
3.9 Power and Ground Pins 3-20
3.10 Power-On Sense Pins Description 3-21
3.11 Internal Pull-ups and Pull-downs 3-25
Chapter 4
PCI Host Register Description
4.1 PCI Configuration Space Register Description 4-1
4.2 PCI I/O Space and Memory Space Register Description 4-29

Contents ix
Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Chapter 5
Specifications 5.1 DC Characteristics 5-1
5.2 TolerANT Technology Electrical Characteristics 5-7
5.3 AC Characteristics 5-9
5.4 External Memory Timing Diagrams 5-11
5.4.1 NVSRAM Timing 5-12
5.4.2 Flash ROM Timing 5-16
5.5 Package Drawings 5-20
Appendix A
Register Summary
Index
Customer Feedback

xContents
Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

xi
Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Figures 1.1 Typical LSI53C1030 Board Application 1-3
1.2 Typical LSI53C1030 System Application 1-4
2.1 LSI53C1030 Block Diagram 2-3
2.2 Paced Transfer Example 2-20
2.3 Example of Precompensation 2-21
2.4 Flash ROM Block Diagram 2-25
2.5 NVSRAM Diagram 2-27
2.6 ZCR Circuit Diagram for LSI53C1030 and LSI53C1010R 2-29
3.1 LSI53C1030 Functional Signal Grouping 3-3
5.1 LVD Driver 5-3
5.2 LVD Receiver 5-4
5.3 Rise and Fall Time Test Condition 5-8
5.4 SCSI Input Filtering 5-9
5.5 External Clock 5-10
5.6 Reset Input 5-10
5.7 Interrupt Output 5-11
5.8 NVSRAM Read Cycle 5-13
5.8 NVSRAM Read Cycle (Cont.) 5-13
5.9 NVSRAM Write Cycle 5-15
5.9 NVSRAM Write Cycle (Cont.) 5-15
5.10 Flash ROM Read Cycle 5-17
5.10 Flash ROM Read Cycle (Cont.) 5-17
5.11 Flash ROM Write Cycle 5-19
5.11 Flash ROM Write Cycle (Cont.) 5-19
5.12 LSI53C1030 456-Pin BGA Top View 5-22
5.12 LSI53C1030 456-Pin BGA Top View (Cont.) 5-23
5.13 456-Pin EPBGA (KY) Mechanical Drawing 5-28

xii Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

xiii
Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Tables 2.1 PCI/PCI-X Bus Commands and Encodings 2-9
2.2 Power States 2-16
2.3 Flash ROM Size Programming 2-24
2.4 Flash Signature Value 2-26
2.5 PCI Configuration Record in Serial EEPROM 2-28
2.6 20-Pin Multi-ICE Header Pinout 2-30
3.1 PCI System Signals 3-4
3.2 PCI Address and Data Signals 3-5
3.3 PCI Interface Control Signals 3-6
3.4 PCI Arbitration Signals 3-7
3.5 PCI Error Reporting Signals 3-7
3.6 PCI Interrupt Signals 3-8
3.7 PCI-related Signals 3-9
3.8 SCSI Bus Clock Signal 3-10
3.9 SCSI Channel [0] Interface Signals 3-10
3.10 SCSI Channel [0] Control Signals 3-12
3.11 SCSI Channel [1] Interface Signals 3-13
3.12 SCSI Channel [1] Control Signals 3-14
3.13 Flash ROM/NVSRAM Interface Pins 3-14
3.14 Serial EEPROM Interface Pins 3-16
3.15 ZCR Configuration Pins 3-16
3.16 JTAG, ICE, and Debug Pins 3-17
3.17 LSI Logic Test Pins 3-18
3.18 GPIO and LED signals 3-19
3.19 Power and Ground Pins 3-20
3.20 MAD Power-On Sense Pin Options 3-21
3.21 PCI-X Function to SCSI Channel Configurations 3-24
3.22 Flash ROM Size Programming 3-24
3.23 Pull-up and Pull-down Conditions 3-25
4.1 LSI53C1030 PCI Configuration Space Address Map 4-2
4.2 Subsystem ID Register Download Conditions and Values 4-14
4.3 Multiple Message Enable Field Bit Encoding 4-22
4.4 Maximum Outstanding Split Transactions 4-25
4.5 Maximum Memory Read Count 4-26
4.6 PCI I/O Space Address Map 4-30
4.7 PCI Memory [0] Address Map 4-30

xiv Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
4.8 PCI Memory [1] Address Map 4-30
4.9 Interrupt Signal Routing 4-37
5.1 Absolute Maximum Stress Ratings 5-2
5.2 Operating Conditions 5-2
5.3 LVD Driver SCSI Signals— SACK±, SATN±, SBSY±, SCD±,
SD[15:0]±, SDP[1:0]±, SIO±, SMSG±, SREQ±, SRST±, SSEL±
5-3
5.4 LVD Receiver SCSI Signals— SACK±, SATN±, SBSY±, SCD±,
SD[15:0]±, SDP[1:0]±, SIO±, SMSG±, SREQ±, SRST±, SSEL±
5-3
5.5 A_DIFFSENS and B_DIFFSENS SCSI Signals 5-4
5.6 Input Capacitance 5-4
5.7 8 mA Bidirectional Signals — GPIO[7:0], MAD[15:0], MADP[1:0],
SerialDATA 5-5
5.8 8 mA PCI Bidirectional Signals — ACK64/, AD[63:0], C_BE[7:0]/,
DEVSEL/, FRAME/, IRDY/, PAR, PAR64, PERR/, REQ64/,
SERR/, STOP/, TRDY/ 5-5
5.9 Input Signals — CLK, CLKMODE_0, CLKMODE_1,
DIS_PCI_FSN/, DIS_SCSI_FSN/, GNT/, IDDTN, IDSEL,
IOPD_GNT/, PVT1, PVT2, SCANEN, SCANMODE, SCLK,
TCK_CHIP, TCK_ICE, TESTACLK, TESTCLKEN, TESTHCLK,
TDI_CHIP, TDI_ICE, TMS_CHIP, TMS_ICE, TN, TRST_ICE/,
TST_RST/, ZCR_EN/ 5-6
5.10 8 mA Output Signals — ADSC/, ADV/, ALT_INTA/, ALT_INTB/,
BWE[1:0]/, FLSHALE[1:0]/, FLSHCE/, INTA/, INTB/, MCLK,
MOE/, PIPESTAT[2:0], RAMCE/, REQ/, RTCK_ICE, SerialCLK,
SERR/, TDO_CHIP, TDO_ICE, TRACECLK, TRACEPKT[7:0],
TRACESYNC 5-6
5.11 12 mA Output Signals — A_LED/, B_LED/, HB_LED/ 5-6
5.12 TolerANT Technology Electrical Characteristics for SE SCSI
Signals 5-7
5.13 External Clock 5-9
5.14 Reset Input 5-10
5.15 Interrupt Output 5-10
5.16 NVSRAM Read Cycle Timing 5-12
5.17 NVSRAM Write Cycle 5-14
5.18 Flash ROM Read Cycle Timing 5-16
5.19 Flash ROM Write Cycle 5-18
A.1 LSI53C1030 PCI Registers A-1

xv
Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
A.2 LSI53C1030 PCI I/O Space Registers A-3
A.3 LSI53C1030 PCI I/O Space Registers A-4

xvi Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller 1-1
Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Chapter 1
Introduction
This chapter provides a general overview of the LSI53C1030 PCI-X to
Dual Channel Ultra320 SCSI Multifunction Controller. This chapter
contains the following sections:
•Section 1.1, “General Description”
•Section 1.2, “Benefits of the Fusion-MPT Architecture”
•Section 1.3, “Benefits of PCI-X”
•Section 1.4, “Benefits of Ultra320 SCSI”
•Section 1.5, “Benefits of SureLINK (Ultra320 SCSI Domain
Validation)”
•Section 1.6, “Benefits of LVDlink Technology”
•Section 1.7, “Benefits of TolerANT® Technology”
•Section 1.8, “Summary of LSI53C1030 Features”
1.1 General Description
The LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction
Controller brings Ultra320 SCSI performance to host adapter,
workstation, and server designs, making it easy to add a
high-performance SCSI bus to any PCI or PCI-X system. The
LSI53C1030 supports both the PCI Local Bus Specification, Revision
2.2, and the PCI-X Addendum to the PCI Local Bus Specification,
Revision 1.0a.1
1. In some instances, this manual references PCI-X explicitly. References to the PCI
bus may be inclusive of both the PCI specification and PCI-X addendum, or they
may refer only to the PCI bus depending on the operating mode of the device.

1-2 Introduction
Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
The LSI53C1030 is pin compatible with the LSI53C1010R PCI to Dual
Channel Ultra160 SCSI Multifunction Controller to provide an easy and
safe migration path to Ultra320 SCSI. The LSI53C1030 supports up to a
64-bit, 133 MHz PCI-X bus. The Ultra320 SCSI features for the
LSI53C1030 include: double transition (DT) clocking, packetized
protocol, paced transfers, quick arbitrate and select (QAS), skew
compensation, intersymbol interference (ISI) compensation, cyclic
redundancy check (CRC), and domain validation technology. These
features comply with the American National Standard Institute (ANSI)
T10 SCSI Parallel Interface-4 (SPI-4) draft specification.
DT clocking enables the LSI53C1030 to achieve data transfer rates of
up to 320 megabytes per second (Mbytes/s) on each SCSI channel, for
a total bandwidth of 640 Mbytes/s on both SCSI channels. Packetized
protocol increases data transfer capabilities with SCSI information units.
QAS minimizes SCSI bus latency by allowing the bus to directly enter
the arbitration/selection bus phase after a SCSI disconnect and skip the
bus free phase. Skew compensation permits the LSI53C1030 to adjust
for cable and bus skew on a per-device basis. Paced transfers enable
high speed data transfers during DT data phases by using the REQ/ACK
transition as a free running data clock. Precompensation enables the
LSI53C1030 to adjust the signal drive strength to compensate for the
charge present on the cable. CRC improves the SCSI data transmission
integrity through enhanced detection of communication errors.
SureLINK™ Domain Validation detects the SCSI bus configuration and
adjusts the SCSI transfer rate to optimize bus interoperability and SCSI
data transfer rates. SureLINK Domain Validation provides three levels of
domain validation, assuring robust system operation.
The LSI53C1030 supports a local memory bus, which supports a
standard serial EEPROM and allows local storage of the BIOS in Flash
ROM memory. The LSI53C1030 supports programming of local Flash
ROM memory for BIOS updates. Figure 1.1 shows a typical LSI53C1030
board application connected to external ROM memory.

General Description 1-3
Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Figure 1.1 Typical LSI53C1030 Board Application
The LSI53C1030 integrates two high-performance SCSI Ultra320 cores
and a 64-bit, 133 MHz PCI-X bus master DMA core. The LSI53C1030
employs three ARM966E-S processors to meet the data transfer
flexibility requirements of the Ultra320 SCSI, PCI, and PCI-X
specifications. Separate ARM®processors support each SCSI channel
and the PCI/PCI-X interface.
These processors implement the LSI Logic Fusion-MPT™ architecture,
a multithreaded I/O algorithm that supports data transfers between the
host system and SCSI devices with minimal host processor intervention.
Fusion-MPT technology provides an efficient architecture that solves the
protocol overhead problems of previous intelligent and nonintelligent
adapter designs.
LVDlink™ technology is the LSI Logic implementation of Low Voltage
Differential (LVD) SCSI. LVDlink transceivers allow the LSI53C1030 to
perform either Single-Ended (SE) or LVD transfers. Figure 1.2 illustrates
a typical LSI53C1030 system application.
Flash ROM/
Memory Control
Block
LSI53C1030
64 Bit, 133 MHz
Multifunction PCI-X
Dual Channel
Channel [0]
68 Pin
Wide SCSI
Connector
SCSI Bus
SCSI Bus
PCI-X Interface
Memory
Address/Data
Bus
Serial Data
Ultra320 SCSI
Controller
and
Terminator
Channel [1]
68 Pin
Wide SCSI
Connector
and
Terminator
Function [1]Function [0]
Serial EEPROM
Serial Clock
NVSRAM

1-4 Introduction
Version 2.1 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Figure 1.2 Typical LSI53C1030 System Application
The LSI53C1030 supports the LSI Logic Integrated Mirroring™(IM)
technology, which provides physical mirroring of the boot volume through
LSI53C1030 firmware. This feature provides extra reliability for the
system’s boot volume without burdening the host CPU. Keeping a
second disk as a mirror requires the LSI Logic Fusion-MPT firmware,
which performs writes to both the boot drive and the mirrored drive. The
runtime mirroring of the boot drive is transparent to the BIOS, drivers,
and operating system.
The IM firmware requires a configuration mechanism, which enables
configuration of the mirroring attributes during initial setup or
reconfiguration after hardware failures or changes in the system
environment. Use the LSI Logic BIOS Configuration Utility or the IM DOS
Configuration Utility to configure the IM firmware attributes. Using the LSI
Logic BIOS and drivers adds support of physical device recognition for
Fixed Disk, Optical Disk,
Printer, Tape, and Other
SCSI Peripherals
Fixed Disk, Optical Disk,
Printer, Tape, and Other
SCSI Peripherals
One PCI Bus Load
PCI Graphic Accelerator
PCI Fast Ethernet
Memory
Controller
Memory
PCI-X Bus
Interface
Controller
Central
Processing
Unit
(CPU)
Processor Bus
LSI53C1030 PCI-X
to Ultra320 SCSI
Channel [0]
and
LSI53C1030 PCI-X
to Ultra320 SCSI
Channel [1]
SCSI Bus
SCSI Bus
PCI-X Bus