LSI LSI53C1000 User manual

®
S14050.A
LSI53C1000
PCI to Ultra160
SCSI Controller
TECHNICAL
MANUAL
February 2001
Version 2.1

ii
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.
Document DB14-000128-03, Third Edition (February 2001). This document
describes the LSI Logic LSI53C1000 PCI to Ultra160 SCSI Controller and will
remain the official reference source for all revisions/releases of this product until
rescinded by an update.
To receive product literature, visit us at http://www.lsilogic.com.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.
Ultra SCSI is the term used by the SCSI Trade Association (STA) to describe
Fast-20 SCSI, as documented in the SCSI-3 Fast-20 Parallel Interface standard,
X3.277-199X.
Ultra2 SCSI is the term used by the SCSI Trade Association (STA) to describe
Fast-40 SCSI, as documented in the SCSI Parallel Interface–2 standard, (SPI–2)
X3T10/1142D.
Copyright © 2000–2001 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design, TolerANT, SCRIPTS, SDMS, SureLINK, and LVDlink
are registered trademarks or trademarks of LSI Logic Corporation. All other brand
and product names may be trademarks of their respective companies.
AP

Preface iii
Preface
This book is the primary reference and technical manual for the LSI Logic
LSI53C1000 PCI to Ultra160 SCSI Controller. This manual contains a
complete functional description for the product and includes physical and
electrical specifications.
Audience
This document was prepared for system designers and programmers
who are using this device to design an Ultra160 SCSI port for PCI-based
personal computers, workstations, servers or embedded applications.
Organization
This document has the following chapters and appendixes:
•Chapter 1, Introduction, describes the general information about the
LSI53C1000.
•Chapter 2, Functional Description, describes the main functional
areas of the chip in greater detail, including the interfaces to the
SCSI bus and external memory.
•Chapter 3, Signal Descriptions, contains the pin diagram and signal
descriptions.
•Chapter 4, Registers, describes each bit in the operating registers,
and is organized by register address.
•Chapter 5, SCSI SCRIPTS Instruction Set, defines all of the SCSI
SCRIPTS instructions that are supported by the LSI53C1000.
•Chapter 6, Specifications, contains the electrical characteristics and
AC timing diagrams.
•Appendix A, Register Summary, is a register summary.

iv Preface
•Appendix B, External Memory Interface Diagram Examples,
contains several example interface drawings for connecting the
LSI53C1000 to external ROMs.
Related Publications
For background please contact:
ANSI
11 West 42nd Street
New York, NY 10036
[phone]
Ask for document number X3.131-199X (SCSI-2)
Global Engineering Documents
15 Inverness Way East
Englewood, CO 80112
[phone] or [phone] (outside U.S.) FAX [phone]
Ask for document number X3.131-1994 (SCSI-2) or X3.253
(SCSI-3 Parallel Interface)
ENDL Publications
14426 Black Walnut Court
Saratoga, CA 95070
[phone]
Document names: SCSI Bench Reference, SCSI Encyclopedia, SCSI
Tutor
Prentice Hall
113 Sylvan Avenue
Englewood Cliffs, NJ 07632
[phone]
Ask for document number ISBN 0-13-796855-8, SCSI: Understanding
the Small Computer System Interface
LSI Logic World Wide Web Home Page
www.lsil.com
SCSI SCRIPTS™ Processors Programming Guide, Order Number
S14044.A

Preface v
PCI Special Interest Group
2575 N. E. Katherine
Hillsboro, OR 97214
[phone]; [phone] (International); FAX [phone]
Conventions Used in This Manual
The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive.
Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.
Revision Record
Revision Date Remarks
0.1 1/00 Advanced Version
1.0 5/00 Preliminary Version
2.0 11/00 Final Version.
Changed branding from SYM53C1000 to LSI53C1000.
2.1 2/01 Changed Ultra3 references to Ultra160.

vi Preface

Contents vii
Contents
Chapter 1 Introduction
1.1 General Description 1-1
1.1.1 New Features in the LSI53C1000 1-3
1.2 Benefits of Ultra160 SCSI 1-4
1.3 Benefits of SureLINK (Ultra160 SCSI Domain Validation) 1-5
1.4 Benefits of LVDlink 1-6
1.5 Benefits of TolerANT®Technology 1-6
1.6 Summary of LSI53C1000 Benefits 1-7
1.6.1 SCSI Performance 1-7
1.6.2 PCI Performance 1-9
1.6.3 Integration 1-9
1.6.4 Ease of Use 1-10
1.6.5 Flexibility 1-10
1.6.6 Reliability 1-11
1.6.7 Testability 1-11
Chapter 2 Functional Description
2.1 PCI Functional Description 2-3
2.1.1 PCI Addressing 2-3
2.1.2 PCI Bus Commands and Functions Supported 2-4
2.1.3 PCI Cache Mode 2-10
2.2 SCSI Functional Description 2-18
2.2.1 SCRIPTS Processor 2-19
2.2.2 Internal SCRIPTS RAM 2-19
2.2.3 64-Bit Addressing in SCRIPTS 2-20
2.2.4 Hardware Control of SCSI Activity LED 2-21
2.2.5 Designing an Ultra160 SCSI System 2-22
2.2.6 Prefetching SCRIPTS Instructions 2-31
2.2.7 Opcode Fetch Burst Capability 2-32

viii Contents
2.2.8 Load and Store Instructions 2-32
2.2.9 JTAG Boundary Scan Testing 2-33
2.2.10 Parity/CRC/AIP Options 2-33
2.2.11 DMA FIFO 2-36
2.2.12 SCSI Data Paths 2-37
2.2.13 SCSI Bus Interface 2-39
2.2.14 Select/Reselect During Selection/Reselection 2-40
2.2.15 Synchronous Operation 2-41
2.2.16 Interrupt Handling 2-45
2.2.17 Interrupt Routing 2-53
2.2.18 Chained Block Moves 2-55
2.3 Parallel ROM Interface 2-59
2.4 Serial EEPROM Interface 2-61
2.4.1 Default Download Mode 2-61
2.4.2 No Download Mode 2-62
2.5 Power Management 2-62
2.5.1 Power State D0 2-63
2.5.2 Power State D1 2-63
2.5.3 Power State D2 2-64
2.5.4 Power State D3 2-64
Chapter 3 Signal Descriptions
3.1 Signal Organization 3-1
3.2 Internal Pull-ups and Pull-downs on LSI53C1000 Signals 3-4
3.3 PCI Bus Interface Signals 3-4
3.3.1 System Signals 3-5
3.3.2 Address and Data Signals 3-6
3.3.3 Interface Control Signals 3-7
3.3.4 Arbitration Signals 3-8
3.3.5 Error Reporting Signals 3-8
3.3.6 Interrupt Signals 3-9
3.4 SCSI Bus Interface Signals 3-9
3.5 General Purpose I/O (GPIO) Signals 3-13
3.6 Flash ROM and Memory Interface Signals 3-14
3.7 Test Interface Signals 3-15
3.8 Power and Ground Signals 3-16
3.9 MAD Bus Programming 3-17

Contents ix
Chapter 4 Registers
4.1 PCI Configuration Registers 4-1
4.2 SCSI Registers 4-21
4.3 SCSI Shadow Registers 4-119
Chapter 5 SCSI SCRIPTS Instruction Set
5.1 SCSI SCRIPTS 5-1
5.1.1 Sample Operation 5-3
5.2 Block Move Instructions 5-4
5.2.1 First Dword 5-5
5.2.2 Second Dword 5-13
5.2.3 Third Dword 5-14
5.3 I/O Instructions 5-14
5.3.1 First Dword 5-14
5.3.2 Second Dword 5-22
5.4 Read/Write Instructions 5-23
5.4.1 First Dword 5-23
5.4.2 Second Dword 5-24
5.4.3 Read-Modify-Write Cycles 5-24
5.4.4 Move To/From SFBR Cycles 5-25
5.5 Transfer Control Instructions 5-27
5.5.1 First Dword 5-27
5.5.2 Second Dword 5-33
5.5.3 Third Dword 5-33
5.6 Memory Move Instructions 5-34
5.6.1 Read/Write System Memory from a SCRIPT 5-35
5.6.2 Second Dword 5-36
5.6.3 Third Dword 5-36
5.7 Load and Store Instructions 5-37
5.7.1 First Dword 5-38
5.7.2 Second Dword 5-39
Chapter 6 Specifications
6.1 DC Characteristics 6-1
6.2 TolerANT Technology Electrical Characteristics 6-7
6.3 AC Characteristics 6-11

x Contents
6.4 PCI and External Memory Interface Timing Diagrams 6-13
6.4.1 Target Timing 6-14
6.4.2 Initiator Timing 6-24
6.4.3 External Memory Timing 6-41
6.5 SCSI Timing Diagrams 6-62
6.6 Package Drawings 6-71
Appendix A Register Summary
Appendix B External Memory Interface Diagram Examples
Index
Customer Feedback
Figures 1.1 Typical LSI53C1000 Board Application 1-2
1.2 Typical LSI53C1000 System Application 1-3
2.1 LSI53C1000 Block Diagram 2-2
2.2 DMA FIFO Sections 2-36
2.3 LSI53C1000 Host Interface SCSI Data Paths 2-37
2.4 Regulated Termination for Ultra160 SCSI 2-40
2.5 Determining the Synchronous Transfer Rate 2-45
2.6 Interrupt Routing Hardware Using the LSI53C1000 2-54
2.7 Chained Block Move Instruction 2-55
3.1 LSI53C1000 Signal Grouping 3-3
4.1 Single Transition Transfer Waveforms 4-102
4.2 DT Transfer Waveforms (XCLKS Examples) 4-103
4.3 DT Transfer Waveforms (XCLKH Examples) 4-104
5.1 SCRIPTS Overview 5-4
5.2 Block Move Instruction - First Dword 5-5
5.3 Block Move Instruction - Second Dword 5-13
5.4 Block Move Instruction - Third Dword 5-14
5.5 First 32-bit Word of the I/O Instruction 5-14
5.6 Second 32-Bit Word of the I/O Instruction 5-22
5.7 Read/Write Instruction - First Dword 5-23

Contents xi
5.8 Read/Write Instruction - Second Dword 5-24
5.9 Transfer Control Instructions - First Dword 5-27
5.10 Transfer Control Instructions - Second Dword 5-33
5.11 Transfer Control Instructions - Third Dword 5-33
5.12 Memory Move Instructions - First Dword 5-35
5.13 Memory Move Instructions - Second Dword 5-36
5.14 Memory Move Instructions - Third Dword 5-37
5.15 Load and Store Instruction - First Dword 5-38
5.16 Load and Store Instructions - Second Dword 5-40
6.1 LVD Driver 6-3
6.2 LVD Receiver 6-4
6.3 Rise and Fall Time Test Condition 6-8
6.4 SCSI Input Filtering 6-8
6.5 Hysteresis of SCSI Receivers 6-9
6.6 Input Current as a Function of Input Voltage 6-9
6.7 Output Current as a Function of Output Voltage 6-10
6.8 External Clock 6-11
6.9 Reset Input 6-12
6.10 Interrupt Output 6-13
6.11 PCI Configuration Register Read 6-15
6.12 PCI Configuration Register Write 6-16
6.13 Operating Registers/SCRIPTS RAM Read, 32 Bits 6-17
6.14 Operating Register/SCRIPTS RAM Read, 64 Bits 6-19
6.15 Operating Register/SCRIPTS RAM Write, 32 Bits 6-21
6.16 Operating Register/SCRIPTS RAM Write, 64 Bits 6-23
6.17 Nonburst Opcode Fetch, 32-Bit Address and Data 6-25
6.18 Burst Opcode Fetch, 32-Bit Address and Data 6-27
6.19 Back to Back Read, 32-Bit Address and Data 6-29
6.20 Back to Back Write, 32-Bit Address and Data 6-31
6.21 Burst Read, 32-Bit Address and Data 6-33
6.22 Burst Read, 64-Bit Address and Data 6-35
6.23 Burst Write, 32-Bit Address and Data 6-37
6.24 Burst Write, 64-Bit Address and Data 6-39
6.25 External Memory Read 6-42
6.26 External Memory Write 6-46
6.27 Normal/Fast Memory (≥128 Kbytes) Single Byte
Access Read Cycle 6-48

xii Contents
6.28 Normal/Fast Memory (≥128 Kbytes) Single Byte
Access Write Cycle 6-50
6.29 Normal/Fast Memory (≥128 Kbytes) Multiple Byte
Access Read Cycle 6-52
6.30 Normal/Fast Memory (≥128 Kbytes) Multiple Byte
Access Write Cycle 6-54
6.31 Slow Memory (≥128 Kbytes) Read Cycle 6-56
6.32 Slow Memory (≥128 Kbytes) Write Cycle 6-58
6.33 ≤64 Kbytes ROM Read Cycle 6-60
6.34 ≤64 Kbytes ROM Write Cycle 6-61
6.35 Initiator Asynchronous Send 6-62
6.36 Initiator Asynchronous Receive 6-63
6.37 Target Asynchronous Send 6-63
6.38 Target Asynchronous Receive 6-64
6.39 Initiator and Target ST Synchronous Transfer 6-66
6.40 Initiator and Target DT Synchronous Transfer 6-69
6.41 LSI53C1000 329 BGA Chip - Top View 6-72
6.42 LSI53C1000 329 Ball Grid Array (Bottom view) 6-76
6.43 LSI53C1000 329 BGA Mechanical Drawing 6-77
B.1 16 Kbyte Interface with 200 ns Memory B-1
B.2 64 Kbyte Interface with 150 ns Memory B-2
B.3 128, 256, 512 Kbyte or 1 Mbyte Interface with 150 ns
Memory B-3
B.4 512 Kbyte Interface with 150 ns Memory B-4
Tables 2.1 PCI Bus Commands and Encoding Types 2-4
2.2 PCI Cache Mode Alignment 2-11
2.3 New Phases on SCSI Bus 2-23
2.4 Bits Used for Parity/CRC/AIP Control and Generation 2-34
2.5 SCSI Parity Errors and Interrupts 2-35
2.6 SCF Divisor Values 2-42
2.7 Parallel ROM Support 2-60
2.8 Default Download Mode Serial EEPROM Data Format 2-61
2.9 Power States 2-63
3.1 LSI53C1000 Internal Pull-ups and Pull-downs 3-4
3.2 System Signals 3-5
3.3 Address and Data Signals 3-6

Contents xiii
3.4 Interface Control Signals 3-7
3.5 Arbitration Signals 3-8
3.6 Error Reporting Signals 3-8
3.7 Interrupt Signals 3-9
3.8 SCSI Bus Interface Signals 3-9
3.9 SCSI Signals 3-10
3.10 SCSI Control Signals 3-12
3.11 GPIO Signals 3-13
3.12 Flash ROM and Memory Interface Signals 3-14
3.13 Test Interface Signals 3-15
3.14 Power and Ground Signals 3-16
3.15 MAD[3:1] Pin Decoding 3-18
4.1 PCI Configuration Register Map 4-2
4.2 SCSI Register Map 4-22
4.3 Maximum Synchronous Offset 4-34
4.4 DT Transfer Rates 4-105
4.5 Single Transition Transfer Rates 4-106
5.1 Read/Write Instructions 5-25
6.1 Absolute Maximum Stress Ratings 6-2
6.2 Operating Conditions 6-2
6.3 LVD Driver SCSI Signals—SD[15:0], SDP[1:0], SREQ/,
SACK/, SMSG/, SIO/, SCD/, SATN/, SBSY/, SSEL/,
SRST/ 6-3
6.4 LVD Receiver SCSI Signals—SD[15:0], SDP[1:0],
SREQ/, SACK/, SMSG/, SIO/, SCD/, SATN/, SBSY/,
SSEL/, SRST/ 6-3
6.5 DIFFSENS SCSI Signals 6-4
6.6 Input Capacitance 6-4
6.7 8 mA Bidirectional Signals—GPIO0_FETCH/,
GPIO1_MASTER/, GPIO2, GPIO3, GPIO4 6-5
6.8 4 mA Bidirectional Signals—MAD[7:0] 6-5
6.9 4 mA Output Signals—MAS[1:0]/, MCE/,
MOE/_TESTOUT, MWE/, TDO 6-5
6.10 8 mA PCI Bidirectional Signals—AD[63:0], C_BE[7:0]/,
FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/,
PAR, PAR64, REQ64/, ACK64/ 6-6

xiv Contents
6.11 Input Signals—CLK, GNT/, IDSEL, INT_DIR, RST/,
SCLK, TCK, TDI, TEST_HSC, TEST_RST/,
TEST_PD, TMS 6-6
6.12 8 mA Output Signals—INTA/, INTB/, ALT_INTA/,
ALT_INTB/, REQ/, SERR/ 6-6
6.13 TolerANT Technology Electrical Characteristics for
SE SCSI Signals 6-7
6.14 External Clock 6-11
6.15 Reset Input 6-12
6.16 Interrupt Output 6-13
6.17 PCI Configuration Register Read 6-15
6.18 PCI Configuration Register Write 6-16
6.19 Operating Register/SCRIPTS RAM Read, 32 Bits 6-17
6.20 Operating Register/SCRIPTS RAM Read, 64 Bits 6-18
6.21 Operating Register/SCRIPTS RAM Read, 32 Bits 6-20
6.22 Operating Register/SCRIPTS RAM Write, 64 Bits 6-22
6.23 Nonburst Opcode Fetch, 32-Bit Address and Data 6-24
6.24 Burst Opcode Fetch, 32-Bit Address and Data 6-26
6.25 Back to Back Read, 32-Bit Address and Data 6-28
6.26 Back to Back Write, 32-Bit Address and Data 6-30
6.27 Burst Read, 32-Bit Address and Data 6-32
6.28 Burst Read, 64-Bit Address and Data 6-34
6.29 Burst Write, 32-Bit Address and Data 6-36
6.30 Burst Write, 64-Bit Address and Data 6-38
6.31 External Memory Read 6-41
6.32 External Memory Write 6-45
6.33 Normal/Fast Memory (≥128 Kbytes) Single Byte
Access Read Cycle 6-48
6.34 Normal/Fast Memory (≥128 Kbytes) Single Byte
Access Write Cycle 6-50
6.35 Slow Memory (≥128 Kbytes) Read Cycle 6-56
6.36 Slow Memory (≥128 Kbytes) Write Cycle 6-58
6.37 ≤64 Kbytes ROM Read Cycle 6-60
6.38 ≤64 Kbytes ROM Write Cycle 6-61
6.39 Initiator Asynchronous Send 6-62
6.40 Initiator Asynchronous Receive 6-63
6.41 Target Asynchronous Send 6-63
6.42 Target Asynchronous Receive 6-64

Contents xv
6.43 SCSI-1 Transfers (SE 5.0 Mbytes) 6-64
6.44 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or
20.0 Mbytes (16-Bit Transfers) 40 MHz Clock 6-65
6.45 Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers)
or 40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz
Clock 6-65
6.46 Ultra2 SCSI Transfers 40.0 Mbyte (8-Bit Transfers) or
80.0 Mbyte (16-Bit Transfers) Quadrupled 40 MHz
Clock 6-66
6.47 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers)
or 20.0 Mbytes (16-Bit Transfers) 40 MHz Clock 6-67
6.48 Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers)
or 40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz
Clock 6-67
6.49 Ultra2 SCSI Transfers 40.0 Mbyte (8-Bit Transfers) or
80.0 Mbyte (16-Bit Transfers) Quadrupled 40 MHz
Clock 6-68
6.50 Ultra160 SCSI Transfers 160.0 Mbyte
(16-Bit Transfers) Quadrupled 40 MHz Clock 6-69
6.51 Alphanumeric list by Signal Names 6-74
6.52 Alphanumeric List by BGA Positions 6-75
A.1 LSI53C1000 PCI Register Map A-1
A.2 LSI53C1000 SCSI Register Map A-3

xvi Contents

LSI53C1000 PCI to Ultra160 SCSI Controller 1-1
Chapter 1
Introduction
This chapter provides a general overview on the LSI53C1000 PCI to
Ultra160 SCSI Controller. This chapter contains the following sections:
•Section 1.1, “General Description”
•Section 1.2, “Benefits of Ultra160 SCSI”
•Section 1.3, “Benefits of SureLINK (Ultra160 SCSI Domain
Validation)”
•Section 1.4, “Benefits of LVDlink”
•Section 1.5, “Benefits of TolerANT®Technology”
•Section 1.6, “Summary of LSI53C1000 Benefits”
1.1 General Description
The LSI53C1000 brings Ultra160 SCSI performance to host adapter,
workstation, and server designs, making it easy to add a
high-performance SCSI bus to any PCI system.
The LSI53C1000 supports a 64-bit or 32-bit, 66 or 33 MHz PCI bus. The
Ultra160 SCSI features implemented in the LSI53C1000 are: Double
Transition (DT) clocking, Cyclic Redundancy Check (CRC), and Domain
Validation. These features comply with the Ultra160 SCSI industry
initiative.
DT clocking permits the LSI53C1000 to transfer data up to
160 megabytes per second (Mbytes/s). CRC improves the integrity of the
SCSI data transmission through enhanced detection of communication
errors. Asynchronous Information Protection (AIP) augments CRC to
protect all nondata phases, providing complete end-to-end protection of
the SCSI I/O. SureLINK™ Domain Validation detects the SCSI bus

1-2 Introduction
configuration and automatically tests and adjusts the SCSI transfer rate
to optimize interoperability. Three levels of Domain Validation are
provided, assuring robust system operation.
The LSI53C1000 has a local memory bus. This allows local storage of
the device’s BIOS ROM in flash memory or standard EPROMs. The
LSI53C1000 supports programming of local flash memory for BIOS
updates. The chip is packaged in a 329 Ball Grid Array (BGA). Figure 1.1
shows a typical LSI53C1000 board application connected to external
ROM or flash memory.
Figure 1.1 Typical LSI53C1000 Board Application
LVDlink™ technology is the LSI Logic implementation of Low Voltage
Differential (LVD). LVDlink transceivers allow the LSI53C1000 to perform
either Single-Ended (SE) or LVD transfers. The LSI53C1000 integrates a
high-performance SCSI core, a 64-bit/66 MHz PCI bus master DMA core,
and the LSI Logic SCSI SCRIPTS™ processor to meet the flexibility
requirements of Ultra160 SCSI standards. It implements multithreaded
I/O algorithms with minimum processor intervention, solving the protocol
overhead problems of previous intelligent and nonintelligent adapter
designs. Figure 1.2 illustrates a typical LSI53C1000 system application.
Flash ROM
Serial EEPROM
Memory Control
Block
LSI53C1000
64-Bit / 66MHz
PCI to
Single Channel
68-Pin
SCSI
Connector
SCSI Data,
Parity, and
Control Signals
PCI Interface
PCI Address, Data, Parity and Control Signals
Memory
Address/Data
Bus
GPIO/[1:0]
Ultra160 SCSI
Controller
and
Terminator

General Description 1-3
Figure 1.2 Typical LSI53C1000 System Application
1.1.1 New Features in the LSI53C1000
The LSI53C1000 is functionally similar to the LSI53C1010 PCI to Dual
Channel Ultra160 SCSI Multifunction Controller, except that it
implements a single SCSI function. Following is a list of LSI53C1000
features:
•Supports 66 MHz PCI
•Complies with PCI 2.2 specification
•Supports Ultra160 DT clocking for data transfers up to 160 Mbytes/s
Fixed Disk, Optical Disk,
Printer, Tape, and Other
SCSI Peripherals
One PCI Bus Load
PCI Graphic Accelerator
PCI Fast Ethernet
Memory
Controller
Memory
PCI Bus
Interface
Controller
Central
Processing
Unit
(CPU) Typical PCI Computer
System Architecture
Processor Bus
LSI53C1000 PCI
to Ultra160 SCSI
Controller
SCSI Bus
PCI Bus

1-4 Introduction
•Supports enhanced protection on nondata asynchronous phases
through AIP
•Supports CRC checking and generation in DT phases
•Supports Domain Validation
– Basic (level 1) with Inquiry Command (Inquiry Check)
– Enhanced (level 2) with Read/Write Buffer
– Margined (level 3) with margining of LVD drivers and
programmable skew test
•All cycles to SCRIPTS RAM stay internal to the device, not
generating PCI cycles
•SCRIPTS engine with improved instruction fetch performance
1.2 Benefits of Ultra160 SCSI
Ultra160 SCSI delivers data up to two times faster than Ultra2 SCSI.
Ultra160 SCSI is an extension of the SPI-3 draft standard that allows
faster synchronous SCSI data transfer rates than Ultra2 SCSI. When
enabled, Ultra160 SCSI performs 80 megatransfers per second
(megatransfers/s) resulting in approximately double the synchronous
data transfer rates of Ultra2 SCSI. The LSI53C1000 performs 16-bit,
Ultra160 SCSI synchronous data transfers as fast as 160 Mbytes/s. This
advantage is most noticeable in heavily loaded systems, or large block
size applications such as video on-demand and image processing.
The Ultra160 data transfer speed is accomplished using DT clocking.
DT clocking refers to transferring data on both polarity edges of the
request or acknowledge signals. Data is clocked on both rising and falling
edges of the request and acknowledge signals. Double-edge clocking
doubles data transfer speeds without increasing the clock rate.
Ultra160 SCSI also includes CRC, which offers higher levels of data
reliability by ensuring complete integrity of transferred data. CRC is a
32-bit scheme, referred to as CRC-32. CRC is guaranteed to detect all
single bit errors, any two bits in error, or any combination of errors within
a single 32-bit range.