LSI LSI53C876 User manual

®
S14066
LSI53C876/876E
PCI to Dual Channel
SCSI Multifunction
Controller
TECHNICAL
MANUAL
March 2001
Version 2.1

ii
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.
Document DB14-000167-00, First Edition (March 2001)
This document describes the LSI Logic LSI53C876/876E PCI to Dual Channel
SCSI Multifunction Controller and will remain the official reference source for all
revisions/releases of this product until rescinded by an update.
To receive product literature, visit us at http://www.lsilogic.com.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.
Copyright © 1996–2001 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design, TolerANT, SDMS, SYMplicity, and SCRIPTS are
registered trademarks or trademarks of LSI Logic Corporation. All other brand
and product names may be trademarks of their respective companies.

Preface iii
Preface
This book is the primary reference and technical manual for the LSI Logic
LSI53C876/876E PCI to Dual Channel SCSI Multifunction Controller. It
contains a complete functional description for the product and includes
complete physical and electrical specifications.
This technical manual assumes the user is familiar with the current and
proposed standards for SCSI and PCI. For additional background
information on these topics, please refer to the list of reference materials
provided in the Related Publications list.
Audience
This manual assumes some prior knowledge of current and proposed
SCSI and PCI standards.
Organization
This document has the following chapters and appendixes:
•Chapter 1, General Description, includes general information about
the LSI53C876/876E.
•Chapter 2, Functional Description, describes the main functional
areas of the chip in more detail, including the interfaces to the SCSI
bus and external memory.
•Chapter 3, Signal Descriptions, contains pin diagrams and signal
descriptions.
•Chapter 4, Registers, describes each bit in the operating registers,
and is organized by register address.
•Chapter 5, SCSI SCRIPTS Instruction Set, defines the SCSI
SCRIPTS instructions supported by the LSI53C876/876E.

iv Preface
•Chapter 6, Electrical Characteristics, contains the electrical
characteristics and AC timing diagrams.
•Appendix A, Register Summary, is a register summary.
•Appendix B, External Memory Interface Diagram Examples,
contains serveral example interface drawings for connecting the
LSI53C876 to external ROMs.
Related Publications
For background please contact:
ANSI
11 West 42nd Street
New York, NY 10036
[phone]
Ask for document number X3.131-199X (SCSI-2)
Global Engineering Documents
15 Inverness Way East
Englewood, CO 80112
[phone] or [phone] (outside U.S.) FAX [phone]
Ask for document number X3.131-1994 (SCSI-2) or X3.253
(SCSI-3 Parallel Interface)
ENDL Publications
14426 Black Walnut Court
Saratoga, CA 95070
[phone]
Document names: SCSI Bench Reference, SCSI Encyclopedia,
SCSI Tutor
Prentice Hall
113 Sylvan Avenue
Englewood Cliffs, NJ 07632
[phone]
Ask for document number ISBN 0-13-796855-8, SCSI: Understanding
the Small Computer System Interface
LSI Logic World Wide Web Home Page
www.lsil.com

Preface v
PCI Special Interest Group
2575 N. E. Katherine
Hillsboro, OR 97214
[phone]; [phone] (International); FAX [phone]
SCSI SCRIPTS™ Processors Programming Guide, Order Number
S14044.A
Conventions Used in This Manual
The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive.
Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.
Revision Record
Revision Date Remarks
1.0 9/96 Prelimiary technical manual.
2.0 11/97 Revised technical manual.
2.1 3/01 All product names changed from SYM to LSI.

vi Preface

Contents vii
Contents
Chapter 1 General Description
1.1 Wide Ultra SCSI Benefits 1-4
1.2 TolerANT®Technology 1-4
1.3 LSI53C876 Benefits 1-5
1.3.1 PCI Performance 1-5
1.3.2 SCSI Performance 1-5
1.3.3 Testability 1-6
1.3.4 Integration 1-7
1.3.5 Reliability 1-7
Chapter 2 Functional Description
2.1 PCI Functional Description 2-3
2.1.1 PCI Addressing 2-3
2.1.2 PCI Bus Commands and Functions Supported 2-4
2.1.3 Internal Arbiter 2-10
2.1.4 PCI Cache Mode 2-11
2.2 SCSI Functional Description 2-13
2.2.1 Two SCSI Controllers 2-13
2.2.2 SCRIPTS Processor 2-13
2.2.3 JTAG Boundary Scan Testing 2-16
2.2.4 SCSI Loopback Mode 2-17
2.2.5 Parity Options 2-17
2.2.6 DMA FIFO 2-20
2.2.7 SCSI Bus Interface 2-24
2.2.8 Synchronous Operation 2-30
2.2.9 Designing a Wide Ultra SCSI System 2-32
2.2.10 Interrupt Handling 2-33
2.2.11 Chained Block Moves 2-40
2.3 Parallel ROM Interface 2-43

viii Contents
2.4 Serial EEPROM Interface 2-45
2.4.1 Mode A Operation 2-45
2.4.2 Mode B Operation 2-46
2.4.3 Mode C Operation 2-46
2.4.4 Mode D Operation 2-48
2.5 Power Management 2-48
2.5.1 Power State D0 2-49
2.5.2 Power State D1 2-49
2.5.3 Power State D2 2-49
2.5.4 Power State D3 2-50
Chapter 3 Signal Descriptions
3.1 PCI Interface Signals 3-6
3.1.1 System Signals 3-6
3.1.2 Address and Data Signals 3-7
3.1.3 Interface Control Signals 3-8
3.1.4 Arbitration Signals 3-9
3.1.5 Error Reporting Signals 3-9
3.1.6 PCI Interrupt Signals 3-10
3.1.7 GPIO Interface Signals 3-11
3.2 SCSI Bus Interface Signals 3-13
3.2.1 SCSI Bus Interface Signal 3-13
3.2.2 SCSI Bus Interface 3-14
3.3 ROM/Flash Interface Signals 3-18
3.4 Test Interface Signals 3-19
3.5 Power and Ground Signals 3-20
3.5.1 Isolated Power Supplies 3-21
3.6 MAD Bus Programming 3-21
Chapter 4 Registers
4.1 PCI Configuration Registers 4-1
4.2 SCSI Registers 4-20
Chapter 5 SCSI SCRIPTS Instruction Set
5.1 Low Level Register Interface Mode 5-1
5.2 High Level SCSI SCRIPTS Mode 5-2
5.2.1 Sample Operation 5-3

Contents ix
5.3 Block Move Instruction 5-6
5.3.1 First Dword 5-6
5.3.2 Second Dword 5-13
5.4 I/O Instruction 5-13
5.4.1 First Dword 5-13
5.4.2 Second Dword 5-22
5.5 Read/Write Instructions 5-22
5.5.1 First Dword 5-22
5.5.2 Second Dword 5-24
5.5.3 Read-Modify-Write Cycles 5-24
5.5.4 Move To/From SFBR Cycles 5-25
5.6 Transfer Control Instructions 5-27
5.6.1 First Dword 5-27
5.6.2 Second Dword 5-34
5.7 Memory Move Instructions 5-34
5.7.1 Read/Write System Memory from SCRIPTS 5-36
5.7.2 Second Dword 5-36
5.7.3 Third Dword 5-36
5.8 Load and Store Instructions 5-38
5.8.1 First Dword 5-39
5.8.2 Second Dword 5-40
Chapter 6 Electrical Characteristics
6.1 DC Characteristics 6-1
6.2 3.3 V PCI DC Characteristics 6-7
6.3 TolerANT Technology Electrical Characteristics 6-8
6.4 AC Characteristics 6-12
6.4.1 PCI and External Memory Interface Timings 6-15
6.4.2 PCI and External Memory Interface Timing 6-54
6.4.3 SCSI Interface Timing 6-55
6.5 Package Diagrams 6-60
Appendix A Register Summary
Appendix B External Memory Interface Diagram Examples

x Contents
Index
Customer Feedback
Figures 1.1 Typical LSI53C876 System Application 1-2
1.2 Typical LSI53C876 Board Application 1-3
2.1 LSI53C876 Block Diagram 2-2
2.2 Parity Checking/Generation 2-20
2.3 DMA FIFO Sections 2-20
2.4 LSI53C876 Host Interface SCSI Data Paths 2-24
2.5 LSI53C876 Differential Wiring Diagram 2-27
2.6 Regulated Termination 2-29
2.7 Determining the Synchronous Transfer Rate 2-32
2.8 Block Move and Chained Block Move Instructions 2-40
3.1 LSI53C876 208-Pin PQFP Diagram 3-2
3.2 LSI53C876 256-Ball BGA Diagram (Top View) 3-3
3.3 LSI53C876 Functional Signal Grouping 3-4
5.1 SCRIPTS Overview 5-5
5.2 Block Move Instruction Register 5-8
5.3 I/O Instruction Register 5-16
5.4 Read/Write Instruction Register 5-23
5.5 Transfer Control Instruction 5-29
5.6 Memory Move Instruction 5-37
5.7 Load and Store Instruction Format 5-41
6.1 Rise and Fall Time Test Conditions 6-10
6.2 SCSI Input Filtering 6-10
6.3 Hysteresis of SCSI Receivers 6-10
6.4 Input Current as a Function of Input Voltage 6-11
6.5 Output Current as a Function of Output Voltage 6-11
6.6 Clock Timing 6-12
6.7 Reset Input 6-13
6.8 Interrupt Output 6-14
6.9 Configuration Register Read 6-17
6.10 Configuration Register Write 6-18
6.11 Target Read (Not From External Memory) 6-19

Contents xi
6.12 Target Write (Not From External Memory) 6-20
6.13 Target Read, from External Memory 6-22
6.14 Target Write, from External Memory 6-26
6.15 Opcode Fetch, Nonburst 6-29
6.16 Opcode Fetch, Burst 6-31
6.17 Back-to-Back Read 6-33
6.18 Back-to-Back Write 6-35
6.19 Burst Read 6-38
6.20 Burst Write 6-42
6.21 Read Cycle, Normal/Fast Memory (≥128 Kbytes),
Single Byte Access 6-44
6.22 Write Cycle, Normal/Fast Memory (≥128 Kbytes),
Single Byte Access 6-45
6.23 Read Cycle, Normal/Fast Memory (≥128 Kbyte),
Multiple Byte Access 6-46
6.24 Write Cycle, Normal/Fast Memory (≥128 Kbyte),
Multiple Byte Access 6-48
6.25 Read Cycle, Slow Memory (≥128 Kbytes) 6-50
6.26 Write Cycle, Slow Memory (≥128 Kbytes) 6-51
6.28 Read Cycle, 16 Kbytes ROM 6-52
6.27 Read Cycle, 16 Kbytes ROM 6-52
6.29 Write Cycle, 16 Kbytes ROM 6-53
6.30 Initiator Asynchronous Send 6-55
6.31 Initiator Asynchronous Receive 6-56
6.32 Target Asynchronous Send 6-57
6.33 Target Asynchronous Receive 6-57
6.34 Initiator and Target Synchronous Transfers 6-58
6.35 256-pin PBGA (GU) Mechanical Drawing 6-61
6.36 208-pin PQFP (P9) Mechanical Drawing (Sheet 1 of 2) 6-62
B.1 64 Kbyte Interface with 200 ns Memory B-1
B.2 64 Kbyte Interface with 150 ns Memory B-2
B.3 256 Kbyte Interface with 150 ns Memory B-3
B.4 512 Kbyte Interface with 150 ns Memory B-4
Tables 2.1 PCI Bus Commands and Encoding Types 2-4
2.2 Bits Used for Parity Control and Generation 2-18
2.3 SCSI Parity Control 2-19

xii Contents
2.4 SCSI Parity Errors and Interrupts 2-19
2.5 Differential Mode 2-25
2.6 Parallel ROM Support 2-44
2.7 Mode A Serial EEPROM Data Format 2-46
2.8 Mode C Serial EEPROM Data Format 2-47
2.9 Power States 2-48
3.1 System Signals 3-6
3.2 Address and Data Signals 3-7
3.3 Interface Control Signals 3-8
3.4 Arbitration Signals 3-9
3.5 Error Reporting Signals 3-9
3.6 PCI Interrupt Signals 3-10
3.7 SCSI GPIO Function A Signals 3-11
3.8 SCSI GPIO Function B Signals 3-12
3.9 SCSI Bus Interface Signal 3-13
3.10 SCSI Function A Interface Signals 3-14
3.11 SCSI Function B Interface Signals 3-15
3.12 SCSI Function A Differential Control Signals 3-16
3.13 SCSI Function B Differential Control Signals 3-17
3.14 ROM/Flash Interface Signals 3-18
3.15 Test Interface Signals 3-19
3.16 Power and Ground Signals 3-20
3.17 Decode of MAD Pins 3-22
4.1 PCI to SCSI Configuration Register Map 4-2
4.2 LSI53C876 SCSI Register Address Map 4-21
4.3 Examples of Synchronous Transfer Periods for SCSI-1
Transfer Rates 4-35
4.4 Example Transfer Periods for Fast SCSI and Wide Ultra
SCSI Transfer Rates 4-35
4.5 Maximum Synchronous Offset 4-36
4.6 SCSI Synchronous Data FIFO Word Count 4-46
5.1 SCRIPTS Instructions 5-3
5.2 Read/Write Instructions 5-25
6.1 Absolute Maximum Stress Ratings 6-2
6.2 Operating Conditions 6-2
6.3 SCSI Signals—SD[15:0]/, SDP[1:0]/, SREQ/, SACK/ 6-3
6.4 SCSI Signals—SMSG, SI_O/, SC_D/, SATN/, SBSY/,
SSEL/, SRST/ 6-3

Contents xiii
6.5 Input Signals—CLK, SCLK, GNT/, IDSEL, RST/,
TESTIN, DIFFSENS 6-3
6.6 Capacitance 6-4
6.7 Output Signals—INTA/, INTB/ 6-4
6.8 Output Signals—SDIR[15:0], SDIRP0, SDIRP1, BSYDIR,
SELDIR, RSTDIR, TGS, IGS, MAS/[1:0], MCE/,
MOE/_TESTOUT, MWE/ 6-4
6.9 Output Signal—REQ/ 6-5
6.10 Output Signal—SERR/ 6-5
6.11 Bidirectional Signals—AD[31:0], C_BE/[3:0], FRAME/,
IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR 6-5
6.12 Bidirectional Signals—GPIO0_FETCH/,
GPIO1_MASTER/, GPIO2, GPIO3, GPIO4 6-6
6.13 Bidirectional Signals—MAD[7:0] 6-6
6.14 Input Signals—TDI, TMS, TCK 6-6
6.15 Output Signal—TDO 6-7
6.16 Bidirectional Signals—AD[31:0], C_BE[3:0]/, FRAME/,
IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR 6-7
6.17 Input Signals—CLK, GNT/, IDSEL, RST/, 6-7
6.18 Output Signals—INTA/, INTB, REQ/ 6-8
6.19 Output Signal—SERR/ 6-8
6.20 TolerANT Technology Electrical Characteristics 6-9
6.21 Clock Timing 6-12
6.22 Reset Input 6-13
6.23 Interrupt Output 6-14
6.24 3.3 V PCI Timing 6-16
6.25 Configuration Register Read 6-17
6.26 Configuration Register Write 6-18
6.27 Target Read (Not From External Memory) 6-19
6.28 Target Write (Not From External Memory) 6-20
6.29 Target Read (From External Memory) 6-21
6.30 Target Write (From External Memory) 6-25
6.31 Opcode Fetch, Nonburst 6-28
6.32 Opcode Fetch, Burst 6-30
6.33 Back-to-Back Read 6-32
6.34 Back-to-Back Write 6-34
6.35 Burst Read 6-37
6.36 Burst Write 6-41

xiv Contents
6.37 Read Cycle, Norma/Fast Memory (≥128 Kbytes),
Single Byte Access 6-44
6.38 Write Cycle, Normal/Fast Memory (≥128 Kbytes),
Single Byte Access 6-45
6.39 Read Cycle, Slow Memory (≥128 Kbytes) 6-50
6.40 Write Cycle, Slow Memory (≥128 Kbytes) 6-51
6.41 Write Cycle, 16 Kbytes ROM 6-53
6.42 LSI53C876 PCI and External Memory Interface Timing 6-54
6.43 Initiator Asynchronous Send 6-55
6.44 Initiator Asynchronous Receive 6-56
6.45 Target Asynchronous Send 6-57
6.46 Target Asynchronous Receive 6-57
6.47 SCSI-1 Transfers (SE, 5.0 Mbytes/s) 6-58
6.48 SCSI-2 Fast Transfers (10.0 Mbytes/s (8-Bit Transfers) or
20.0 Mbytes/s (16-Bit Transfers), 40 MHz Clock 6-59
6.49 SCSI-2 Fast-20 SE Transfers (20.0 Mbytes/s
(8-Bit Transfers) or 40.0 Mbytes/s (16-Bit Transfers),
80 MHz Clock) with Clock Doubled Internally 6-59
A.1 Configuration Registers A-1
A.2 SCSI Registers A-2

LSI53C876/876E PCI to Dual Channel SCSI Multifunction Controller 1-1
Chapter 1
General Description
This chapter includes the following sections:
•Section 1.1, “Wide Ultra SCSI Benefits”
•Section 1.2, “TolerANT®Technology”
•Section 1.3, “LSI53C876 Benefits”
This manual combines information for the LSI53C876 and LSI53C876E,
which are a PCI to dual SCSI controllers. The LSI53C876E is a minor
modification of the existing LSI53C876 product. It has all of the
functionality of the LSI53C876 with the addition of features to enable it
to comply with the Microsoft PC 97 Hardware Design Guide. Specifically,
the LSI53C876E has a Power Management Support enhancement.
Because there are only slight differences between them, the LSI53C876
and LSI53C876E are referred to as LSI53C876 throughout this technical
manual. Only the new enhancements are referred to as LSI53C876E.
The LSI53C876 PCI to Dual Channel SCSI Multifunction Controller is a
PCI 2.1 compliant device. It implements two LSI53C875 PCI to Ultra
SCSI controllers on a single chip. The LSI53C876 presents only one load
to the PCI bus, and it uses one REQ/ - GNT/ signal pair in arbitration for
PCI bus mastership.
Two packaging options are available. The 208-pin Plastic Quad Flat Pack
(PQFP) provides a differential Single-Ended (SE) SCSI interface on SCSI
Function A and an SE interface on SCSI Function B. The 256-bump Ball
Grid Array (BGA) provides a differential SE interface on both SCSI
Function A and SCSI Function B.
The LSI53C876 has a local memory bus for storage of the device’s BIOS
ROM in Flash memory or standard EPROMs. The LSI53C876 supports
programming of local Flash memory for updates to BIOS or SCRIPTS™
programs.

1-2 General Description
The LSI53C876 reduces the requirement for system BIOS support and
PCI bus bandwidth. It also supports the Wide Ultra SCSI standard. The
LSI53C876 performs Wide Ultra SCSI transfers or Fast SCSI transfers,
and it improves performance by optimizing PCI bus utilization. Figure 1.1
illustrates a typical LSI53C876 system and Figure 1.2 illustrates a typical
LSI53C876 board application.
Figure 1.1 Typical LSI53C876 System Application
Fixed Disk, Optical Disk,
Printer, Tape, and Other
Peripherals
Fixed Disk, Optical Disk,
Printer, Tape, and Other
Peripherals
One PCI Bus Load
PCI Graphic Accelerator
PCI Sound Card
Memory
Controller
Memory
PCI Bus
Interface
Controller
Central
Processing
Unit
(CPU) Typical PCI Computer
System Architecture
Processor Bus
LSI53C876 PCI
to Wide Ultra SCSI
Function A
and
LSI53C876 PCI
to Wide Ultra SCSI
Function B
SCSI Bus
SCSI Bus

1-3
Figure 1.2 Typical LSI53C876 Board Application
The LSI53C876 integrates a high-performance SCSI core, a PCI bus
master DMA core, and the LSI Logic SCSI SCRIPTS processor to meet
the flexibility requirements of SCSI, Fast SCSI, and Wide Ultra SCSI
standards. It is designed to implement multithreaded I/O algorithms with
a minimum of processor intervention, solving the protocol overhead
problems of previous intelligent and nonintelligent controller designs.
The LSI53C876 is fully supported by the LSI Logic Storage Device
Management System (SDMS™), a software package that supports the
Advanced SCSI Protocol Interface (ASPI). SDMS software provides
BIOS and driver support for hard disk, tape, removable media products,
and CD-ROM under the major PC operating systems.
In addition, LSI Logic provides a SYMplicity™ I2O Hardware Device
Module for the LSI53C876 to support the device in I2O-ready systems.
The SYMplicity I2O architecture is compliant with the I2O specification.
I2O is a split driver architecture that increases system efficiency by
transferring I/O intensive processing tasks from the host CPU to
intelligent peripheral platforms.
Flash EEPROM
Serial EEPROM
Function A
Serial EEPROM
Function B
Memory Control
Block
LSI53C876
PCI
to
Dual Channel SCSI
Multifunction
Function A
68 Pin
Wide SCSI
Connector
SCSI Data,
Parity, and
Control Signals
Function B
68 Pin
Wide SCSI
Connector
SCSI Data,
Parity, and
Control Signals
PCI Interface
PCI Address, Data, Parity and Control Signals
Memory
Address/Data
Bus
A_GPIO/[1:0]
B_GPIO/[1:0]
Controller

1-4 General Description
1.1 Wide Ultra SCSI Benefits
Wide Ultra SCSI is an extension of the SCSI-3 family of standards that
expands the bandwidth of the SCSI bus and allows faster synchronous
SCSI transfer rates. When enabled, Wide Ultra SCSI performs
40 megatransfers per second during an I/O operation, resulting in
approximately twice the synchronous transfer rates of Fast SCSI. The
LSI53C876 can perform Ultra SCSI synchronous transfers at
20 Mbytes/s. It can also perform Wide Ultra SCSI transfers at
40 Mbytes/s. This advantage is most noticeable in heavily loaded
systems or large block size requirements, such as video on-demand and
image processing.
An advantage of Wide Ultra SCSI is that it significantly improves SCSI
bandwidth while preserving existing hardware and software investments.
The LSI53C876 is compatible with all existing LSI53C875 software.
1.2 TolerANT®Technology
The LSI53C876 features TolerANT technology, which includes active
negation on the SCSI drivers and input signal filtering on the SCSI
receivers. Active negation actively drives the SCSI Request,
Acknowledge, Data, and Parity signals HIGH rather than allowing them
to be passively pulled up by terminators. Active negation is enabled by
setting bit 7 in the SCSI Test Three (STEST3) register.
TolerANT receiver technology improves data integrity in unreliable
cabling environments where other devices would be subject to data
corruption. TolerANT receivers filter the SCSI bus signals to eliminate
unwanted transitions, without the long signal delay associated with
RC-type input filters. This improved driver and receiver technology helps
eliminate double clocking of data, the single biggest reliability issue with
SCSI operations. TolerANT input signal filtering is a built in feature of the
LSI53C876 and all LSI Logic Fast SCSI and Ultra SCSI devices.
The benefits of TolerANT technology include increased immunity to noise
on the deasserting signal edge, better performance due to balanced duty
cycles, and improved Fast SCSI transfer rates. In addition, TolerANT
SCSI devices do not cause glitches on the SCSI bus at power-up or

LSI53C876 Benefits 1-5
power-down, so other devices on the bus are also protected from data
corruption. TolerANT technology is compatible with both the Alternative
One and Alternative Two termination schemes proposed by the American
National Standards Institute (ANSI).
1.3 LSI53C876 Benefits
This section provides an overview of the LSI53C876 features and
benefits. It contains information on PCI Performance,SCSI Performance,
Testability,Integration, and Reliability.
1.3.1 PCI Performance
To improve SCSI performance, the LSI53C876:
•Complies with PCI 2.1 specification
•Presents a single electrical load to the PCI bus (True PCI
multifunction device).
•Supports 32-bit word data bursts with variable burst lengths of 2, 4,
8, 16, 32, 64 or 128 Dwords across the PCI bus.
•Prefetches up to 8 Dwords of SCSI SCRIPTS.
•Bursts SCSI SCRIPTS opcode fetches across the PCI bus.
•Performs zero wait-state bus master data bursts up to 132 Mbytes/s
(@ 33 MHz).
•Supports PCI Cache Line Size register.
•Supports PCI Write and Invalidate, Read Line, and Read Multiple
commands.
•Complies with PCI Bus Power Management Specification
(LSI53C876E) Revision 1.0.
1.3.2 SCSI Performance
To improve SCSI performance, the LSI53C876:
•Includes 4 Kbytes internal RAM on each channel for SCRIPTS
instruction storage.
•Wide Ultra SCSI SE Interface.

1-6 General Description
•Performs Wide Ultra SCSI synchronous transfers as fast as
40 Mbytes/s.
•Supports 536-byte DMA FIFO for more effective PCI and SCSI bus
utilization.
•Supports 16 levels of SCSI synchronous offset.
•Supports variable block size and scatter/gather data transfers
•Minimizes SCSI I/O start latency.
•Performs complex bus sequences without interrupts, including
restore data pointers.
•Reduces interrupt service routine overhead through a unique
interrupt status reporting method.
•Supports Load and Store SCRIPTS instructions to increase the
performance of data transfers to and from chip registers.
•Supports target disconnect and later reconnect with no interrupt to
the system processor.
•Supports multithreaded I/O algorithms in SCSI SCRIPTS with fast
I/O context switching.
•Supports expanded Register Move instructions.
•Compatible with LSI53C875 software (drivers and SCRIPTS).
•Enables Ultra SCSI with 40 MHz SCSI clock input with integrated
clock doubler.
1.3.3 Testability
The LSI53C876 contains these testability features:
•All SCSI signals accessible through programmed I/O.
•SCSI loopback diagnostics.
•SCSI bus signal continuity checking.
•Support for single step mode operation.
•Test mode (AND-tree) to check pin continuity to the board.