Microchip Technology PIC16C62B/72A User manual

1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 1
Microcontroller Core Features:
• High-performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches, which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• 2K x 14 words of Program Memory,
128 x 8 bytes of Data Memory (RAM)
• Interrupt capability
• Eight level deep hardware stack
• Direct, indirect, and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Brown-out detection circuitry for
Brown-out Reset (BOR)
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options
• Low-power, high-speed CMOS EPROM
technology
• Fully static design
• In-Circuit Serial Programming(ICSP)
• Wide operating voltage range: 2.5V to 5.5V
• High Sink/Source Current 25/25 mA
• Commercial, Industrial and Extended temperature
ranges
• Low-power consumption:
- < 2 mA @ 5V, 4 MHz
- 22.5 A typical @ 3V, 32 kHz
-<1A typical standby current
Pin Diagram
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during sleep via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Capture, Compare, PWM module
• Capture is 16-bit, max. resolution is 12.5 ns,
Compare is 16-bit, max. resolution is 200 ns,
PWM maximum resolution is 10-bit
• 8-bit multi-channel Analog-to-Digital converter
• Synchronous Serial Port (SSP) with Enhanced
SPI and I2C
PIC16C72A
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/SS/AN4
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7
RC6
RC5/SDO
RC4/SDI/SDA
• 1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SDIP, SOIC, SSOP, Windowed CERDIP
PIC16C62B/72A
28-Pin 8-Bit CMOS Microcontrollers

PIC16C62B/72A
DS35008C-page 2 Preliminary 1998-2013 Microchip Technology Inc.
Pin Diagrams
PIC16C62B
MCLR/VPP
RA0
RA1
RA2
RA3
RA4/T0CKI
RA5/SS
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7
RC6
RC5/SDO
RC4/SDI/SDA
• 1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SDIP, SOIC, SSOP, Windowed CERDIP
Key Features
PIC®Mid-Range Reference Manual (DS33023) PIC16C62B PIC16C72A
Operating Frequency DC - 20 MHz DC - 20 MHz
Resets (and Delays) POR, BOR (PWRT, OST) POR, BOR (PWRT, OST)
Program Memory (14-bit words) 2K 2K
Data Memory (bytes) 128 128
Interrupts 7 8
I/O Ports Ports A,B,C Ports A,B,C
Timers 3 3
Capture/Compare/PWM modules 1 1
Serial Communications SSP SSP
8-bit Analog-to-Digital Module — 5 input channels

PIC16C62B/72A
1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 3
Table of Contents
1.0 Device Overview .................................................................................................................................................... 5
2.0 Memory Organization ............................................................................................................................................. 7
3.0 I/O Ports ............................................................................................................................................................... 19
4.0 Timer0 Module ..................................................................................................................................................... 25
5.0 Timer1 Module ..................................................................................................................................................... 27
6.0 Timer2 Module ..................................................................................................................................................... 31
7.0 Capture/Compare/PWM (CCP) Module ............................................................................................................... 33
8.0 Synchronous Serial Port (SSP) Module ............................................................................................................... 39
9.0 Analog-to-Digital Converter (A/D) Module............................................................................................................ 49
10.0 Special Features of the CPU................................................................................................................................ 55
11.0 Instruction Set Summary ...................................................................................................................................... 67
12.0 Development Support........................................................................................................................................... 75
13.0 Electrical Characteristics ...................................................................................................................................... 81
14.0 DC and AC Characteristics Graphs and Tables................................................................................................. 103
15.0 Packaging Information........................................................................................................................................ 105
Appendix A: Revision History ................................................................................................................................... 111
Appendix B: Conversion Considerations .................................................................................................................. 111
Appendix C: Migration from Base-line to Mid-Range Devices .................................................................................. 112
Index ........................................................................................................................................................................... 113
On-Line Support.......................................................................................................................................................... 117
Reader Response ....................................................................................................................................................... 118
PIC16C62B/72A Product Identification System .......................................................................................................... 119
To Our Valued Customers
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PIC16C62B/72A
DS35008C-page 4 Preliminary 1998-2013 Microchip Technology Inc.
NOTES:

PIC16C62B/72A
1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 5
1.0 DEVICE OVERVIEW
This document contains device-specific information.
Additional information may be found in the PIC®MCU
Mid-Range Reference Manual, (DS33023), which may
be obtained from your local Microchip Sales Represen-
tative or downloaded from the Microchip website. The
Reference Manual should be considered a comple-
mentary document to this data sheet, and is highly rec-
ommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.
There are two devices (PIC16C62B, PIC16C72A) cov-
ered by this datasheet. The PIC16C62B does not have
the A/D module implemented.
Figure 1-1 is the block diagram for both devices. The
pinouts are listed in Table 1-1.
FIGURE 1-1: PIC16C62B/PIC16C72A BLOCK DIAGRAM
EPROM
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
Direct Addr 7
RAM Addr(1) 9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR VDD, VSS
PORTA
PORTB
PORTC
RB0/INT
RB7:RB1
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6
RC7
8
8
Brown-out
Reset
Note 1: Higher order bits are from the STATUS register.
2: The A/D module is not available on the PIC16C62B.
CCP1 Synchronous A/D(2)
Timer0 Timer1 Timer2
Serial Port
RA4/T0CKI
RA5/SS/AN4(2)
RA3/AN3/VREF(2)
RA2/AN2(2)
RA1/AN1(2)
RA0/AN0(2)
8
3
2K x 14
128 x 8

PIC16C62B/72A
DS35008C-page 6 Preliminary 1998-2013 Microchip Technology Inc.
TABLE 1-1 PIC16C62B/PIC16C72A PINOUT DESCRIPTION
Pin Name DIP
Pin#
SOIC
Pin#
I/O/P
Type
Buffer
Type Description
OSC1/CLKIN 9 9 I ST/CMOS(3) Oscillator crystal input/external clock source input.
OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, the OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
MCLR/VPP 1 1 I/P ST Master clear (reset) input or programming voltage input. This
pin is an active low reset to the device.
PORTA is a bi-directional I/O port.
RA0/AN0(4) 2 2 I/O TTL RA0 can also be analog input 0
RA1/AN1(4) 3 3 I/O TTL RA1 can also be analog input 1
RA2/AN2(4) 4 4 I/O TTL RA2 can also be analog input 2
RA3/AN3/VREF(4) 5 5 I/O TTL RA3 can also be analog input 3 or analog reference voltage
RA4/T0CKI 6 6 I/O ST RA4 can also be the clock input to the Timer0 module.
Output is open drain type.
RA5/SS/AN4(4) 7 7 I/O TTL RA5 can also be analog input 4 or the slave select for the
synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT 21 21 I/O TTL/ST(1) RB0 can also be the external interrupt pin.
RB1 22 22 I/O TTL
RB2 23 23 I/O TTL
RB3 24 24 I/O TTL
RB4 25 25 I/O TTL Interrupt on change pin.
RB5 26 26 I/O TTL Interrupt on change pin.
RB6 27 27 I/O TTL/ST(2) Interrupt on change pin. Serial programming clock.
RB7 28 28 I/O TTL/ST(2) Interrupt on change pin. Serial programming data.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1
clock input.
RC1/T1OSI 12 12 I/O ST RC1 can also be the Timer1 oscillator input.
RC2/CCP1 13 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL 14 14 I/O ST RC3 can also be the synchronous serial clock input/output
for both SPI and I2C modes.
RC4/SDI/SDA 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or
data I/O (I2C mode).
RC5/SDO 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode).
RC6 17 17 I/O ST
RC7 18 18 I/O ST
VSS 8, 19 8, 19 P — Ground reference for logic and I/O pins.
VDD 20 20 P — Positive supply for logic and I/O pins.
Legend: I = input O = output I/O = input/output P = power or program
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
4: The A/D module is not available on the PIC16C62B.

PIC16C62B/72A
1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 7
2.0 MEMORY ORGANIZATION
There are two memory blocks in each of these micro-
controllers. Each block (Program Memory and Data
Memory) has its own bus, so that concurrent access
can occur.
Additional information on device memory may be found
in the PICmicroMid-Range Reference Manual,
(DS33023).
2.1 Program Memory Organization
The PIC16C62B/72A devices have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. Each device has 2K x 14 words of pro-
gram memory. Accessing a location above 07FFh will
cause a wraparound.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK
PC<12:0>
13
0000h
0004h
0005h
07FFh
0800h
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
On-chip Program
Memory
CALL, RETURN
RETFIE, RETLW
User Memory
Space

PIC16C62B/72A
DS35008C-page 8 Preliminary 1998-2013 Microchip Technology Inc.
2.2 Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.
= 00 Bank0
= 01 Bank1
= 10 Bank2 (not implemented)
= 11 Bank3 (not implemented)
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some “high use” Special Function
Registers from one bank may be mirrored in another
bank for code reduction and quicker access.
2.2.1 GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indi-
rectly through the File Select Register FSR
(Section 2.5).
FIGURE 2-2: REGISTER FILE MAP
RP1(1) RP0 (STATUS<6:5>)
Note 1: Maintain this bit clear to ensure upward compati-
bility with future products.
Unimplemented data memory locations,
read as '0'.
Note 1: Not a physical register.
2: These registers are not implemented on the
PIC16C62B, read as '0'.
File
Address
File
Address
00h INDF(1) INDF(1) 80h
01h TMR0 OPTION_REG 81h
02h PCL PCL 82h
0 3 h S TAT U S S TAT U S 8 3 h
04h FSR FSR 84h
05h PORTA TRISA 85h
06h PORTB TRISB 86h
07h PORTC TRISC 87h
08h — — 88h
09h — — 89h
0Ah PCLATH PCLATH 8Ah
0Bh INTCON INTCON 8Bh
0Ch PIR1 PIE1 8Ch
0Dh — — 8Dh
0Eh TMR1L PCON 8Eh
0Fh TMR1H —8Fh
10h T1CON —90h
11h TMR2 —91h
12h T2CON PR2 92h
13h SSPBUF SSPADD 93h
14h SSPCON SSPSTAT 94h
15h CCPR1L —95h
16h CCPR1H —96h
17h CCP1CON —97h
18h — — 98h
19h — — 99h
1Ah — — 9Ah
1Bh — — 9Bh
1Ch — — 9Ch
1Dh — — 9Dh
1Eh ADRES(2) —9Eh
1Fh ADCON0(2) ADCON1(2) 9Fh
20h
General
Purpose
Registers
General
Purpose
Registers
A0h
BFh
—C0h
—
7Fh —FFh
Bank 0 Bank 1

PIC16C62B/72A
1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 9
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The Special Function Registers can be classified into
two sets; core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
TABLE 2-1 SPECIAL FUNCTION REGISTER SUMMARY
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Value on all
other resets
(4)
Bank 0
00h INDF(1) Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
02h PCL(1) Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
03h STATUS(1) IRP(5) RP1(5) RP0 TO PD ZDCC0001 1xxx 000q quuu
04h FSR(1) Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA(6,7) —— PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000
06h PORTB(6,7) PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC(6,7) PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h-09h —Unimplemented — —
0Ah PCLATH(1,2) — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
0Bh INTCON(1) GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —ADIF
(3) —— SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
0Dh —Unimplemented — —
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON —— CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h-1Dh —Unimplemented — —
1Eh ADRES(3) A/D Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0(3) ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON0000 00-0 0000 00-0
Legend: x= unknown, u= unchanged, q= value depends on condition, -= unimplemented, read as '0',
Shaded locations are unimplemented, read as '0'.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents
are transferred to the upper byte of the program counter.
3: A/D not implemented on the PIC16C62B, maintain as ’0’.
4: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
5: The IRP and RP1 bits are reserved. Always maintain these bits clear.
6: On any device reset, these pins are configured as inputs.
7: This is the value that will be in the port output latch.

PIC16C62B/72A
DS35008C-page 10 Preliminary 1998-2013 Microchip Technology Inc.
Bank 1
80h INDF(1) Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h PCL(1) Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
83h STATUS(1) IRP(5) RP1(5) RP0 TO PD ZDCC0001 1xxx 000q quuu
84h FSR(1) Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA —— PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h-89h —Unimplemented — —
8Ah PCLATH(1,2) — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
8Bh INTCON(1) GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1 —ADIE
(3) —— SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
8Dh —Unimplemented — —
8Eh PCON — — — — — —PORBOR ---- --qq ---- --uu
8Fh-91h —Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 0000 0000
95h-9Eh —Unimplemented — —
9Fh ADCON1(3) — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Legend: x= unknown, u= unchanged, q= value depends on condition, -= unimplemented, read as '0',
Shaded locations are unimplemented, read as '0'.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents
are transferred to the upper byte of the program counter.
3: A/D not implemented on the PIC16C62B, maintain as ’0’.
4: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
5: The IRP and RP1 bits are reserved. Always maintain these bits clear.
6: On any device reset, these pins are configured as inputs.
7: This is the value that will be in the port output latch.
TABLE 2-1 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Value on all
other resets
(4)

PIC16C62B/72A
1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 11
2.2.2.1 STATUS REGISTER
The STATUS register, shown in Register 2-1, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, the write to these three bits is dis-
abled. These bits are set or cleared according to the
device logic. The TO and PD bits are not writable. The
result of an instruction with the STATUS register as
destination may be different than intended.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u= unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions, not affecting any status bits, see the
"Instruction Set Summary."
REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h)
Note 1: The IRP and RP1 bits are reserved. Main-
tain these bits clear to ensure upward
compatibility with future products.
Note 2: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions.
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC C R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: IRP: Register Bank Select bit (used for indirect addressing)
(reserved, maintain clear)
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
Note: RP1 is reserved, maintain clear
bit 4: TO: Time-out bit
1= After power-up, CLRWDT instruction, or SLEEP instruction
0= A WDT time-out occurred
bit 3: PD: Power-down bit
1= After power-up or by the CLRWDT instruction
0= By execution of the SLEEP instruction
bit 2: Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
bit 1: DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is reversed)
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
bit 0: C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is reversed)
1= A carry-out from the most significant bit of the result occurred
0= No carry-out from the most significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.

PIC16C62B/72A
DS35008C-page 12 Preliminary 1998-2013 Microchip Technology Inc.
2.2.2.2 OPTION_REG REGISTER
The OPTION_REG register is a readable and writable
register, which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assign-
able register known as the prescaler), the External INT
Interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 2-2: OPTION_REG REGISTER (ADDRESS 81h)
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit
W = Writable bit
- n = Value at POR reset
bit7 bit0
bit 7: RBPU: PORTB Pull-up Enable bit
1= PORTB pull-ups are disabled
0= PORTB pull-ups are enabled for all PORTB inputs
bit 6: INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of RB0/INT pin
0= Interrupt on falling edge of RB0/INT pin
bit 5: T0CS: TMR0 Clock Source Select bit
1= Transition on RA4/T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
bit 4: T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on RA4/T0CKI pin
0= Increment on low-to-high transition on RA4/T0CKI pin
bit 3: PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
bit 2-0: PS2:PS0: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate

PIC16C62B/72A
1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 13
2.2.2.3 INTCON REGISTER
The INTCON Register is a readable and writable regis-
ter, which contains various interrupt enable and flag
bits for the TMR0 register overflow, RB Port change
and External RB0/INT pin interrupts.
REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh)
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit
W = Writable bit
- n = Value at POR reset
bit7 bit0
bit 7: GIE: Global Interrupt Enable bit
1= Enables all un-masked interrupts
0= Disables all interrupts
bit 6: PEIE: Peripheral Interrupt Enable bit
1= Enables all un-masked peripheral interrupts
0= Disables all peripheral interrupts
bit 5: T0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 interrupt
0= Disables the TMR0 interrupt
bit 4: IINTE: RB0/INT External Interrupt Enable bit
1= Enables the RB0/INT external interrupt
0= Disables the RB0/INT external interrupt
bit 3: RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
bit 2: T0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (software must clear bit)
0= TMR0 register did not overflow
bit 1: INTF: RB0/INT External Interrupt Flag bit
1= The RB0/INT external interrupt occurred (software must clear bit)
0= The RB0/INT external interrupt did not occur
bit 0: RBIF: RB Port Change Interrupt Flag bit
1= At least one of the RB7:RB4 input pins have changed state (clear by reading PORTB)
0= None of the RB7:RB4 input pins have changed state

PIC16C62B/72A
DS35008C-page 14 Preliminary 1998-2013 Microchip Technology Inc.
2.2.2.4 PIE1 REGISTER
This register contains the individual enable bits for the
peripheral interrupts.
REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch)
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
—ADIE(1) — — SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: Unimplemented: Read as ‘0’
bit 6: ADIE(1): A/D Converter Interrupt Enable bit
1= Enables the A/D interrupt
0= Disables the A/D interrupt
bit 5-4: Unimplemented: Read as ‘0’
bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit
1= Enables the SSP interrupt
0= Disables the SSP interrupt
bit 2: CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Note 1: The PIC16C62B does not have an A/D module. This bit location is reserved on these devices. Always maintain this
bit clear.

PIC16C62B/72A
1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 15
2.2.2.5 PIR1 REGISTER
This register contains the individual flag bits for the
Peripheral interrupts.
REGISTER 2-5: PIR1 REGISTER (ADDRESS 0Ch)
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
—ADIF(1) — — SSPIF CCP1IF TMR2IF TMR1IF R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: Unimplemented: Read as ‘0’
bit 6: ADIF(1): A/D Converter Interrupt Flag bit
1= An A/D conversion completed (must be cleared in software)
0= The A/D conversion is not complete
bit 5-4: Unimplemented: Read as ‘0’
bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit
1= The transmission/reception is complete (must be cleared in software)
0= Waiting to transmit/receive
bit 2: CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare Mode
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
Note 1: The PIC16C62B does not have an A/D module. This bit location is reserved on these devices. Always maintain this
bit clear.

PIC16C62B/72A
DS35008C-page 16 Preliminary 1998-2013 Microchip Technology Inc.
2.2.2.6 PCON REGISTER
The Power Control register (PCON) contains flag bits to
allow differentiation between a Power-on Reset (POR),
Brown-Out Reset (BOR) and resets from other
sources. .
REGISTER 2-6: PCON REGISTER (ADDRESS 8Eh)
Note: On Power-on Reset, the state of the BOR
bit is unknown and is not predictable.
If the BODEN bit in the configuration word
is set, the user must first set the BOR bit on
a POR, and check it on subsequent resets.
If BOR is cleared while POR remains set,
a Brown-out reset has occurred.
If the BODEN bit is clear, the BOR bit may
be ignored.
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q
— — — — — —PORBOR R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7-2: Unimplemented: Read as '0'
bit 1: POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0: BOR: Brown-out Reset Status bit
1= No Brown-out Reset occurred
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

PIC16C62B/72A
1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 17
2.3 PCL and PCLATH
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 13 bits
wide. The low byte is called the PCL register and is
readable and writable. The high byte is called the PCH
register. This register contains the PC<12:8> bits and
is not directly accessible. All updates to the PCH regis-
ter go through the PCLATH register.
2.3.1 STACK
The stack allows any combination of up to 8 program
calls and interrupts to occur. The stack contains the
return address from this branch in program execution.
Mid-range devices have an 8 level deep hardware
stack. The stack space is not part of either program or
data space and the stack pointer is not accessible. The
PC is PUSHed onto the stack when a CALL instruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a RETURN, RETLW or a RET-
FIE instruction execution. PCLATH is not modified
when the stack is PUSHed or POPed.
After the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
2.4 Program Memory Paging
The CALL and GOTO instructions provide 11 bits of
address to allow branching within any 2K program
memory page. When doing a CALL or GOTO instruction,
the upper bit of the address is provided by
PCLATH<3>. The user must ensure that the page
select bit is programmed to address the proper pro-
gram memory page. If a return from a CALL instruction
(or interrupt) is executed, the entire 13-bit PC is popped
from the stack. Therefore, manipulation of the
PCLATH<3> bit is not required for the return instruc-
tions.

PIC16C62B/72A
DS35008C-page 18 Preliminary 1998-2013 Microchip Technology Inc.
2.5 Indirect Addressing, INDF and FSR
Registers
The INDF register is not a physical register. Address-
ing INDF actually addresses the register whose
address is contained in the FSR register (FSR is a
pointer ).
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-1.
EXAMPLE 2-1: HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
movlw 0x20 ;initialize pointer
movwf FSR ; to RAM
NEXT clrf INDF ;clear INDF register
incf FSR ;inc pointer
btfss FSR,4 ;all done?
goto NEXT ;NO, clear next
CONTINUE
: ;YES, continue
An effective 9-bit address is obtained by concatenating
the 8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 2-3. However, IRP is not used in the
PIC16C62B/72A.
FIGURE 2-3: DIRECT/INDIRECT ADDRESSING
Note 1: Maintain clear for upward compatibility with future products.
2: Not implemented.
Data
Memory
Indirect AddressingDirect Addressing
bank select location select
RP1:RP0 6 0
from opcode IRP FSR register 70
bank select location select
00 01 10 11
Bank 0 Bank 1 Bank 2 Bank 3
not used
FFh
80h
7Fh
00h
17Fh
100h
1FFh
180h
(1) (1)
(2) (2)

PIC16C62B/72A
1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 19
3.0 I/O PORTS
Some I/O port pins are multiplexed with an alternate
function for the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Additional information on I/O ports may be found in the
PIC®MCU Mid-Range Reference Manual, (DS33023).
3.1 PORTA and the TRISA Register
PORTA is a 6-bit wide bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (=1) will make the corresponding PORTA pin
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISA bit (=0) will
make the corresponding PORTA pin an output, (i.e., put
the contents of the output latch on the selected pin).
The PORTA register reads the state of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. There-
fore, a write to a port implies that the port pins are read,
this value is modified, and then written to the port data
latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other RA port pins have TTL input levels and full
CMOS output drivers.
Pin RA5 is multiplexed with the SSP to become the
RA5/SS pin.
On the PIC16C72A device, other PORTA pins are mul-
tiplexed with analog inputs and analog VREF input. The
operation of each pin is selected by clearing/setting the
control bits in the ADCON1 register (A/D Control
Register1).
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
FIGURE 3-1: BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
FIGURE 3-2: BLOCK DIAGRAM OF
RA4/T0CKI PIN
Note: On a Power-on Reset, pins with analog
functions are configured as analog inputs
with digital input buffers disabled . A digital
read of these pins will return ’0’.
Data
Bus
QD
Q
CK
QD
Q
CK
QD
EN
P
N
WR
Port
WR
TRIS
Data Latch
TRIS Latch
RD TRIS
RD PORT
VSS
VDD
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and
VSS.
Analog
input
mode
TTL
input
buffer
To A/D Converter (72A only)
(72A
only)
Data
Bus
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
input
buffer
N
VSS
I/O pin(1)
TMR0 clock input
QD
Q
CK
QD
Q
CK
EN
QD
EN
Note 1: I/O pin has protection diodes to VSS only.

PIC16C62B/72A
DS35008C-page 20 Preliminary 1998-2013 Microchip Technology Inc.
TABLE 3-1 PORTA FUNCTIONS
TABLE 3-2 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit# Buffer Function
RA0/AN0 bit0 TTL Input/output or analog input(1)
RA1/AN1 bit1 TTL Input/output or analog input(1)
RA2/AN2 bit2 TTL Input/output or analog input(1)
RA3/AN3/VREF bit3 TTL Input/output or analog input(1) or VREF(1)
RA4/T0CKI bit4 ST
Input/output or external clock input for Timer0
Output is open drain type
RA5/SS/AN4 bit5 TTL Input/output or slave select input for synchronous serial port or analog input(1)
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: The PIC16C62B does not implement the A/D module.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR,
BOR
Value on all
other resets
05h PORTA
(for PIC16C72A only)
—— RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
05h PORTA
(for PIC16C62B only)
—— RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu
85h TRISA —— PORTA Data Direction Register --11 1111 --11 1111
9Fh ADCON1(1) — — — — —PCFG2PCFG1PCFG0---- -000 ---- -000
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by PORTA.
Note 1: The PIC16C62B does not implement the A/D module. Maintain this register clear.