Microchip Technology PIC12F1501 User manual

2011-2015 Microchip Technology Inc. DS40001609E-page 1
PIC16(L)F1508/9
High-Performance RISC CPU:
• C Compiler Optimized Architecture
• Only 49 Instructions
• Operating Speed:
- DC – 20 MHz clock input
- DC – 200 ns instruction cycle
• Interrupt Capability with Automatic Context
Saving
• 16-Level Deep Hardware Stack with Optional
Overflow/Underflow Reset
• Direct, Indirect and Relative Addressing modes:
- Two full 16-bit File Select Registers (FSRs)
- FSRs can read program and data memory
Flexible Oscillator Structure:
• 16 MHz Internal Oscillator Block:
- Factory calibrated to ±1%, typical
- Software selectable frequency range from
16 MHz to 31 kHz
• 31 kHz Low-Power Internal Oscillator
• Three External Clock modes up to 20 MHz
Special Microcontroller Features:
• Operating Voltage Range:
- 1.8V to 3.6V (PIC16LF1508/9)
- 2.3V to 5.5V (PIC16F1508/9)
• Self-Programmable under Software Control
• Power-on Reset (POR)
• Power-up Timer (PWRT)
• Programmable Low-Power Brown-out Reset
(LPBOR)
• Extended Watchdog Timer (WDT):
- Programmable period from 1 ms to 256s
• Programmable Code Protection
• In-Circuit Serial Programming™ (ICSP™) via Two
Pins
• Enhanced Low-Voltage Programming (LVP)
• In-Circuit Debug (ICD) via Two Pins
• Power-Saving Sleep mode:
- Low-Power Sleep mode
- Low-Power BOR (LPBOR)
• Integrated Temperature Indicator
• 128 Bytes High-Endurance Flash
- 100,000 write Flash endurance (minimum)
Memory:
• Up to 8 Kwords Linear Program Memory
Addressing
• Up to 512 bytes Linear Data Memory Addressing
• High-Endurance Flash Data Memory (HEF)
- 128 bytes if nonvolatile data storage
- 100k erase/write cycles
eXtreme Low-Power (XLP)
Features(PIC16LF1508/9):
• Sleep Current:
- 20 nA @ 1.8V, typical
• Watchdog Timer Current:
- 260 nA @ 1.8V, typical
• Operating Current:
-30A/MHz @ 1.8V, typical
• Secondary Oscillator Current:
- 700 nA @ 32 kHz, 1.8V, typical
Peripheral Features:
• Analog-to-Digital Converter (ADC):
- 10-bit resolution
- 12 external channels
- Three internal channels:
- Fixed Voltage Reference
- Digital-to-Analog Converter (DAC)
- Temperature Indicator channel
- Auto acquisition capability
- Conversion available during Sleep
• 5-Bit Digital-to-Analog Converter (DAC):
- Output available externally
- Positive reference selection
- Internal connections to comparators and ADC
• Two Comparators:
- Rail-to-rail inputs
- Power mode control
- Software controllable hysteresis
• Voltage Reference:
- 1.024V Fixed Voltage Reference (FVR) with
1x, 2x and 4x Gain output levels
• 18 I/O Pins (1 Input-only Pin):
- High current sink/source 25 mA/25 mA
- Individually programmable weak pull-ups
- Individually programmable
Interrupt-on-Change (IOC) pins
• Timer0: 8-Bit Timer/Counter with 8-Bit
Programmable Prescaler
• Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Gate Input mode
• Timer2: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler
• Four 10-bit PWM modules
• Master Synchronous Serial Port (MSSP) with SPI
and I2C with:
- 7-bit address masking
- SMBus/PMBus™ compatibility
20-Pin Flash, 8-Bit Microcontrollers with XLP Technology

PIC16(L)F1508/9
DS40001609E-page 2 2011-2015 Microchip Technology Inc.
Peripheral Features (Continued):
• Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART)
- RS-232, RS-485 and LIN compatible
- Auto-Baud Detect
- Auto-wake-up on Start
• Four Configurable Logic Cell (CLC) modules:
- 16 selectable input source signals
- Four inputs per module
- Software control of combinational/sequential
logic/state/clock functions
- AND/OR/XOR/D Flop/D Latch/SR/JK
- Inputs from external and internal sources
- Output available to pins and peripherals
- Operation while in Sleep
• Numerically Controlled Oscillator (NCO):
- 20-bit accumulator
- 16-bit increment
- True linear frequency control
- High-speed clock input
- Selectable Output modes
- Fixed Duty Cycle (FDC) mode
- Pulse Frequency (PF) mode
• Complementary Waveform Generator (CWG):
- Eight selectable signal sources
- Selectable falling and rising edge dead-band
control
- Polarity control
- Four auto-shutdown sources
- Multiple input sources: PWM, CLC, NCO
PIC12(L)F1501/PIC16(L)F150X FAMILY TYPES
Device
Data Sheet Index
Program Memory
Flash (words)
Data SRAM
(bytes)
I/O’s(2)
10-bit ADC (ch)
Comparators
DAC
Timers
(8/16-bit)
PWM
EUSART
MSSP (I2C/SPI)
CWG
CLC
NCO
Debug(1)
XLP
PIC12(L)F1501 (1) 1024 64 6 4 1 1 2/1 4 — — 1 2 1 H —
PIC16(L)F1503 (2) 2048 128 12 8 2 1 2/1 4 — 1 1 2 1 H —
PIC16(L)F1507 (3) 2048 128 18 12 — — 2/1 4 — — 1 2 1 H —
PIC16(L)F1508 (4) 4096 256 18 12 2 1 2/1 4 1 1 1 4 1 I/H Y
PIC16(L)F1509 (4) 8192 512 18 12 2 1 2/1 4 1 1 1 4 1 I/H Y
Note 1: Debugging Methods: (I) - Integrated on Chip; (H) - using Debug Header; (E) - using Emulation Header.
2: One pin is input-only.
Data Sheet Index: (Unshaded devices are described in this document.)
1: DS40001615 PIC12(L)F1501 Data Sheet, 8-Pin Flash, 8-bit Microcontrollers.
2: DS40001607 PIC16(L)F1503 Data Sheet, 14-Pin Flash, 8-bit Microcontrollers.
3: DS40001586 PIC16(L)F1507 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers.
4: DS40001609 PIC16(L)F1508/9 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers.
Note: For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.

2011-2015 Microchip Technology Inc. DS40001609E-page 3
PIC16(L)F1508/9
PIN DIAGRAMS
PIC16(L)F1508 PIC16(L)F1509
1
2
3
4
14
13
12
11
5
6
7
10
9
8
VDD
RA5
RA4
MCLR/VPP/RA3
RC5
RC4
VSS
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RC0
RC1
RC2
RC3
Note: See Table 1 for location of all peripheral functions.
18
17
16
15
20
19
RC6
RC7
RB7
RB4
RB5
RB6
20-pin PDIP, SOIC, SSOP
PIC16(L)F1508
PIC16(L)F1509
Note 1: See Table 1 for location of all peripheral functions.
2: It is recommended that the exposed bottom pad be connected to VSS.
15 RA1/ICSPCLK
RA2
RC0
RC1
RC2
11
12
13
14
67
RC7
RB7 RB4 RB5 RB6
8910
2
3
1
1819
20 1617
5
4
VDD RA5 RA4
MCLR/VPP/RA3
RC5
RC4
RC3
RC6
VSS RA0/ICSPDAT
20-pin QFN, UQFN

PIC16(L)F1508/9
DS40001609E-page 4 2011-2015 Microchip Technology Inc.
PIN ALLOCATION TABLE
TABLE 1: 20-PIN ALLOCATION TABLE (PIC16(L)F1508/9)
I/O
20-Pin PDIP/SOIC/SSOP
20-Pin QFN/UQFN
ADC
Reference
Comparator
Timers
EUSART
MSSP
CWG
NCO
CLC
PWM
Interrupt
Pull-up
Basic
RA0 19 16 AN0 DAC1OUT1 C1IN+ — — —— — — — IOC YICSPDAT
ICDDAT
RA1 18 15 AN1 VREF+C1IN0-
C2IN0-
——— — — CLC4IN1 —IOC YICSPCLK
ICDCLK
RA2 17 14 AN2 DAC1OUT2 C1OUT T0CKI — — CWG1FLT —CLC1 PWM3 INT/
IOC
Y —
RA3 4 1 — — — T1G(1) —SS
(1) — — CLC1IN0 —IOC YMCLR
VPP
RA4 320 AN3 — — SOSCO
T1G
— — — — — — IOC YCLKOUT
OSC2
RA5 219 — — — SOSCI
T1CKI
—— —NCO1CLK — — IOC YCLKIN
OSC1
RB4 13 10 AN10 — — — — SDA/SDI — — CLC3IN0 —IOC Y —
RB5 12 9AN11 — — —RX/DT— — — CLC4IN0 —IOC Y —
RB6 11 8 — — — — — SCL/SCK — — — — IOC Y —
RB7 10 7 — — — —TX/CK— — — CLC3 —IOC Y —
RC0 16 13 AN4 —C2IN+ — — — — — CLC2 — — — —
RC1 15 12 AN5 —C1IN1-
C2IN1-
——— —NCO1 —PWM4 — — —
RC2 14 11 AN6 —C1IN2-
C2IN2-
— — — — — — — — — —
RC3 7 4 AN7 —C1IN3-
C2IN3-
——— — — CLC2IN0 PWM2 — — —
RC4 6 3 — — C2OUT — — — CWG1B —CLC4
CLC2IN1
— — — —
RC5 5 2 — — — ———CWG1A —CLC1(1) PWM1 — — —
RC6 8 5 AN8 — — — — SS —NCO1(1) CLC3IN1 — — — —
RC7 9 6 AN9 — — ——SDO — — CLC1IN1 — — — —
VDD 118 — — — — — — — — — — — — VDD
VSS 20 17 — — — — — — — — — — — — VSS
Note 1: Alternate pin function selected with the APFCON (Register 11-1)register.

2011-2015 Microchip Technology Inc. DS40001609E-page 5
PIC16(L)F1508/9
TABLE OF CONTENTS
1.0 Device Overview .......................................................................................................................................................................... 8
2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 13
3.0 Memory Organization ................................................................................................................................................................. 15
4.0 Device Configuration .................................................................................................................................................................. 40
5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 46
6.0 Resets ........................................................................................................................................................................................ 62
7.0 Interrupts .................................................................................................................................................................................... 70
8.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 83
9.0 Watchdog Timer (WDT) ............................................................................................................................................................. 86
10.0 Flash Program Memory Control ................................................................................................................................................. 90
11.0 I/O Ports ................................................................................................................................................................................... 106
12.0 Interrupt-On-Change ................................................................................................................................................................ 119
13.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 124
14.0 Temperature Indicator Module ................................................................................................................................................. 126
15.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 128
16.0 5-Bit Digital-to-Analog Converter (DAC) Module...................................................................................................................... 142
17.0 Comparator Module.................................................................................................................................................................. 145
18.0 Timer0 Module ......................................................................................................................................................................... 152
19.0 Timer1 Module with Gate Control............................................................................................................................................. 155
20.0 Timer2 Module ......................................................................................................................................................................... 166
21.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 169
22.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 223
23.0 Pulse-Width Modulation (PWM) Module .................................................................................................................................. 251
24.0 Configurable Logic Cell (CLC).................................................................................................................................................. 257
25.0 Numerically Controlled Oscillator (NCO) Module ..................................................................................................................... 273
26.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 280
27.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 292
28.0 Instruction Set Summary .......................................................................................................................................................... 294
29.0 Electrical Specifications............................................................................................................................................................ 309
30.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 339
31.0 Development Support............................................................................................................................................................... 380
32.0 Packaging Information.............................................................................................................................................................. 384
Appendix A: Data Sheet Revision History.......................................................................................................................................... 397
The Microchip Website ...................................................................................................................................................................... 398
Customer Change Notification Service .............................................................................................................................................. 398
Customer Support.............................................................................................................................................................................. 398
Product Identification System ............................................................................................................................................................ 399

PIC16(L)F1508/9
DS40001609E-page 6 2011-2015 Microchip Technology Inc.
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PIC16(L)F1508/9
DS40001609E-page 8 2011-2015 Microchip Technology Inc.
1.0 DEVICE OVERVIEW
The block diagram of these devices are shown in
Figure 1-1, the available peripherals are shown in
Table 1-1, and the pinout descriptions are shown in
Table 1-2.
TABLE 1-1: DEVICE PERIPHERAL SUMMARY
Peripheral
PIC12(L)F1501 PIC16(L)F1503 PIC16(L)F1507 PIC16(L)F1508 PIC16(L)F1509
Analog-to-Digital Converter (ADC) ● ● ●●●
Complementary Wave Generator (CWG) ● ● ●●●
Digital-to-Analog Converter (DAC) ● ● ●●
Enhanced Universal
Synchronous/Asynchronous Receiver/
Transmitter (EUSART)
●●
Fixed Voltage Reference (FVR) ● ● ●●●
Numerically Controlled Oscillator (NCO) ● ● ●●●
Temperature Indicator ● ● ●●●
Comparators
C1 ● ● ●●
C2 ●●●
Configurable Logic Cell (CLC)
CLC1 ● ● ●●●
CLC2 ● ● ●●●
CLC3 ●●
CLC4 ●●
Master Synchronous Serial Ports
MSSP1 ●●●
PWM Modules
PWM1 ● ● ●●●
PWM2 ● ● ●●●
PWM3 ● ● ●●●
PWM4 ● ● ●●●
Timers
Timer0 ● ● ●●●
Timer1 ● ● ●●●
Timer2 ● ● ●●●

2011-2015 Microchip Technology Inc. DS40001609E-page 9
PIC16(L)F1508/9
FIGURE 1-1: PIC16(L)F1508/9 BLOCK DIAGRAM
OSC2/CLKOUT
OSC1/CLKIN
RAM
CPU
(Note 3)
Timing
Generation
INTRC
Oscillator
MCLR
Program
Flash Memory
FVRDAC
ADC
10-bit
Temp
Indicator
C1C2TMR0TMR1TMR2MSSP1
PWM1 EUSART PWM2PWM3PWM4CLC1CLC2CLC3CLC4NCO1CWG1
PORTA
PORTB
PORTC
Rev. 10-000039A
8/1/2013
Note 1: See applicable chapters for more information on peripherals.
2: See Table 1 -1 for peripherals on specific devices.
3: See Figure 2-1.

PIC16(L)F1508/9
DS40001609E-page 10 2011-2015 Microchip Technology Inc.
TABLE 1-2: PIC16(L)F1508/9 PINOUT DESCRIPTION
Name Function Input
Type Output Type Description
RA0/AN0/C1IN+/DAC1OUT1/
ICSPDAT/ICDDAT
RA0 TTL CMOS General purpose I/O.
AN0 AN — ADC Channel input.
C1IN+ AN — Comparator positive input.
DAC1OUT1 — AN Digital-to-Analog Converter output.
ICSPDAT ST CMOS ICSP™ Data I/O.
ICDDAT ST CMOS In-Circuit Debug data.
RA1/AN1/CLC4IN1/VREF+/
C1IN0-/C2IN0-/ICSPCLK/
ICDCLK
RA1 TTL CMOS General purpose I/O.
AN1 AN — ADC Channel input.
CLC4IN1 ST — Configurable Logic Cell source input.
VREF+ AN — ADC Positive Voltage Reference input.
C1IN0- AN — Comparator negative input.
C2IN0- AN — Comparator negative input.
ICSPCLK ST — ICSP Programming Clock.
ICDCLK ST — In-Circuit Debug Clock.
RA2/AN2/C1OUT/DAC1OUT2/
T0CKI/INT/PWM3/CLC1/
CWG1FLT
RA2 ST CMOS General purpose I/O.
AN2 AN — ADC Channel input.
C1OUT — CMOS Comparator output.
DAC1OUT2 — AN Digital-to-Analog Converter output.
T0CKI ST — Timer0 clock input.
INT ST — External interrupt.
PWM3 — CMOS PWM output.
CLC1 — CMOS Configurable Logic Cell source output.
CWG1FLT ST — Complementary Waveform Generator Fault input.
RA3/CLC1IN0/VPP/T1G(1)/SS(1)/
MCLR
RA3 TTL — General purpose input with IOC and WPU.
CLC1IN0 ST — Configurable Logic Cell source input.
VPP HV — Programming voltage.
T1G ST — Timer1 Gate input.
SS ST — Slave Select input.
MCLR ST — Master Clear with internal pull-up.
RA4/AN3/SOSCO/
CLKOUT/T1G
RA4 TTL CMOS General purpose I/O.
AN3 AN — ADC Channel input.
SOSCO XTAL XTAL Secondary Oscillator Connection.
CLKOUT — CMOS FOSC/4 output.
T1G ST — Timer1 Gate input.
RA5/CLKIN/T1CKI/NCO1CLK/
SOSCI
RA5 TTL CMOS General purpose I/O.
CLKIN CMOS — External clock input (EC mode).
T1CKI ST — Timer1 clock input.
NCO1CLK ST — Numerically Controlled Oscillator Clock source input.
SOSCI XTAL XTAL Secondary Oscillator Connection.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: Alternate pin function selected with the APFCON (Register 11-1) register.

2011-2015 Microchip Technology Inc. DS40001609E-page 11
PIC16(L)F1508/9
RB4/AN10/CLC3IN0/SDA/SDI RB4 TTL CMOS General purpose I/O.
AN10 AN — ADC Channel input.
CLC3IN0 ST — Configurable Logic Cell source input.
SDA I2CODI
2C data input/output.
SDI CMOS — SPI data input.
RB5/AN11/CLC4IN0/RX/DT RB5 TTL CMOS General purpose I/O.
AN11 AN — ADC Channel input.
CLC4IN0 ST — Configurable Logic Cell source input.
RX ST — USART asynchronous input.
DT ST CMOS USART synchronous data.
RB6/SCL/SCK RB6 TTL CMOS General purpose I/O.
SCL I2CODI
2C clock.
SCK ST CMOS SPI clock.
RB7/CLC3/TX/CK RB7 TTL CMOS General purpose I/O.
CLC3 — CMOS Configurable Logic Cell source output.
TX — CMOS USART asynchronous transmit.
CK ST CMOS USART synchronous clock.
RC0/AN4/CLC2/C2IN+ RC0 TTL CMOS General purpose I/O.
AN4 AN — ADC Channel input.
CLC2 — CMOS Configurable Logic Cell source output.
C2IN+ AN — Comparator positive input.
RC1/AN5/C1IN1-/C2IN1-/PWM4/
NCO1
RC1 TTL CMOS General purpose I/O.
AN5 AN — ADC Channel input.
C1IN1- AN — Comparator negative input.
C2IN1- AN — Comparator negative input.
PWM4 — CMOS PWM output.
NCO1 — CMOS Numerically Controlled Oscillator is source output.
RC2/AN6/C1IN2-/C2IN2- RC2 TTL CMOS General purpose I/O.
AN6 AN — ADC Channel input.
C1IN2- AN — Comparator negative input.
C2IN2- AN — Comparator negative input.
RC3/AN7/C1IN3-/C2IN3-/PWM2/
CLC2IN0
RC3 TTL CMOS General purpose I/O.
AN7 AN — ADC Channel input.
C1IN3- AN — Comparator negative input.
C2IN3- AN — Comparator negative input.
PWM2 — CMOS PWM output.
CLC2IN0 ST — Configurable Logic Cell source input.
RC4/C2OUT/CLC2IN1/CLC4/
CWG1B
RC4 TTL CMOS General purpose I/O.
C2OUT — CMOS Comparator output.
CLC2IN1 ST — Configurable Logic Cell source input.
CLC4 — CMOS Configurable Logic Cell source output.
CWG1B — CMOS CWG complementary output.
TABLE 1-2: PIC16(L)F1508/9 PINOUT DESCRIPTION (CONTINUED)
Name Function Input
Type Output Type Description
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: Alternate pin function selected with the APFCON (Register 11-1) register.

PIC16(L)F1508/9
DS40001609E-page 12 2011-2015 Microchip Technology Inc.
RC5/PWM1/CLC1(1)/
CWG1A
RC5 TTL CMOS General purpose I/O.
PWM1 — CMOS PWM output.
CLC1 — CMOS Configurable Logic Cell source output.
CWG1A — CMOS CWG primary output.
RC6/AN8/NCO1(1)/CLC3IN1/
SS
RC6 TTL CMOS General purpose I/O.
AN8 AN — ADC Channel input.
NCO1 — CMOS Numerically Controlled Oscillator source output.
CLC3IN1 ST — Configurable Logic Cell source input.
SS ST — Slave Select input.
RC7/AN9/CLC1IN1/SDO RC7 TTL CMOS General purpose I/O.
AN9 AN — ADC Channel input.
CLC1IN1 ST — Configurable Logic Cell source input.
SDO — CMOS SPI data output.
VDD VDD Power — Positive supply.
VSS VSS Power — Ground reference.
TABLE 1-2: PIC16(L)F1508/9 PINOUT DESCRIPTION (CONTINUED)
Name Function Input
Type Output Type Description
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: Alternate pin function selected with the APFCON (Register 11-1) register.

2011-2015 Microchip Technology Inc. DS40001609E-page 13
PIC16(L)F1508/9
2.0 ENHANCED MID-RANGE CPU
This family of devices contain an enhanced mid-range
8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16 levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect, and
Relative addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
program and data memory.
• Automatic Interrupt Context Saving
• 16-level Stack with Overflow and Underflow
• File Select Registers
• Instruction Set
FIGURE 2-1: CORE BLOCK DIAGRAM
15
15
15
15
8
8
8
12
14
7
5
3
Program Counter
MUX
Addr MUX
16-Level Stack
(15-bit)
Program Memory
Read (PMR)
Instruction Reg
Configuration
FSR0 Reg
FSR1 Reg
BSR Reg
STATUS Reg
RAM
WReg
Power-up
Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Instruction
Decode and
Control
Timing
Generation
Internal
Oscillator
Block
ALU
Flash
Program
Memory
MUX
Data Bus
Program
Bus
Direct Addr
Indirect
Addr
RAM Addr
CLKIN
CLKOUT
VDD VSS
Rev. 10-000055A
7/30/2013
12
12

PIC16(L)F1508/9
DS40001609E-page 14 2011-2015 Microchip Technology Inc.
2.1 Automatic Interrupt Context
Saving
During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 7.5 “Automatic Context Saving”,
for more information.
2.2 16-Level Stack with Overflow and
Underflow
These devices have a hardware stack memory 15 bits
wide and 16 words deep. A Stack Overflow or Under-
flow will set the appropriate bit (STKOVF or STKUNF)
in the PCON register, and if enabled, will cause a soft-
ware Reset. See Section 3.5 “Stack” for more details.
2.3 File Select Registers
There are two 16-bit File Select Registers (FSR).
FSRs can access all file registers and program mem-
ory, which allows one Data Pointer for all memory.
When an FSR points to program memory, there is one
additional instruction cycle in instructions using INDF
to allow the data to be fetched. General purpose mem-
ory can now also be addressed linearly, providing the
ability to access contiguous data larger than 80 bytes.
There are also new instructions to support the FSRs.
See Section 3.6 “Indirect Addressing” for more
details.
2.4 Instruction Set
There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See Section
28.0 “Instruction Set Summary” for more details.

2011-2015 Microchip Technology Inc. DS40001609E-page 15
PIC16(L)F1508/9
3.0 MEMORY ORGANIZATION
These devices contain the following types of memory:
• Program Memory
- Configuration Words
- Device ID
-UserID
- Flash Program Memory
• Data Memory
- Core Registers
- Special Function Registers
- General Purpose RAM
- Common RAM
The following features are associated with access and
control of program memory and data memory:
• PCL and PCLATH
•Stack
• Indirect Addressing
3.1 Program Memory Organization
The enhanced mid-range core has a 15-bit program
counter capable of addressing a 32K x 14 program
memory space. Table 3-1 shows the memory sizes
implemented. Accessing a location above these
boundaries will cause a wrap-around within the
implemented memory space. The Reset vector is at
0000h and the interrupt vector is at 0004h (See
Figure 3-1).
3.2 High-Endurance Flash
This device has a 128 byte section of high-endurance
program Flash memory (PFM) in lieu of data EEPROM.
This area is especially well suited for nonvolatile data
storage that is expected to be updated frequently over
the life of the end product. See Section 10.2 “Flash
Program Memory Overview” for more information on
writing data to PFM. See Section 3.2.1.2 “Indirect
Read with FSR” for more information about using the
FSR registers to read byte data stored in PFM.
TABLE 3-1: DEVICE SIZES AND ADDRESSES
Device Program Memory
Space (Words) Last Program Memory Address High-Endurance Flash Memory Address Range (1)
PIC16LF1508
PIC16F1508 4,096 0FFFh 0F80h-0FFFh
PIC16LF1509
PIC16F1509 8,192 1FFFh 1F80h-1FFFh
Note 1: High-endurance Flash applies to low byte of each address in the range.

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FIGURE 3-1: PROGRAM MEMORY MAP
AND STACK FOR
PIC16(L)F1508
Stack Level 0
Stack Level 15
Stack Level 1
Reset Vector
PC<14:0>
Interrupt Vector
Page 1
Page 0
Rollover to Page 0
Rollover to Page 1
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
7FFFh
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
On-chip
Program
Memory
15
Rev. 10-000040A
7/30/2013
PIC16(L)F1508
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
On-chip
Program
Memory
Stack Level 0
Stack Level 15
Stack Level 1
Reset Vector
PC<14:0>
Interrupt Vector
Page 1
Page 0
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
7FFFh
Rollover to Page 0
Rollover to Page 3
Page 2
Page 3
17FFh
1800h
1FFFh
2000h
15
Rev. 10-000040B
7/30/2013
PIC16(L)F1509

2011-2015 Microchip Technology Inc. DS40001609E-page 17
PIC16(L)F1508/9
3.2.1 READING PROGRAM MEMORY AS
DATA
There are two methods of accessing constants in
program memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSR to point to the program memory.
3.2.1.1 RETLW Instruction
The RETLW instruction can be used to provide access
to tables of constants. The recommended way to create
such a table is shown in Example 3-1.
EXAMPLE 3-1: RETLW INSTRUCTION
The BRW instruction makes this type of table very
simple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRW instruction is not available so the older table read
method must be used.
3.2.1.2 Indirect Read with FSR
The program memory can be accessed as data by set-
ting bit 7 of the FSRxH register and reading the match-
ing INDFx register. The MOVIW instruction will place the
lower eight bits of the addressed word in the W register.
Writes to the program memory cannot be performed via
the INDF registers. Instructions that access the pro-
gram memory via the FSR require one extra instruction
cycle to complete. Example 3-2 demonstrates access-
ing the program memory via an FSR.
The HIGH operator will set bit<7> if a label points to a
location in program memory.
EXAMPLE 3-2: ACCESSING PROGRAM
MEMORY VIA FSR
constants
BRW ;Add Index in W to
;program counter to
;select data
RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3
my_function
;… LOTS OF CODE…
MOVLW DATA_INDEX
call constants
;… THE CONSTANT IS IN W
constants
DW DATA0 ;First constant
DW DATA1 ;Second constant
DW DATA2
DW DATA3
my_function
;… LOTS OF CODE…
MOVLW DATA_INDEX
ADDLW LOW constants
MOVWF FSR1L
MOVLW HIGH constants;MSb sets
automatically
MOVWF FSR1H
BTFSC STATUS, C ;carry from ADDLW?
INCF FSR1h, f ;yes
MOVIW 0[FSR1]
;THE PROGRAM MEMORY IS IN W

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3.3 Data Memory Organization
The data memory is partitioned in 32 memory banks
with 128 bytes in a bank. Each bank consists of
(Figure 3-2):
• 12 core registers
• 20 Special Function Registers (SFR)
• Up to 80 bytes of General Purpose RAM (GPR)
• 16 bytes of common RAM
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See Section 3.6 “Indirect
Addressing” for more information.
Data memory uses a 12-bit address. The upper five bits
of the address define the Bank address and the lower
seven bits select the registers/RAM in that bank.
3.3.1 CORE REGISTERS
The core registers contain the registers that directly
affect the basic operation. The core registers occupy
the first 12 addresses of every data memory bank
(addresses x00h/x08h through x0Bh/x8Bh). These
registers are listed below in Ta bl e 3 -2 . For detailed
information, see Table 3-8 .
TABLE 3-2: CORE REGISTERS
Addresses BANKx
x00h or x80h INDF0
x01h or x81h INDF1
x02h or x82h PCL
x03h or x83h STATUS
x04h or x84h FSR0L
x05h or x85h FSR0H
x06h or x86h FSR1L
x07h or x87h FSR1H
x08h or x88h BSR
x09h or x89h WREG
x0Ah or x8Ah PCLATH
x0Bh or x8Bh INTCON

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PIC16(L)F1508/9
3.3.1.1 STATUS Register
The STATUS register, shown in Register 3-1, contains:
• the arithmetic status of the ALU
• the Reset status
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u= unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section
28.0 “Instruction Set Summary”).
Note 1: The C and DC bits operate as Borrow
and Digit Borrow out bits, respectively, in
subtraction.
REGISTER 3-1: STATUS: STATUS REGISTER
U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u
— — — TO PD ZDC
(1) C(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7-5 Unimplemented: Read as ‘0’
bit 4 TO:Time-Out bit
1= After power-up, CLRWDT instruction or SLEEP instruction
0= A WDT time-out occurred
bit 3 PD:Power-Down bit
1= After power-up or by the CLRWDT instruction
0= By execution of the SLEEP instruction
bit 2 Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1= A carry-out from the 4th low-order bit of the result occurred
0= No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.

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3.3.2 SPECIAL FUNCTION REGISTER
The Special Function Registers are registers used by
the application to control the desired operation of
peripheral functions in the device. The Special Function
Registers occupy the 20 bytes after the core registers of
every data memory bank (addresses x0Ch/x8Ch
through x1Fh/x9Fh). The registers associated with the
operation of the peripherals are described in the appro-
priate peripheral chapter of this data sheet.
3.3.3 GENERAL PURPOSE RAM
There are up to 80 bytes of GPR in each data memory
bank. The Special Function Registers occupy the 20
bytes after the core registers of every data memory
bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).
3.3.3.1 Linear Access to GPR
The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section
3.6.2 “Linear Data Memory” for more information.
3.3.4 COMMON RAM
There are 16 bytes of common RAM accessible from all
banks.
FIGURE 3-2: BANKED MEMORY
PARTITIONING
Memory Region7-bit Bank Offset
00h
0Bh
0Ch
1Fh
20h
6Fh
7Fh
70h
Core Registers
(12 bytes)
Special Function Registers
(20 bytes maximum)
General Purpose RAM
(80 bytes maximum)
Common RAM
(16 bytes)
Rev. 10-000041A
7/30/2013

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PIC16(L)F1508/9
3.3.5 DEVICE MEMORY MAPS
The memory maps for Bank 0 through Bank 31 are shown in the tables in this section.
TABLE 3-3: PIC16(L)F1508 MEMORY MAP, BANK 0-7
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h
Core Registers
(Tabl e 3-2)
080h
Core Registers
(Tabl e 3-2)
100h
Core Registers
(Table 3-2)
180h
Core Registers
(Table 3-2)
200h
Core Registers
(Table 3-2)
280h
Core Registers
(Table 3-2)
300h
Core Registers
(Table 3-2)
380h
Core Registers
(Table 3-2)
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch — 30Ch — 38Ch —
00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh — 30Dh — 38Dh —
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh —28Eh—30Eh—38Eh—
00Fh —08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh—
010h —090h—110h—190h—210h—290h—310h — 390h —
011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h SSP1BUF 291h —311h —391h IOCAP
012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h SSP1ADD 292h —312h —392h IOCAN
013h PIR3 093h PIE3 113h CM2CON0 193h PMDATL 213h SSP1MSK 293h —313h —393h IOCAF
014h —094h— 114h CM2CON1 194h PMDATH 214h SSP1STAT 294h —314h —394h IOCBP
015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h SSP1CON1 295h —315h —395h IOCBN
016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSP1CON2 296h — 316h — 396h IOCBF
017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON 217h SSP1CON3 297h — 317h — 397h —
018h T1CON 098h —118h
DAC1CON0 198h —218h—298h — 318h — 398h —
019h T1GCON 099h OSCCON 119h DAC1CON1 199h RCREG 219h —299h— 319h — 399h —
01Ah TMR2 09Ah OSCSTAT 11Ah —19Ah
TXREG 21Ah —29Ah—31Ah—39Ah—
01Bh PR2 09BhADRESL11Bh —19Bh
SPBRG 21Bh —29Bh—31Bh—39Bh —
01Ch T2CON 09Ch ADRESH 11Ch — 19Ch SPBRGH 21Ch — 29Ch — 31Ch —39Ch —
01Dh — 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh —29Dh —31Dh —39Dh —
01Eh —09Eh ADCON1 11Eh —19Eh TXSTA 21Eh —29Eh —31Eh —39Eh —
01Fh —09Fh ADCON2 11Fh —19Fh
BAUDCON 21Fh —29Fh —31Fh —39Fh —
020h
General
Purpose
Register
80 Bytes
0A0h
General
Purpose
Register
80 Bytes
120h
General
Purpose
Register
80 Bytes
1A0h
Unimplemented
Read as ‘0’
220h
Unimplemented
Read as ‘0’
2A0h
Unimplemented
Read as ‘0’
320h
Unimplemented
Read as ‘0’
3A0h
Unimplemented
Read as ‘0’
0EFh
06Fh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh
070h
Common RAM
0F0h Common RAM
(Accesses
70h – 7Fh)
170h Common RAM
(Accesses
70h – 7Fh)
1F0h Common RAM
(Accesses
70h – 7Fh)
270h Common RAM
(Accesses
70h – 7Fh)
2F0h Common RAM
(Accesses
70h – 7Fh)
370h Common RAM
(Accesses
70h – 7Fh)
3F0h Common RAM
(Accesses
70h – 7Fh)
07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh
Legend: = Unimplemented data memory locations, read as ‘0’.