Motorola MVME410 User manual
MVME410
Dual
Parallel
Port
Module
User's
Manual
MVME410/D2
QUALITY • PEOPLE • PERFORMANCE
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MVME410/D2
AUGUST
1983
MVME410
DUAL
PARALLEL
PORT
MODULE
USER'S
MANUAL
The
information
in
this
document
has
been
carefully
checked
and
is
believed
to
~
entirely
reliable.
However, no
responsibility
is
assumed
for
inaccuracies.
Furthermore,
Motorola
reserves
the
right
to
make
changes
to
any
products
herein
to
improve
reliability,
function,
or
design.
Motorola
does
not
assume any
liability
arising
out
of
the
application
or
use
of
any
product
or
circuit
described
herein;
neither
does
it
convey
any
license
under
its
patent
rights
or
the
rights
of
others.
I/Onodule
is
a
trademark
of
Motorola
Inc.
Secom
Frlition
Copyright
1982
by
Motorola
Inc.
First
Frlition
October 1982
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SAFETY SUMMARY
SAFETY DEPENDS ON YOU
The fol/owinggeneralsafetyprecautionsmustbe observedduring
all
phases
of
operation, service,
and
repair
of
this equipment. Failure to
comply
with theseprecautions
or
with specific warnings elsewhere
In this manual violates safety standards
of
design, manufacture,
and
Intended use
of
the equipment.
Motorola Inc. assumes
no
liability
for
the customer's failure to
comply
with these requirements. The
safetyprecautions /Isled belowrepresent warnings
of
certain dangers
of
which we
are
aware.
You,
as
the
user
of
the product, should follow these warnings
and
all
othersafety precautions necessary
for
the safe operation
of
the equipmentIn
your
operating environment.
GROUND THE INSTRUMENT.
To
minimize shock hazard, the equipment chassis and enclosure must be connected
to
an
electrical
ground. The equipment is supplied with a
three-conductor
ac powercable. The powercable musteither
be plugged
into
an approved three-contact electrical
outlet
or
used with a three-contact
to
two-contact
adapter, with the
grounding
wire (green) firmly connected
to
an electrical
ground
(safety ground) at the
power outlet. The
power
jack
and mating plug
of
the
power
cable meet International Electrotechnical
Commission (IEC) safety standards.
DO
NOT
OPERATE
IN
AN EXPLOSIVE ATMOSPHERE.
Do not operate the
equipment
in the presence
of
flammable gases
or
fumes. Operation
of
any electrical
equipment in such an environment constitutes a definite safety hazard.
KEEP AWAY FROM LIVE CIRCUITS.
Operating personnel must
not
remove equipment covers. Component replacement and internal adjust-
ments must be made by qualified maintenance personnel. Do
not
replace components with power
cable connected.
Under
certain conditions, dangerous voltages may exist even
with
the power cable
removed.
To
avoid injuries, always disconnect power and
di~charge
circuits before
touching
them.
DO
NOT
SERVICE OR
ADJUST
ALONE.
Do
not
attempt internal service
or
adjustment unless
another
person, capable
of
rendering first aid and
resuscitation, is present.
USE CAUTION WHEN EXPOSING OR HANDLING THE CRT.
Breakage
of
the Cathode-RayTube (CRT) causes a high-velocity scattering
of
glass fragments (implo-
sion).
To
prevent CRT implosion, avoid rough handling
or
jarring
of
the equipment. Handling
of
the
CRT should be done
only
by
qualified maintenance personnel using approved safety mask and gloves.
DO
NOT
SUBSTITUTE PARTS OR MODIFY EQUIPMENT.
Because
of
the danger
of
introducing
additional hazards,
do
not
install
substitute
parts
or
perform any
unauthorized
modification
of
the equipment.
Contact
Motorola
Microsystems Warranty and Repair
for
service and repair
to
ensure
~hat
safety features are maintained.
DANGEROUS PROCEDURE WARNINGS.
Warnings,
such
as
the
example
below,
precede
potentially
dangerous
procedures
throughout
this
manual. Instructions contained in the warnings must be followed. You should also employ all
other
safety precautions
which
you
deem necessary
for
the operation
of
the
equipment
in
your
operating
environment.
WARNING
Dangerousvoltages, capable
of
causing death,are presentIn this equipment. Use extreme
caution when handling, testing, and adjusting.
14260 PRINTED IN USA
(61811
MPS
300
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PREFACE
Unless
otherwise
specified,
all
address
references
are
in
hexadecimal
throughout
this
manual.
An
asterisk
(*)
following
the
signal
name
for
signals
which
are
level
significant
denotes
that
the
signal
is
true
or
valid
When
the
signal
is
low.
An
asterisk
(*)
following
the
signal
name
for
signals
which
are
edge
significant
denotes
that
the
actions
initiated
by
that
signal
occur
on a
high
to
low
transition.
Throughout
this
manual,
the
X
in
the
signal
mI'lemonic
of
peripheral
signals
(i.e.,
PXCBl,
PXCB2)
denotes
the
following:
X = 1
denotes
Jl
front
panel
connector
X =2
denotes
Jl6
front
panel
connector
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CHAPTER
1
1.1
1.2
1.3
1.4
1.5
CHAPTER
2
2.1
2.2
2.3
2.3.l
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
2.4
2.4.1
2.4.2
CHAPTER
3
3.1
3.2
3.3
CHAPTER
4
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.4
4.5
4.6
4.7
4.8
TABLE
OF
CONTENTS
GENERAL
INFORMATION
INTRODUCTION
•••••••••••••••••••••••••••••••••••••••••••••
FEATURES
•••••••••••••••••••••••••••••••••••••••••••••••••
SPECIFICATIONS
••••••••••••••••••••••••••
·•
••••••••••••••••
GENERAL
DESCRIPTION
••••••••••••••••••••••••••••••••••••••
REI.ATED
DOCUMENTATION
••••••••••••••••••••••••••••••••••••
HARDWARE
PREPARATION
AND
INSTALLATION
INSTRUCTIONS
IN'l'RODUCTI
00
•••••••••••••••••••••••••••••••••••••••••••••
UNPACKIN3
INSTRUCTIONS•••••••••••••••••••••••••••••••••••
HARDWARE
PREPARATION'
•••••••••••••••••••••••••••••••••••••
LED
Monitor Header (J2)
Port
1
Direction
Headers
Port
Port
Port
1
Direction
Headers
2
Direction
Headers
2
Direction
Headers
(J3,
J4)
••••••••••••••••••••••
(JS,
J6)
••••••••••••••••••••••
(J8'
J9)
••••••••••••••••••••••
(JlO,
Jll)
••••••••••••••••••••
Interrupt
Select
Headers
(Jl2,
Jl3)
Base Address
Selection
Header
(Jl4)
LED
Control
Header
(Jl5)
....................
INSTALI.ATION
INSTRUCTIONS
••••••••••••••••••••••••••••••••
Installation
in
VME
Chassis
••••••••••••••••••••••••••••
Installation
in
5-Slot
I/Qnodule
card
Cage
•••••••••••••
OPERATIN3
INSTRUCTIONS
IN'l'RODUCTI
ON
•••••••••••••••••••••••••••••••••••••••••••••
INDICATOR
................................................
OPERATI~
PROCEDURE
••••••••••••••••••••••••••••••••••••••
FUNCTIONAL
DESCRIPTION
INTRODUCTION
•••••••••••••••••••••••••••••••••••••••••••••
GENERAL
DESCRIPTION
••••••••••••••••••••••••••••••••••••••
I/O
CHANNEL
INTERFACE
••••••••••••••••••••••••••••••••••••
Map
Decoding Logic .....................................
Access
Control
Logic ...................................
Interrupt
Logic
ti
•••••••••••••••••••••••••••••••••••••••
PARALLEL
PORT
1 ..........................................
PARALLEL
PORT
2
••••••••••••••••••••••••••••••••••••••••••
LIMITATIONS
••••••••••••••••••••••••••••••••••••••••••••••
MODULE
I/O
TIMIN:;
........................................
MODULE
PERIPHERAL
TIMI~
•••••••••••••••••••••••••••••••••
i
1-1
1-1
1-1
1-5
1-5
2-1
2-1
2-1
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-11
2-12
2-12
2-12
3-1
3-1
3-1
4-1
4-1
4-1
4-1
4-1
4-2
4-5
4-5
4-6
4-6
4-7
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CHAPrER
S
S.l
S.2
s.2.1
S.2.2
S.3
S.4
FIGURE
1-1.
2-1.
2-2.
2-3.
2-4.
2-S.
2-6.
2-7.
2-8.
2-9.
2-10.
3-1.
4-1.
4-2.
4-3.
4-4.
5-1.
5-2.
TABLE
1-1.
1-2.
2-1.
2-2.
2-3.
2-4.
2-S.
2-6.
2-7.
2-8.
4-1.
4-2.
4-3.
5-1.
S-2.
5-3.
TABLE
OF
CONTENTS
(cont'd)
SUPPORT
INFORMATION
INTRODUCTI,ON
•••••••••••••••••••••••••••••••••••••••••••••
CONNECTOR
SIGNAL
DESCRIPTIONS
••••••••••••••••••••••••••••
I/O
Channel Connector
••••••••••••••••••••••••••••••••••
Peripheral
Connectors
••••••••••••••••••••••••••••••••••
PARTS
LIST
•••••••••••••••••••••••••••••••••••••••••••••••
DIAGR.AMS
••••••••••••••••••••••••••••••••••••••
•
••••
• • • • • •
LIST
OF
ILLUSTRATIONS
Dual
Parallel
Port
Module
••••••••••••••••••••••••••••••••
OPP
Module Header
Location
Diagram
•••••••••••••••••••••••
LED
Monitor Header (J2)
••••••••••••••••••••••••••••••••••
Port
1
Direction
Headers
(J3,
J4)
••••••••••••••••••••••••
Port
1
Direction
Headers (JS,
J6)
••••••••••••••••••••••••
Port
2
Direction
Headers
(J8,
J9)
••••••••••••••••••••••••
Port
2
Direction
Headers (JlO,
Jll)
••••••••••••••••••••••
Interrupt
Select
Headers
(Jl2,
Jl3)
••••••••••••••••••••••
Base Address
Select
Header
(Jl4)
•••••••••••••••••••••••••
LED
Control
Header
(JlS)
•••••••••••••••••••••••••••••••••
Typical
OPP
Interface
Cabling
Diagram
••••••••••••••••••••
Typical
Printer
Driver
Routine
(3
Sheets)
••••••••••••••••
OPP
Module Block Diagram
···························~·····
I/O Channel
Memory
Map
•••••••••••••••••••••••••••••••••••
I/O
Channel
Side
Timing
Signal
Diagram
•••••••••••••••••••
Peripheral
Side
Timing
Signal
Diagram (3
sheets)
•••••••••
OPP
Module
Parts
Location
Diagram
••••••••••••••••••••••••
DPP
Module Schematic Diagram (2
Sheets)
••••••••••••••••••
LIST
OF
TABLES
Dual
Parallel
Port
Module
Specifications
•••••••••••••••••
Peripheral
Signal
Specifications
•••••••••••••••••••••••••
OPP
Module Headers
•••••••••••••••••••••••••••••••••••••••
Headers
J3
am
J4
Configurations
•••••••••••••••••••••••••
Headers JS and
J6
Configurations
•••••••••••••••••••••••••
Headers
J8
am
J9
Configurations
•••••••••••••••••••••••••
Headers JlO and
Jll
Configurations
•••••••••••••••••••••••
Headers
Jl2
am
Jl3
Configurations
•••••••••••••••••••••••
Header
Jl4
Configurations
••••••••••••••••••••••••••••••••
Header
JlS
Configurations
••••••••••••••••••••••••••••••••
OPP
Module
Register
Addresses
••••••••••••••••••••••••••••
I/O Channel Timing
Signal
Characteristics
••••••••••••••••
Peripheral
Timing
Signal
Characteristics
•••••••••••••••••
I/O Connector
Pl
Pin
Assignments
•••••••••••••••••••••••••
Peripheral
Connectors
Jl
and
Jl6
Pin
Assignments
•••••••••
OPP
Module
Parts
List
••••••••••••••••••••••••••••••••••••
ii
S-1
S-1
S-1
S-1
S-1
S-1
1-2
2-2
2-3
2-4
2-S
2-6
2-7
2-8
2-10
2-11
2-13
3-2
4-2
4-3
4-7
4-8
S-7
S-9
1-3
1-4
2-3
2-4
2-S
2-6
2-7
2-9
2-10
2-11
4-4
4-6
4-7
S-2
S-4
s-s
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CHAPTER
1
GENERAL
INFORMATION
1.1
INTRODUCTION
'Ibis
manual provides
general
infonnation,
hardware
preparation
and
installation
instructions,
operating
instructions,
functional
description,
and
support
information
for
the
MVME410
:rual
Parallel
I-Ort
M:>dule
{referred
to
as
DPP
throi..ghout
this
manual) • 'Ihe
OPP
is
shown
in
Figure
1-1.
1.2
FEATURES
Features
of
the
OPP
are
listed
below•
• M:>torola I/O Channel compatible•
• Single-wide
VME
board fonn
factor
•
• Centronics
printer
standard
interface
compatible•
•
Two
MC6821
Peripheral
Interface
Adapter
{PIA)
buffered
ports
•
•
Each
port
capable
of
driving
two
of
four I/O Channel
interrupt
lines.
•
16
peripheral
data
lines
per
port,
each
capable
of
sinking
24
mA
•
• Four
peripheral
control
lines
per
port
--
t\.V'O
input
only
and
two
individually
configurable
as
input
or
output
•
•
Each
9roup
of
eight
peripheral
data
lines
is
hardware
strappa~le
as
input
only,
output
only,
or
bidirectional
under
software
control
•
• Will
interface
two
asynchronous
parallel
data
hard copy
printers
to
the
I/O Channel •
• Operates with I/O Channel master
to
drive
hard copy
printers
•
•
Self-test
FAIL
LED
indicator.
1.3
SPECIFICATIONS
General
specifications
for
the
OPP
are
given
in
Table
1-1.
Table 1-2
gives
peripheral
signal
specifications.
1-1
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FIGURE
1-1.
Dual
Parallel
Port
Module
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TABLE
1-1.
n.tal
Parallel
Port
Module
Specifications
CHARACTERISTIC
SPECIFICATIONS
Power
requirements
Temperature
Operating
Storage
Relative
humidity
Physical
characteristics
PC
board
only
Height
Depth
'Ihickness
PC
board
with
connectors
and board
stiffener
Height
Depth
'Ihickness
1-3
+5
Vdc
@762
mA
typical
991
mA
maximum
00
to
100 C
-40°
to
85° c
0%
to
90%
(non-condensing)
6.30
in.
(160
nun)
3.94
in.
(100
nun)
0.59
in.
(15
nun)
7.40
in.
(188
nun)
5.12
in.
(130
mm)
0.83
in.
(21
mm)
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SIGNALS
(1)
PlPAO-PlPA7,
PlPBO-PlPB7,
P2PAO-P2PA7,
P2PBO-P2PB7,
PlCAl-PlCBl,
P2CA1-P2CB1
NOTE:
TABLE
1-2.
Peripheral
Signal
Specifications
CHARACTERISTIC
High
level
input
voltage
I.ow
level
input
voltage
High
level
output
voltage
with
!OH=
-15
mA
I.ow
level
output
voltage
with
IOL
=
24
mA
Off
state
output
current
with
high
level
output
voltage
applied
Off
state
output
current
with
low
level
output
voltage
applied
High
level
input
current
with
VIH
=
2.7
volts
de
I.ow
level
input
current
with
VIL
=
0.4
volts
de
SPECIFICATIONS
2
volts
de
minimum
a.a
volts
de
maximun
2
volts
de
minimum
o.s
volts
de
maximum
10
uA
maximum
-200
uA
maximum
20
uA
maximum
-0.2
mA
maximum
(1) Refer
to
schematic diagram.
Peripheral
signals
PlCA2,PlCB2,
P2CA2,
and
P2CB2
have
the
same
specifications
except
that
the
off
state
characteristics
do
not
apply.
'/m.y
of
the
signals
that
are
configured
as
inputs
(except
PXCAl
and
PXCBl)
should
not
be allowed
to
float;
therefore,
any
input
signals
not
driven
by
the
peripheral
should be
held
in
either
a high
state
or
a low
state.
1-4
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1.4
GENERAL
DESCRIPTION
'Ihe
DPP
is
an I/O Channel-compatible
dual
printer
interface
module.
'Ihis
module
confonns
to
the
single-wide
VME
board fonn
factor
and
connects
to
the
I/O
Channel with a 64-pin
DIN
standard
connector.
'Ihe
DPP
is
used
to
expand
the
resources
of
an I/O Channel master
to
include
two
printer
interfaces,
one
printer
interface
and a
general-purpose
16-bit
parallel
data
I/O
port,
or
two
general-purpose
16-bit
parallel
data
I/O
ports.
'1\-.o
PIA's
(with
buffers
on
their
peripheral
sides)
are
employed
to
implement
the
two
parallel
data
ports.
In
addition
to
having an I/O Channel
interface,
each
of
the
PIA's
is
capable
of
driving
up
to
two
of
the
I/O Channel
interrupt
lines.
A
front
panel
FAIL
LED
indicator
is
provided
to
indicate
a module
malfunction.
The
user
must provide a connector-compatible I/O Channel backplane
or
ribbon
cable
for
DPP
connection
to
the
I/O Channel
master.
Refer
to
the
I/O Channel
Specification
Manual,
~torola
publication
number
M68RIOCS,
for
interfacing
and
backplane
information.
'Ihe
user
must
also
provide compatible
cables
for
DPP
connection
(via
front
panel connectors)
to
peripheral
devices.
1.5
RELATED
DOCUMENTATION
'Ihe
Input/Oltput
Channel
Specification
Manual,
M68RIOCS,
is
applicable
to
the
DPP.
1-5/1-6
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CHAPTER
2
HARrWARE
PREPARATION
AND
INSTALIATION
INS'IRUCTIONS
2.1
INTRODUCTION
'Ibis
chapter
provides
tmpacking,
hardware
preparation,
and
installation
instructions
for
the
I:Ual
Parallel
Port
Module.
2.2
UNPACKING
INS'IRUCTIONS
NOTE
If
shipping
carton
is
damaged upon
receipt,
request
carrier's
agent
be
present
during
tmpacking and
.inspection
of
equipnent.
lbpack
equipnent
from
shipping
carton.
Refer
to
packing
list
and
verify
that
all
items
are
present.
Save packing
material
for
storing
or
reshipping
the
equipnent.
2.3
HARil4/ARE
PREPARATION
'Ibis
section
describes
the
hardware
preparation
of
the
DPP
module
prior
to
system
installation.
'lhe
DPP
has
been
factory
tested
for
system
operation
and
is
shipped
with
factory-installed
junpers.
'lhese
factory-installed
jlltlper
connections
should
be
verified
to
ensure
that
the
components
are
properly
configured
for
system
operation.
'!he
DPP
is
configured
to
interface
the
I/O
Cllannel
master
with
Centronics
printer-compatible
equipnent.
'!here
are
13
headers
on
the
DPP,
as
shown
in
Figure
2-1.
'Ibey
are
J2-J6
and
J8-Jl5.
Table
2-1
lists
each
header,
its
function
and
factory-installed
jlltlper
configuration.
For
signal
names
such
as
PlCA2,
etc.,
refer
to
the
schematic
diagram.
2-1
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JS J8
CJ
CJ
I
I
J4
J9
..
lJi l Jt2
Jt3
JIO
D~r
0
J11D
l
J••D
Jt5
c
__
__.
FIGURE
2-1.
DPP
Module
Header I.Dcation Diagram
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TABLE
2-1.
OPP
ftt>dule
Headers
HFADER
FACTORY
NUMBER
FUNCTION
CONFIGURATION
J2
LED
monitor 2-3
J3
FOrt 1
(PlCA2,
PlPAO-PlPA7)
direction
1-2
J4
FOrt 1 (PlCA2,
PlPAO-PlPA7)
direction
1-2
JS FOrt 1 (PlCB2,
PlPBO-PlPB7)
direction
1-2
J6
FOrt 1 (PlCB2,
PlPBO-PlPB7)
direction
No jumper
JS FOrt 2
(P2CA2,
P2PAO-P2PA7)
direction
1-2
J9
FOrt 2
(P2CA2,
P2PAO-P2PA7)
direction
1-2
JlO FOrt 2
(P2CB2,
P2PBO-P2PB7)
direction
1-2
Jll
FOrt 2
(P2CB2,
P2PBO-P2PB7)
direction
No jumper
Jl2
Interrupt
select
2-4,
7-9
Jl3
Interrupt
select
3-5,
a-10
Jl4
Base
address
select
No jumper
JlS
LED
control
2-3
2.3.1
LED
.r.t:>nitor
Header (J2)
Header
J2
is
junpered between
pins
2 and
3,
as
shown
in
Figure 2-2, and should
not
be
altered.
J2
1 0
2 I
3
FIGURE
2-2.
LED
r-t>ni
tor
Header (J2)
2-3
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2.3.2
Port
1
Direction
Headers
(J3,
J4)
Headers
J3
and J4
together
control
the
direction
of
signal
lines
PlCA2
and
PlPAO-PlPA7. 'Ihe
factory
configuration
of
each header
is
shown
in
Figure
2-3.
Table 2-2
lists
the
jumper
configurations
that
determine whether
the
lines
are
inputs
or
outputs.
J3
1 2
J4
0---0
o o I
1 2 3 4
FIGURE
2-3.
Port
1
Direction
Headers
(J3,
J4)
TABLE
2-2.
Headers
J3
and J4
Configurations
HEADER
JUMPER
PINS
CONNECTED
J3
none
J4
1-2
J3
none
J4 2-3
J3 none
J4 3-4
J3
none
J4
1-2,
3-4
J3 none
J4 none
RF.MARKS
PlCA2
is
not
used;
PlPAO-PlPA7
are
outputs.
PlCA2
is
not
used;
PlPAO-PlPA7
are
inputs
when
U8-39
(CA2)
is
high,
and
outputs
when
U8-39
(CA2)
is
low.
PlCA2
is
an
input;
PlPAO-PlPA7
are
inputs.
PlCA2
is
an
input;
PlPAO-PlPA7
are
outputs.
PlCA2
is
not
used;
PlPAO-PlPA7
are
inputs.
-------------------·----------------------------------
J3
1-2
PlCA2
is
an
output;
PlPAO-PlPA7
are
inputs.
J4 none
J3
1-2
(1)
PlCA2
is
an
output;
PlPAO-PlPA7
are
outputs.
J4
1-2
(1)
NOTE:
(1)
Factory-installed
jumper placement.
2-4
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2.3.3
Port
1
Direction
Headers (JS, J6)
Headers JS and
J6
together
control
the
direction
of
signal
lines
PlCB2
and
PlPBO-PlPB7. '!he
factory
configuration
of
each header
is
shown
in
Figure
2-4.
Table 2-3
lists
the
jumper
configurations
that
determine whether
the
lines
are
inputs
or
outputs.
JS J6
0--0
I0 0 0 0 I
1 2 1 2 3 4
FIGURE
2-4.
Port
1
Direction
Headers (JS, J6)
TABLE
2-3.
Headers JS and
J6
Configurations
HEADER
JUMPER
PINS
CONNECTED
JS none
J6
1-2
JS none
J6
2-3
JS none
J6 3-4
---
JS none
J6
1-2,
3-4
JS none
J6 none
--------
JS 1-2
(1)
J6 none
(1)
JS 1-2
J6 1-2
REMARKS
PlCB2
is
not
used;
PlPBO-PlPB7
are
outputs.
·----------
PlCB2
is
not
used;
PlPBO-PlPB7
are
inputs
when
US-19
(CB2)
is
high,
and
outputs
when
US-19
(CB2)
is
low.
PlCB2
is
an
input;
PlPBO-PlPB7
are
inputs.
·--------
PlCB2
is
an
input;
PlPBO-PlPB7
are
outputs.
PlCB2
is
not
used;
PlPBO-PlPB7
are
inputs.
PlCB2
is
an
output;
PlPBO-PlPB7
are
inputs.
PlCB2
is
an ouput;
PlPBO-PlPB7
are
outputs.
NOTE:
(1)
Factory-installed
jumper placement.
2-S
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2.3.4
Port
2
Direction
Headers
(JS,
J9)
Headers JS and
J9
together
control
the
direction
of
signal
lines
P2CA2
and
P2PAO-P2PA7.
'!he
factory
configuration
of
each
header
is
shown
in
Figure
2-5.
Table 2-4
lists
the
jwnper
configurations
that
determine
whether
the
lines
are
inputs
or
outputs.
JS
1 2
J9
o---<>
o o I
1 2 3 4
FIGURE
2-5.
Port
2
Direction
Headers
(JS,
J9)
TABLE
2-4.
Headers
J8
and
J9
Configurations
HEADER
JUMPER
PINS
CONNECTED
JS none
J9
1-2
JS none
J9
2-3
JS none
J9
3-4
~~~~--------~-
JS none
J9
1-2,
3-4
JS none
J9
none
RF.MARKS
P2CA2
is
not
used;
P2PAO-P2PA7
are
outputs.
P2CA2
is
not
used;
P2PAO-P2PA7
are
inputs
when
Ul0-39
(CA2)
is
high,
and
outputs
when
Ul0-39
(CA2)
is
low.
P2CA2
is
an
input;
P2PAO-P2PA7
are
inputs.
---------------------------------
P2CA2
is
an
input;
P2PAO-P2PA7
are
outputs.
~------·---------~~-·---
P2CA2
is
not
used;
P2PAO-P2PA7
are
inputs.
-------
·------·----·---------·
JS
1-2
P2CA2
is
an
output;
P2PAO-P2PA7
are
inputs.
J9
none
JS
1-2
(1)
P2CA2
is
an
output;
P2PAO-P2PA7
are
outputs.
J9
1-2
(1)
NOTE:
(1)
Factory-installed
jumper
placement.
2-6
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