NEC V850/SA1 mPD703015 User manual

Preliminary User’s Manual
µ
µµ
µ
PD703015
µ
µµ
µ
PD703015Y
µ
µµ
µ
PD70F3017
µ
µµ
µ
PD70F3017Y
V850/SA1TM
32-/16-Bit Single-Chip Microcontrollers
Hardware
1997©
Printed in Japan
Document No. U12768EJ2V0UM00 (2nd edition)
Date Published June 1998 N CP(K)

2
[MEMO]

3
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static
electricityasmuchaspossible,andquicklydissipateitonce,whenithasoccurred. Environmental
control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid
using insulators that easily build static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work bench and floor should be grounded. The operator should be
grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar
precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
totheinputpins,itispossiblethataninternalinputlevelmaybegeneratedduetonoise,etc.,hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input
levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each
unused pin should be connected to VDD or GND with a resistor, if it is considered to have a
possibility of being an output pin. All handling related to the unused pins must be judged device
by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until
the reset signal is received. Reset operation must be executed immediately after power-on for
devices having reset function.
V850 Family, V850/SA1 is a trademark of NEC Corporation.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or
other countries.
UNIX is a registered trademark licensed by X/Open Company Limited in the United States and other
countries.

4
Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined
by Philips.
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
Licence not needed : µ PD70F3017,70F3017Y
The customer must judge the need for licence : µ PD703015,703015Y
The information in this document is subject to change without notice.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M7 96.5

5
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: [phone]
800-366-9782
Fax: [phone]
800-729-9288
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: [phone]
Fax: [phone]
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: [phone]
Fax: [phone]
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: [phone]
Fax: [phone]
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: [phone]
Fax: [phone]
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: [phone]
Fax: [phone]
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
Tel: [phone]
Fax: [phone]
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: [phone]
Fax: [phone]
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: [phone]
Fax: [phone]
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: [phone]
Fax: [phone]
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: [phone]
Fax: [phone]
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: [phone]
Fax: [phone]
NEC do Brasil S.A.
Cumbica-Guarulhos-SP, Brasil
Tel: [phone]
Fax: [phone]
J98. 2

6
Major Revisions in This Edition
p.23 121-pin fine pitch BGA has been added to 1.4 Ordering Information
p.24 121-pin fine pitch BGA has been added to 1.5 Pin Configuration (Top View).
p.57 The explanation of EP bit has been modified in 3.2.2 (2) Program status word (PSW).
p.71 The description has been modified in 3.4.6 (2) memory address output mode register
(MAM).
p.75 3.4.8 Peripheral I/O registers has been modified. Note has been added to this section.
p.80 Caution has been added to 3.4.9 Specific registers.
p.90 Note has been added to 4.7.1 Outline of function.
p.102 Note has been added to Table 5-1 Interrupt Source List.
p.148, 149 Caution has been added to 7.1.3 (2) Capture/compare register n0 (CR00, CR10) and
(3) Capture/compare register n1 (CR01, CR11).
p.152 Caution has been modified in Figure 7-2 Format of 16-Bit Timer Mode Control Register
0, 1 (TMC0, TMC1).
p.153 Caution has been added to Figure 7-3 Format of Capture/Compare Control Register 0,
1 (CRC0, CRC1).
p.155 Note has been added to Figure 7-4 Format of 16-Bit Timer Output Control Register 0, 1
(TOC0, TOC1)
p.156
p.157
p.160
Caution has been added to the following figures:
Figure 7-5 Format of Prescaler Mode Register 0 (PRM0)
Figure 7-6 Format of Prescaler Mode Register 1 (PRM1)
Figure 7-10 Control register Settings in PPG Output Operation
p.162 Figure 7-13 has been modified.
p.164 TIn0 has been modified in Figure 7-15 CRn1 Capture Operation with Rising Edge
Specified.
p.164
p.166
p.167
The following figures have been modified.
Figure 7-16 Timing of Pulse Width Measurement with Free Running Counter (with
both edges specified)
Figure 7-18 Timing of Pulse Width Measurement with Free Running Counter and Two
Capture Registers (with rising edge specified)
Figure 7-20 Timing of Pulse Width Measurement by Restarting (with rising edge
specified)
p.198 The description has been changed in 8.4.1 Operation as watch timer.
p.222 Caution has been added to 10.3.2 (1) IIC control register (IICC0).
p.223 Figure 10-9 Format of IIC Control Register (IICC0) has been modified and Remark has
been added to this figure.
p.266 The explanation has been modified in 10.3.12 Communication reservation.
p.269 Figure 10-23 Communication Reservation Flow Chart has been modified.
p.303 Caution has been added to 11.2 (2) A/D conversion result register (ADCR).
p.308 Caution has been added to 11.4.1 Basic operation.
p.314 11.5 (9) Reading A/D conversion result register (ADCR) has been added.
p.359, 362, 366 Erase/write voltage has been changed to VPP = 7.8 V
The mark shows major revised points.

7
INTRODUCTION
Readers
This manual is intended for users who wish to understand the functions of the V850/SA1 ( µ PD703015,
703015Y, 70F3017, 70F3017Y) and design application systems using these products.
Purpose This manual is intended to help users understand the hardware functions described following the
organization below.
Organization The V850/SA1 user’s manual is divided into two parts: hardware (this manual) and architecture
(V850 FamilyUser’s Manual Architecture).
Hardware Architecture
•Pin function
•CPU function
•Internal peripheral function
•Flash memory programming mode
•Data type
•Register set
•Instruction format and instruction set
•Interrupt and exception
•Pipeline operation
How to Read This Manual The manual assumes that the reader has general knowledge of electricity, logical
circuits and microcontrollers.
To find the details of a register whose name is known:
→Refer to APPENDIX A REGISTER INDEX.
To find the details of a function, etc. whose name is known:
→Refer to APPENDIX C INDEX.
To understand the details of instruction functions:
→Refer to V850 Family User’s Manual Architecture
To understand the overall functions of the V850/SA1:
→Read this manual according to the Table of Contents.
Legend Data significance: Higher digits on the left and lower digits on the right
Active low : xxx (overscore over pin or signal name)
Memory map address :Top: highest, bottom: lowest
Note : Footnote for item marked with Note in the text
Caution : Information requiring particular information
Remark : Supplementary information
Number representation : Binary … xxxxB or xxxx
Decimal number … xxxx
Hexadecimal … xxxxH
Prefixes indicating power of 2 (address space, memory capacity):
K (kilo) : 210=1024
M (mega) : 220=10242
G (giga) : 230=10243

8
Related documents The related documents indicted in this publication may included preliminary versions.
However, preliminary versions are not marked as such.
Related documents for V850/SA1
Document Name Document No.
V850 Family Architecture User’s Manual U10243E
V850 Family Instruction Table U10229E
µ
PD703015 Data Sheet To be prepared
µ
PD703015Y Data Sheet To be prepared
µ
PD703017 Data Sheet To be prepared
µ
PD70F3017Y Data Sheet To be prepared
V850/SA1 Hardware User’s Manual This manual
Related documents for development tool (user’s manual)
Document Name Document No.
IE-703002-MC (In-circuit emulator) U11595E
IE-703017-MC-EM1 (In-circuit emulator option board) U12898E
CA850 (C compiler package) Operation (UNIXbased) U11013E
Operation (Windowsbased) U11068E
Assembly Language U10543E
C Language U11010E
Project Manager U11991E
ID850 (C source debugger) Operation (UNIX based) U12209E
Operation (Windows based) U11196E
Installation (UNIX based) U12210E
RX850 (Real Time OS) Fundamental U11037E
Technical U11117E
Nucleus Installation U11038E
Debugger (Windows based) U11158E
AZ850 (System Performance Analyzer) Operation U11181E

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CONTENTS
CHAPTER 1 INTRODUCTION............................................................................................................. 21
1.1 General.................................................................................................................................................. 21
1.2 Features................................................................................................................................................ 21
1.3 Application Fields ................................................................................................................................ 23
1.4 Ordering Information ........................................................................................................................... 23
1.5 Pin Configuration (Top View).............................................................................................................. 24
1.6 Function Blocks ................................................................................................................................... 27
1.6.1 Internal Block Diagram................................................................................................................ 27
1.6.2 On-chip units............................................................................................................................... 28
CHAPTER 2 PIN FUNCTIONS............................................................................................................ 31
2.1 List of Pin Functions............................................................................................................................ 31
2.2 Pin States.............................................................................................................................................. 37
2.3 Description of Pin Functions .............................................................................................................. 38
2.4 Pins’ I/O Circuit Types and Handling When Not Used...................................................................... 49
2.5 Pins’ I/O Circuits .................................................................................................................................. 51
CHAPTER 3 CPU FUNCTIONS........................................................................................................... 53
3.1 Features................................................................................................................................................ 53
3.2 CPU Register Set.................................................................................................................................. 54
3.2.1 Program register set.................................................................................................................... 55
3.2.2 System register set ..................................................................................................................... 56
3.3 Operation Modes.................................................................................................................................. 58
3.4 Address Space ..................................................................................................................................... 59
3.4.1 CPU address space.................................................................................................................... 59
3.4.2 Image (virtual address space)..................................................................................................... 60
3.4.3 Wrap-around of CPU address space.......................................................................................... 61
3.4.4 Memory map ............................................................................................................................... 62
3.4.5 Area............................................................................................................................................. 63
3.4.6 External expansion mode............................................................................................................ 69
3.4.7 Recommended use of address space......................................................................................... 72
3.4.8 Peripheral I/O registers............................................................................................................... 75
3.4.9 Specific registers........................................................................................................................ 80
CHAPTER 4 BUS CONTROL FUNCTION ......................................................................................... 83
4.1 Features................................................................................................................................................ 83
4.2 Bus Control Pins and Control Register.............................................................................................. 83
4.2.1 Bus control pins........................................................................................................................... 83
4.2.2 Control register............................................................................................................................ 84
4.3 Bus Access........................................................................................................................................... 84
4.3.1 Number of access clocks............................................................................................................ 84

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4.3.2 Bus width..................................................................................................................................... 85
4.4 Memory Block Function....................................................................................................................... 86
4.5 Wait Function........................................................................................................................................ 87
4.5.1 Programmable wait function........................................................................................................ 87
4.5.2 External wait function.................................................................................................................. 88
4.5.3 Relations between programmable wait and external wait........................................................... 88
4.6 Idle State Insertion Function............................................................................................................... 89
4.7 Bus Hold Function................................................................................................................................ 90
4.7.1 Outline of function ....................................................................................................................... 90
4.7.2 Bus hold procedure..................................................................................................................... 91
4.7.3 Operation in power save mode ................................................................................................... 91
4.8 Bus Timing............................................................................................................................................ 92
4.9 Bus Priority........................................................................................................................................... 99
4.10 Memory Boundary Operation Condition ............................................................................................ 99
4.10.1 Program space.......................................................................................................................... 99
4.10.2 Data space................................................................................................................................ 99
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION................................................. 101
5.1 Features ................................................................................................................................................ 101
5.2 Non-Maskable Interrupt ....................................................................................................................... 104
5.2.1 Accepting operation..................................................................................................................... 105
5.2.2 Restore........................................................................................................................................ 107
5.2.3 NP flag......................................................................................................................................... 108
5.2.4 Noise elimination circuit of NMI pin............................................................................................. 108
5.2.5 Edge detection function of NMI pin ............................................................................................. 109
5.3 Maskable Interrupts.............................................................................................................................. 110
5.3.1 Operation..................................................................................................................................... 110
5.3.2 Restore........................................................................................................................................ 112
5.3.3 Priorities of maskable interrupts.................................................................................................. 113
5.3.4 Interrupt control register (xxICn).................................................................................................. 117
5.3.5 In-service priority register (ISPR)................................................................................................ 119
5.3.6 Maskable interrupt status flag ..................................................................................................... 119
5.3.7 Watchdog timer mode register (WDTM)...................................................................................... 120
5.3.8 Noise elimination......................................................................................................................... 120
5.3.9 Edge detection function............................................................................................................... 121
5.4 Software Exception.............................................................................................................................. 122
5.4.1 Operation..................................................................................................................................... 122
5.4.2 Restore........................................................................................................................................ 123
5.4.3 EP flag......................................................................................................................................... 124
5.5 Exception Trap ..................................................................................................................................... 124
5.5.1 Illegal op code definition.............................................................................................................. 124
5.5.2 Operation..................................................................................................................................... 124
5.5.3 Restore........................................................................................................................................ 125
5.6 Priority Control..................................................................................................................................... 127
5.6.1 Priorities of interrupts and exceptions......................................................................................... 127
5.6.2 Multiple interrupt processing ....................................................................................................... 127
5.7 Interrupt Latency Time......................................................................................................................... 130

11
5.8 Periods Where Interrupt is Not Acknowledged................................................................................. 130
CHAPTER 6 CLOCK GENERATION FUNCTION............................................................................. 131
6.1 General.................................................................................................................................................. 131
6.2 Composition ......................................................................................................................................... 131
6.3 Clock Output Function......................................................................................................................... 132
6.3.1 Control registers.......................................................................................................................... 132
6.4 Power Saving Functions...................................................................................................................... 135
6.4.1 General ....................................................................................................................................... 135
6.4.2 HALT mode................................................................................................................................. 136
6.4.3 IDLE mode.................................................................................................................................. 139
6.4.4 Software STOP mode ................................................................................................................. 141
6.5 Oscillation Stabilization Time ............................................................................................................. 142
CHAPTER 7 TIMER/COUNTER FUNCTION...................................................................................... 145
7.1 16-bit Timer (TM0, TM1)....................................................................................................................... 145
7.1.1 Overview..................................................................................................................................... 145
7.1.2 Function ...................................................................................................................................... 145
7.1.3 Configuration............................................................................................................................... 147
7.1.4 Timer 0, 1 Control Register......................................................................................................... 150
7.2 Operation .............................................................................................................................................. 158
7.2.1 Operation as interval timer (16 bits)............................................................................................ 158
7.2.2 PPG output operation.................................................................................................................. 160
7.2.3 Pulse width measurement........................................................................................................... 161
7.2.4 Operation as external event counter........................................................................................... 168
7.2.5 Operation to output square wave................................................................................................ 169
7.2.6 Operation to output one-shot pulse............................................................................................. 171
7.2.7 Cautions...................................................................................................................................... 175
7.3 8-bit Timer (TM2-TM5).......................................................................................................................... 178
7.3.1 Functions..................................................................................................................................... 178
7.3.2 Configuration............................................................................................................................... 179
7.3.3 Timer n control register............................................................................................................... 181
7.4 Operation .............................................................................................................................................. 185
7.4.1 Operating as an interval timer (8-bit operation)........................................................................... 185
7.4.2 Operating as external event counter........................................................................................... 187
7.4.3 Operating as square wave output (8-bit resolution).................................................................... 188
7.4.4 Operating as 8-bit PWM output................................................................................................... 189
7.4.5 Cautions...................................................................................................................................... 194
CHAPTER 8 WATCH TIMER.............................................................................................................. 195
8.1 Function................................................................................................................................................ 195
8.2 Configuration........................................................................................................................................ 196
8.3 Watch Timer Control Register............................................................................................................. 197
8.4 Operation .............................................................................................................................................. 198
8.4.1 Operation as watch timer............................................................................................................ 198

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8.4.2 Operation as interval timer.......................................................................................................... 199
CHAPTER 9 WATCHDOG TIMER...................................................................................................... 201
9.1 Functions .............................................................................................................................................. 201
9.2 Configuration........................................................................................................................................ 203
9.3 Watchdog Timer Control Register...................................................................................................... 203
9.4 Operation .............................................................................................................................................. 206
9.4.1 Operating as watchdog timer ...................................................................................................... 206
9.4.2 Operating as interval timer.......................................................................................................... 207
9.5 Standby Function Control Register.................................................................................................... 208
CHAPTER 10 SERIAL INTERFACE FUNCTION .............................................................................. 209
10.1 Overview ............................................................................................................................................... 209
10.2 3-wire Serial I/O (CSI0-CSI2)................................................................................................................ 209
10.2.1 Configuration............................................................................................................................. 210
10.2.2 CSIn control registers................................................................................................................ 211
10.2.3 Operations................................................................................................................................. 213
10.3 I2C Bus (
µ
µµ
µ
PD703015Y, 70F3017Y)........................................................................................................ 217
10.3.1 Configuration............................................................................................................................. 220
10.3.2 I2C control register..................................................................................................................... 222
10.3.3 I2C bus mode functions.............................................................................................................. 232
10.3.4 I2C bus definitions and control methods.................................................................................... 233
10.3.5 I2C interrupt requests (INTIIC0)................................................................................................. 240
10.3.6 Interrupt request (INTIIC0) generation timing and wait control.................................................. 260
10.3.7 Address match detection method.............................................................................................. 261
10.3.8 Error detection........................................................................................................................... 262
10.3.9 Extension code.......................................................................................................................... 262
10.3.10 Arbitration................................................................................................................................ 263
10.3.11 Wake up function..................................................................................................................... 265
10.3.12 Communication reservation..................................................................................................... 266
10.3.13 Other cautions......................................................................................................................... 270
10.3.14 Communication operations...................................................................................................... 271
10.3.15 Timing of data communication ................................................................................................ 273
10.4 Asynchronous Serial Interface (UART0, UART1) .............................................................................. 280
10.4.1 Configuration............................................................................................................................. 280
10.4.2 UARTn control registers............................................................................................................ 282
10.4.3 Operations................................................................................................................................. 287
10.4.4 Asynchronous serial interface (UARTn) mode.......................................................................... 288
10.4.5 Standby function........................................................................................................................ 300
CHAPTER 11 A/D CONVERTER........................................................................................................ 301
11.1 Function ................................................................................................................................................ 301
11.2 Configuration........................................................................................................................................ 303
11.3 Control Registers ................................................................................................................................ 305
11.4 Operation .............................................................................................................................................. 308

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11.4.1 Basic operation ......................................................................................................................... 308
11.4.2 Input voltage and conversion result.......................................................................................... 310
11.4.3 A/D converter operation mode.................................................................................................. 311
11.5 Notes on Using A/D Converter............................................................................................................ 314
CHAPTER 12 DMA FUNCTIONS ....................................................................................................... 317
12.1 Functions.............................................................................................................................................. 317
12.2 Transfer Completion Interrupt Request ............................................................................................. 317
12.3 Control Registers................................................................................................................................. 317
CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) ................................................................. 321
13.1 Function................................................................................................................................................ 321
13.2 Configuration........................................................................................................................................ 322
13.3 RTO Control Registers......................................................................................................................... 323
13.4 Operation .............................................................................................................................................. 326
13.5 Usage .................................................................................................................................................... 327
13.6 Notes ..................................................................................................................................................... 327
CHAPTER 14 PORT FUNCTION........................................................................................................ 329
14.1 Port Configuration................................................................................................................................ 329
14.2 Port Pin Function ................................................................................................................................. 329
14.2.1 Port 0......................................................................................................................................... 329
14.2.2 Port 1......................................................................................................................................... 333
14.2.3 Port 2......................................................................................................................................... 336
14.2.4 Port 3......................................................................................................................................... 339
14.2.5 Ports 4 and 5............................................................................................................................. 341
14.2.6 Port 6......................................................................................................................................... 343
14.2.7 Ports 7 and 8............................................................................................................................. 345
14.2.8 Port 9......................................................................................................................................... 346
14.2.9 Port 10....................................................................................................................................... 348
14.2.10 Port 11..................................................................................................................................... 350
14.2.11 Port 12..................................................................................................................................... 353
CHAPTER 15 RESET FUNCTION...................................................................................................... 357
15.1 General.................................................................................................................................................. 357
15.2 Pin Operations...................................................................................................................................... 357
CHAPTER 16 FLASH MEMORY ( µ
µµ
µ PD70F3017, 70F3017Y)........................................................... 359
16.1 Features ................................................................................................................................................ 359
16.2 Writing by Flash Writer........................................................................................................................ 359
16.3 Programming Environment................................................................................................................. 360
16.4 Communication System ...................................................................................................................... 360
16.5 Pin Connection..................................................................................................................................... 362

14
16.5.1 VPP pin....................................................................................................................................... 362
16.5.2 Serial interface pin..................................................................................................................... 362
16.5.3 RESET pin................................................................................................................................. 364
16.5.4 Port pin...................................................................................................................................... 364
16.5.5 Other signal pins ....................................................................................................................... 364
16.5.6 Power supply............................................................................................................................. 364
16.6 Programming Method .......................................................................................................................... 365
16.6.1 Flash memory control................................................................................................................ 365
16.6.2 Flash memory programming mode............................................................................................ 365
16.6.3 Selection of communication mode ............................................................................................ 366
16.6.4 Communication command......................................................................................................... 366
16.6.5 Resources used ........................................................................................................................ 367
APPENDIX A REGISTER INDEX........................................................................................................ 369
APPENDIX B LIST OF INSTRUTION SET ........................................................................................ 375
APPENDIX C INDEX ............................................................................................................................ 383

15
LIST OF FIGURES (1/5)
Fig. No. Title Page
3-1 CPU Address Space............................................................................................................................... 59
3-2 Image on Address Space ....................................................................................................................... 60
3-3 Memory Map........................................................................................................................................... 62
3-4 Internal ROM Area (with Mask ROM Internal Version)...........................................................................63
3-5 External Memory Area (when expanded to 64 K, 256 K, or 1 Mbytes)................................................... 67
3-6 External Memory Area (when expanded to 4 Mbytes)............................................................................ 68
3-7 Memory Expansion Mode Register (MM) Format...................................................................................70
3-8 Memory Address Output Mode Register (MAM) Format ........................................................................ 71
3-9 Recommended Memory Map (Flash Memory Internal Version)............................................................. 74
4-1 Example of Inserting Wait States............................................................................................................ 88
5-1 Non-Maskable Interrupt Processing ....................................................................................................... 105
5-2 Accepting Non-Maskable Interrupt Request........................................................................................... 106
5-3 RETI Instruction Processing................................................................................................................... 107
5-4 Rising Edge Specification Register (EGP0) Format............................................................................... 109
5-5 Falling Edge Specification Register (EGN0) Format .............................................................................. 109
5-6 Maskable Interrupt Processing............................................................................................................... 111
5-7 RETI Instruction Processing................................................................................................................... 112
5-8 Example of Interrupt Nesting Process.................................................................................................... 114
5-9 Example of Processing Interrupt Requests Simultaneously Generated................................................. 116
5-10 Interrupt Control Register (xxICn) Format .............................................................................................. 117
5-11 Inservice Priority Register (ISPR) Format............................................................................................... 119
5-12 Watchdog Timer Mode Register (WDTM) Format.................................................................................. 120
5-13 Software Exception Processing.............................................................................................................. 122
5-14 RETI Instruction Processing................................................................................................................... 123
5-15 Exception Trap Processing..................................................................................................................... 125
5-16 RETI Instruction Processing................................................................................................................... 126
5-17 Pipeline Operation at Interrupt Request Acknowledge........................................................................... 130
6-1 Format of Processor Clock Control Register (PCC)............................................................................... 132
6-2 Format of Power Saving Control Register (PSC).................................................................................... 134
6-3 Format of Oscillation Stabilization Time Select Register (OSTS)........................................................... 135
7-1 Block Diagram of TM0 and TM1............................................................................................................. 146
7-2 Format of 16-Bit Timer Mode Control Register 0, 1 (TMC0, TMC1)....................................................... 151
7-3 Format of Capture/Compare Control Register 0, 1 (CRC0, CRC1)........................................................ 153
7-4 Format of 16-Bit Timer Output Control Register 0, 1 (TOC0, TOC1)...................................................... 155
7-5 Format of Prescaler Mode Register 0 (PRM0)........................................................................................ 156
7-6 Format of Prescaler Mode Register 1 (PRM1)........................................................................................ 157
7-7 Control Register Settings When Timer 0 Operates as Interval Timer..................................................... 158
7-8 Configuration of Interval Timer ............................................................................................................... 159
7-9 Timing of Interval Timer Operation......................................................................................................... 159
7-10 Control Register Settings in PPG Output Operation............................................................................... 160

16
LIST OF FIGURES (2/5)
Fig. No. Title Page
7-11 Control Register Settings for Pulse Width Measurement with
Free Running Counter and One Capture Register ................................................................................ 161
7-12 Configuration for Pulse Width Measurement with Free Running Counter............................................. 162
7-13 Timing of Pulse Width Measurement with Free Running Counter and
One Capture Register (with both edges specified)................................................................................ 162
7-14 Control Register Settings for Measurement of Two Pulse Widths with Free Running Counter............. 163
7-15 CRn1 Capture Operation with Rising Edge Specified............................................................................ 164
7-16 Timing of Pulse Width Measurement with Free Running Counter (with both edges specified)............. 164
7-17 Control Register Settings for Pulse Width Measurement
with Free Running Counter and Two Capture Registers ....................................................................... 165
7-18 Timing of Pulse Width Measurement with Free Running Counter and
Two Capture Registers (with rising edge specified)............................................................................... 166
7-19 Control Register Settings for Pulse Width Measurement by Restarting ................................................ 167
7-20 Timing of Pulse Width Measurement by Restarting (with rising edge specified)................................... 167
7-21 Control Register Settings in External Event Counter Mode................................................................... 168
7-22 Configuration of External Event Counter ............................................................................................... 169
7-23 Timing of External Event Counter Operation (with rising edge specified).............................................. 169
7-24 Control Register Settings in Square Wave Output Mode....................................................................... 170
7-25 Timing of Square Wave Output Operation............................................................................................. 171
7-26 Control Register Settings for One-Shot Pulse Output with Software Trigger......................................... 172
7-27 Timing of One-Shot Pulse Output Operation with Software Trigger ...................................................... 173
7-28 Control Register Settings for One-Shot Pulse Output with External Trigger.......................................... 174
7-29 Timing of One-Shot Pulse Output Operation with External Trigger (with rising edge specified)............ 175
7-30 Start Timing of 16-Bit Timer Register n.................................................................................................. 175
7-31 Timing after Changing Compare Register during Timer Count Operation............................................. 176
7-32 Data Hold Timing of Capture Register................................................................................................... 176
7-33 Operation Timing of OVFn Flag............................................................................................................. 177
7-34 Block Diagram of TM2-TM5................................................................................................................... 179
7-35 Format of TM2, TM3 Timer Clock Selection Register 2 and 3 (TCL2, TCL3)........................................ 181
7-36 Format of TM4, TM5 Timer Clock Selection Register 4 and 5 (TCL4, TCL5)........................................ 182
7-37 Format of 8-Bit Timer Mode Control Register 2-5 (TMC2-TMC5).......................................................... 183
7-38 Timing of Interval Timer Operation ........................................................................................................ 185
7-39 Timing of External Event Counter Operation (when rising edge is set)................................................. 188
7-40 Timing of PWM Output........................................................................................................................... 190
7-41 Timing of Operation Based on CRn0 Transitions .................................................................................. 191
7-42 Cascade Connection Mode with 16-Bit Resolution................................................................................ 193
7-43 Start Timing of Timer n .......................................................................................................................... 194
7-44 Timing After Compare Register Changes During Timer Counting......................................................... 194
8-1 Block Diagram of Watch Timer.............................................................................................................. 195
8-2 Format of Watch Timer Mode Control Register (WTM) ......................................................................... 197
8-3 Operation Timing of Watch Timer/Interval Timer................................................................................... 199
9-1 Block Diagram of Watchdog Timer........................................................................................................ 201

17
LIST OF FIGURES (3/5)
Fig. No. Title Page
9-2 Format of Oscillation Stabilization Time Selection Register (OSTS)...................................................... 203
9-3 Format of Watchdog Timer Clock Selection Register (WDCS)............................................................... 204
9-4 Format of Watchdog Timer Mode Register (WDTM).............................................................................. 205
9-5 Format of Oscillation Stabilization Time Selection Register (OSTS)...................................................... 208
10-1 Block Diagram of 3-wire Serial I/O.......................................................................................................... 210
10-2 Format of Serial Operation Mode Register 0-2 (CSIM0-CSIM2) ............................................................ 211
10-3 Format of Serial Clock Selection Registers 0-2 (CSIS0-CSIS2)............................................................. 212
10-4 Format of Serial Operation Mode Register 0-2 (CSIM0-CSIM2) ............................................................ 213
10-5 Format of Serial Operation Mode Registers 0-2 (CSIM0-CSIM2)........................................................... 214
10-6 Timing of 3-wire Serial I/O Mode............................................................................................................ 215
10-7 Block Diagram of I2C............................................................................................................................... 218
10-8 Serial Bus Configuration Example Using I2C Bus................................................................................... 219
10-9 Format of IIC Control Register (IICC0)................................................................................................... 223
10-10 Format of IIC Status Register (IICS0)..................................................................................................... 227
10-11 Format of IIC Clock Select Register (IICCL0)......................................................................................... 230
10-12 Pin Configuration Diagram...................................................................................................................... 232
10-13 I2C Bus’s Serial Data Transfer Timing .................................................................................................... 233
10-14 Start Conditions...................................................................................................................................... 233
10-15 Address .................................................................................................................................................. 234
10-16 Transfer Direction Specification.............................................................................................................. 235
10-17 ACK Signal ............................................................................................................................................. 236
10-18 Stop Condition........................................................................................................................................ 237
10-19 Wait Signal ............................................................................................................................................. 238
10-20 Arbitration Timing Example..................................................................................................................... 264
10-21 Communication Reservation Timing....................................................................................................... 267
10-22 Timing for Accepting Communication Reservations............................................................................... 268
10-23 Communication Reservation Flow Chart................................................................................................ 269
10-24 Master Operation Flow Chart.................................................................................................................. 271
10-25 Slave Operation Flow Chart.................................................................................................................... 272
10-26 Example of Master to Slave Communication
(when 9-clock Wait Is Selected for Both Master and Slave)................................................................... 274
10-27 Example of Slave to Master Communication
(when 9-clock Wait Is Selected for Both Master and Slave)................................................................... 277
10-28 Block Diagram of UARTn........................................................................................................................ 281
10-29 Format of Asynchronous Serial Interface Mode Register 0, 1 (ASIM0, ASIM1)..................................... 283
10-30 Format of Asynchronous Serial Interface Status Registers 0, 1 (ASIS0, ASIS1)................................... 284
10-31 Format of Baud Rate Generator Control Registers 0, 1 (BRGC0, BRGC1)............................................ 285
10-32 Format of Baud Rate Generator Mode Control Registers 0, 1 (BRGMC0, BRGMC1)............................ 286
10-33 Error Tolerance (when k = 0), including Sampling Errors....................................................................... 294
10-34 Format of Transmit/Receive Data in Asynchronous Serial Interface...................................................... 295
10-35 Timing of Asynchronous Serial Interface Transmit Completion Interrupt ............................................... 297
10-36 Timing of Asynchronous Serial Interface Receive Completion Interrupt ................................................ 298
10-37 Receive Error Timing.............................................................................................................................. 299

18
LIST OF FIGURES (4/5)
Fig. No. Title Page
11-1 Block Diagram of A/D Converter............................................................................................................ 302
11-2 Format of A/D Converter Mode Register (ADM).................................................................................... 305
11-3 Format of Analog Input Channel Specification Register (ADS) ............................................................. 307
11-4 Basic Operation of A/D Converter.......................................................................................................... 309
11-5 Relation between Analog Input Voltage and A/D Conversion Result .................................................... 310
11-6 A/D Conversion by Hardware Start (with falling edge specified) ........................................................... 312
11-7 A/D Conversion by Software Start......................................................................................................... 313
11-8 Processing of Analog Input Pin.............................................................................................................. 315
11-9 A/D Conversion End Interrupt Generation Timing ................................................................................. 316
11-10 Processing of AVDD Pin........................................................................................................................ 316
12-1 Format of DMA Peripheral I/O Address Registers 0 to 2 (DIOA0 to DIOA2) ......................................... 317
12-2 Format of DMA On-chip RAM Address Registers 0 to 2 (DRA0 to DRA2)............................................ 318
12-3 Format of DMA Byte Count Registers 0 to 2 (DBC0 to DBC2).............................................................. 318
12-4 Format of DMA Channel Control Registers 0 to 2 (DCHC0 to DCHC2)................................................. 319
13-1 Block Diagram of RTO........................................................................................................................... 321
13-2 Configuration of Real-Time Output Buffer Registers ............................................................................. 322
13-3 Format of Real-Time Output Port Mode Register (RTPM)..................................................................... 324
13-4 Format of Real-Time Output Port Control Register (RTPC)................................................................... 325
13-5 Example of Operation Timing of RTO (when EXTR = 0, BYTE = 0)...................................................... 326
14-1 Format of Port 0 (P0)............................................................................................................................. 329
14-2 Format of Port 0 Mode Register (PM0).................................................................................................. 331
14-3 Format of Pull-up Resistance Option Register 0 (PU0)......................................................................... 331
14-4 Format of Rising Edge Enable Register (EGP0).................................................................................... 332
14-5 Format of Falling Edge Enable Register (EGN0)................................................................................... 332
14-6 Format of Port 1 (P1)............................................................................................................................. 333
14-7 Format of Port 1 Mode Register (PM1).................................................................................................. 334
14-8 Format of Pull-up Resistance Option Register 1 (PU1)......................................................................... 335
14-9 Format of Port 1 Function Register (PF1).............................................................................................. 335
14-10 Format of Port 2 (P2)............................................................................................................................. 336
14-11 Format of Port 2 Mode Register (PM2).................................................................................................. 337
14-12 Format of Pull-up Resistance Option Register 2 (PU2)......................................................................... 338
14-13 Format of Port 2 Function Register (PF2).............................................................................................. 338
14-14 Format of Port 3 (P3)............................................................................................................................. 339
14-15 Format of Port 3 Mode Register (PM3).................................................................................................. 340
14-16 Format of Pull-up Resistance Option Register 3 (PU3)......................................................................... 341
14-17 Format of Ports 4 and 5 (P4 and P5)..................................................................................................... 341
14-18 Format of Port 4 Mode Register, Port 5 Mode Register (PM4, PM5)..................................................... 343
14-19 Format of Port 6 (P6)............................................................................................................................. 343
14-20 Format of Port 6 Mode Register (PM6).................................................................................................. 344
14-21 Format of Ports 7 and 8 (P7 and P8)..................................................................................................... 345
14-22 Format of Port 9 (P9)............................................................................................................................. 346

19
LIST OF FIGURES (5/5)
Fig. No. Title Page
14-23 Format of Port 9 Mode Register (PM9)................................................................................................... 347
14-24 Format of Port 10 (P10).......................................................................................................................... 348
14-25 Format of Port 10 Mode Register (PM10)............................................................................................... 349
14-26 Format of Pull-up Resistance Option Register 10 (PU10)...................................................................... 350
14-27 Format of Port 10 Function Register (PF10)........................................................................................... 350
14-28 Format of Port 11 (P11).......................................................................................................................... 351
14-29 Format of Port 11 Mode Register (PM11)............................................................................................... 352
14-30 Format of Pull-up Resistance Option Register 11 (PU11)...................................................................... 352
14-31 Format of Port 12 (P12).......................................................................................................................... 353
14-32 Format of Port 12 Mode Register (PM12)............................................................................................... 354
14-33 Format of Port 12 Mode Control Register (PMC12)................................................................................ 355
15-1 System Reset Timing.............................................................................................................................. 357

20
LIST OF TABLES
Table. No. Title Page
3-1 Program Registers................................................................................................................................. 55
3-2 System Register Numbers..................................................................................................................... 56
3-3 Interrupt/Exception Table....................................................................................................................... 64
4-1 Bus Priority............................................................................................................................................. 99
5-1 Interrupt Source List............................................................................................................................... 102
6-1 Operating Statuses during HALT Mode................................................................................................. 137
6-2 Operating Statuses during IDLE Mode.................................................................................................. 139
6-3 Operating States during Software STOP Mode..................................................................................... 141
7-1 Configuration of Timer 0 ........................................................................................................................ 147
7-2 Valid Edge of TIn0 Pin and Capture Trigger of CRn0............................................................................ 148
7-3 Valid Edge of TIn1 Pin and Capture Trigger of CRn0............................................................................ 148
7-4 Timer 2-5 Configuration......................................................................................................................... 179
8-1 Interval Time of Interval Timer............................................................................................................... 196
8-2 Configuration of Watch Timer................................................................................................................ 196
8-3 Interval Time of Interval Timer............................................................................................................... 199
9-1 Runaway Detection Time for Watchdog Timer...................................................................................... 202
9-2 Interval Time.......................................................................................................................................... 202
9-3 Watchdog Timer Configuration.............................................................................................................. 203
9-4 Runaway Detection Time of Watchdog Timer ....................................................................................... 206
9-5 Interval Time of Interval Timer............................................................................................................... 207
10-1 Configuration of CSIn............................................................................................................................. 210
10-2 Configuration of I2C................................................................................................................................ 220
10-3 INTIIC0 Timing and Wait Control........................................................................................................... 260
10-4 Extension Code Bit Definitions............................................................................................................... 262
10-5 Status during Arbitration and Interrupt Request Generation Timing...................................................... 264
10-6 Wait Periods........................................................................................................................................... 266
10-7 Configuration of UARTn......................................................................................................................... 280
10-8 Relation between Main Clock and Baud Rate ....................................................................................... 293
10-9 Receive Error Causes............................................................................................................................ 299
11-1 Configuration of A/D Converter.............................................................................................................. 303
13-1 Configuration of RTO............................................................................................................................. 322
13-2 Operation When Real-Time Output Buffer Registers Are Manipulated.................................................. 323
13-3 Operation Mode and Output Trigger of Real-Time Output Port............................................................. 325
16-1 List of Communication Systems............................................................................................................. 366