NEC V850E/RS1 User manual

User’s Manual
V850E/RS1TM
32-/16-bit Single-Chip Microcontroller with CAN
Interface
Hardware
µPD70F3402, µPD70F3403, µPD70F3403A
Document No. U16702EE3V2UD00
Date Published April 2006
©NEC Electronics Corporation 2006
Printed in Germany
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VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
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All (other) product, brand, or trade names used in this pamphlet are the trademarks or
registered trademarks of their respective owners.
Product specifications are subject to change without notice. To ensure that you have
the latest product data, please contact your local NEC Electronics sales office.
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User’s Manual U16702EE3V2UD00
The information in this document is current as of April, 2006. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
•
•
•
•
•
•
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
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NEC Electronics Corporation
1753, Shimonumabe, Nakahara-ku,
Kawasaki, Kanagawa 211-8668,
Japan
Tel: [phone]
http://www.necel.com/
[America]
NEC Electronics America, Inc.
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Pudong New Area, Shanghai P.R. China P.C:200120
Tel: [phone]
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Tel: [phone]
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Seoul Branch
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NEC Electronics Singapore Pte. Ltd.
238A Thomson Road,
#12-08 Novena Square,
Singapore 307684
Tel: [phone]
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For further information,
please contact:
G05.11-1A
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The Netherlands
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User’s Manual U16702EE3V2UD00
Preface
Readers This User’s Document is intended for users who want to understand the func-
tions of the V850E/RS1.
Purpose This User’s Document presents the hardware manual of V850E/RS1.
Organization This system specification describes the following sections:
•Pin function
•CPU function
•Internal peripheral function
•Flash memory
•Target Electrical Specification
•Package Drawing
•Recommended Soldering Conditions
Legend Symbols and notation are used as follows:
Weight in data notation : Left is high-order column, right is low order column
Active low notation : xxx (pin or signal name is over-scored) or
/xxx (slash before signal name)
Memory map address: : High order at high stage and low order at low stage
Note : Explanation of (Note) in the text
Caution : Item deserving extra attention
Remark : Supplementary explanation to the text
Numeric notation : Binary... XXXX or XXXB
Decimal...
XXXX
Hexadecimal... XXXXH or 0x XXXX
Prefixes representing powers of 2 (address space, memory capacity)
K (kilo): 210 = 1024
M (mega): 220 = 10242= 1,048,576
G (giga): 230 = 10243= 1,073,741,824
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User’s Manual U16702EE3V2UD00
Table of Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chapter 1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.1 Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.5 Pin Configuration (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.6 Configuration of Function Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
1.6.1 Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
1.6.2 On-chip units. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Chapter 2 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.1 List of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.2 Pin States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.3 Description of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.4 Pin I/O Circuit Types, I/O Buffer Power Supply and Handling of Unused Pins . . . . 57
Chapter 3 CPU Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.2 CPU Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.2.1 Program register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.2.2 System register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.2.3 Special registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.3 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.3.1 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.4 Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.4.1 CPU address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.4.2 Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.4.3 Wrap-around of CPU address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.4.4 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.4.5 Memory areas. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.4.6 Recommended use of address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.4.7 Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.5 Programmable I/O Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
3.5.1 Programmable peripheral I/O control register (BPC) . . . . . . . . . . . . . . . . . . . . . 92
3.6 Peripheral I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Chapter 4 Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.2 Basic Port Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.3 Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.3.1 Table of port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.3.2 Port function swap control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.3.3 Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.3.4 Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
4.3.5 Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
4.3.6 Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
4.3.7 Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
4.3.8 Port 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
4.3.9 Port 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
4.3.10 Port CM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
4.3.11 Port CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
4.3.12 Port CT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
4.3.13 Port DL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
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4.4 Port Function Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
4.4.1 Write to I/O ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
4.4.2 Read from I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
4.4.3 I/O port calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
4.5 Port Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
4.6 Port Block Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
4.6.1 Port block type E-SD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
4.6.2 Port block type E-SD4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
4.6.3 Port block type E-SD7E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
4.6.4 Port block type E-SDW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
4.6.5 Port block type N-SDW7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
4.6.6 Port block type N-SD7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
4.6.7 Port block type L-SD1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
4.6.8 Port block type G-SD7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
4.6.9 Port block type U-SD8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
4.6.10 Port block type N-SD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
4.6.11 Port block type E-SDW10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
4.6.12 Port block diagram E-SD1L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
4.6.13 Port block type W-SDW11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
4.6.14 Port block type E-SD7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
4.6.15 Port block type A-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
4.6.16 Port block type U-SDW11E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
4.6.17 Port block type G-SD7A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
4.6.18 Port block type G-SDW8E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
4.6.19 Port block type G-SD6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
4.6.20 Port block type G-SDJ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
4.6.21 Port block type G-SDJ5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
4.6.22 Port block type G-SDJ8E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
4.6.23 Port block type E-DWJ4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
4.6.24 Port block type U-SDW11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
4.6.25 Port block type W-SD11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
4.6.26 Port block type W-SD12E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
4.6.27 Port block type U-SDW10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
4.6.28 Port Block type G-SDW6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
4.6.29 Port block type E-D1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
4.6.30 Port block type E-D4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
4.6.31 Port block type D-7E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
4.6.32 Port block type C-D1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
4.6.33 Port block type B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Chapter 5 Bus Control Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
5.2 Bus Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
5.2.1 Pin status when internal ROM, internal RAM, or peripheral I/O is accessed . . 208
5.2.2 Pin status in each operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
5.3 Memory Block Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
5.3.1 Chip select control function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
5.4 Bus Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
5.4.1 Number of clocks for access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
5.4.2 Bus size setting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
5.4.3 Access by bus size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
5.5 Wait Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
5.5.1 Programmable wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
5.5.2 External wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
5.5.3 Relationship between programmable wait and external wait . . . . . . . . . . . . . . 220
5.5.4 Programmable address wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
5.6 Idle State Insertion Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
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5.7 Bus Hold Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
5.7.1 Functional outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
5.7.2 Bus hold procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
5.7.3 Operation in power save mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
5.8 Bus Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
5.9 Boundary Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
5.9.1 Program space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
5.9.2 Data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
5.10 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
Chapter 6 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
6.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
6.3 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
6.4 PLL Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
6.4.1 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
6.5 Programmable Clock output Function (PCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
6.5.1 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
6.6 Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
6.6.1 To use PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
6.6.2 To use clock through mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
6.6.3 to Use the programmable clock output function (PCL) . . . . . . . . . . . . . . . . . . . 253
Chapter 7 16-Bit Timer/Event Counter P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
7.2 Function Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
7.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
7.4 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
7.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
7.5.1 Anytime write and reload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
7.5.2 Interval timer mode (TPnMD2 to TPnMD0 = 000) . . . . . . . . . . . . . . . . . . . . . . 275
7.5.3 External event counter mode (TPnMD2 to TPnMD0 = 001). . . . . . . . . . . . . . . 278
7.5.4 External trigger pulse mode (TPnMD2 to TPnMD0 = 010). . . . . . . . . . . . . . . . 281
7.5.5 One-shot pulse mode (TPnMD2 to TPnMD0 = 011). . . . . . . . . . . . . . . . . . . . . 284
7.5.6 PWM mode (TPnMD2 to TPnMD0 = 110) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
7.5.7 Free-running mode (TPnMD2 to TPnMD0 = 101) . . . . . . . . . . . . . . . . . . . . . . 291
7.5.8 Pulse width measurement mode (TPnMD2 to TPnMD0 = 110) . . . . . . . . . . . . 297
7.6 Timer Synchronization Operation Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Chapter 8 16-Bit Timer/Event Counter Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
8.2 Function Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
8.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
8.4 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
8.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
8.5.1 Anytime write and reload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
8.5.2 Interval timer mode (TQnMD2 to TQnMD0 = 000) . . . . . . . . . . . . . . . . . . . . . . 324
8.5.3 External event counter mode (TQnMD2 to TQnMD0 = 001) . . . . . . . . . . . . . . 327
8.5.4 External trigger pulse mode (TQnMD2 to TQnMD0 = 010) . . . . . . . . . . . . . . . 331
8.5.5 One-shot pulse mode (TQnMD2 to TQnMD0 = 011) . . . . . . . . . . . . . . . . . . . . 334
8.5.6 PWM mode (TQnMD2 to TQnMD0 = 110) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
8.5.7 Free-running mode (TQnMD2 to TQnMD0 = 101) . . . . . . . . . . . . . . . . . . . . . . 342
8.5.8 Pulse width measurement mode (TQnMD2 to TQnMD0 = 110). . . . . . . . . . . . 349
8.6 Timer Synchronization Operation Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
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Chapter 9 16-Bit Interval Timer M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
9.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356
9.3 Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
9.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
9.4.1 Interval timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
9.4.2 Clock generator and clock enable timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Chapter 10 Functions of Watchdog Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
10.1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
10.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .360
10.3 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
10.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Chapter 11 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
11.1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
11.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369
11.3 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
11.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
11.4.1 Basic operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
11.4.2 Trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
11.4.3 Operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
11.5 Extended Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
11.5.1 Automatic discharge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
11.5.2 Diagnostic mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
11.6 Precautions on Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
11.6.1 Stopping A/D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
11.6.2 Trigger input during A/D conversion operation . . . . . . . . . . . . . . . . . . . . . . . . . 392
11.6.3 External or timer trigger interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
11.6.4 Operation in standby modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
11.6.5 Compare match interrupt in timer trigger mode (External trigger mode) . . . . . 393
11.6.6 Timing that makes the A/D conversion result undefined . . . . . . . . . . . . . . . . . 393
11.7 Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
11.8 How to Read A/D Converter Characteristics Table. . . . . . . . . . . . . . . . . . . . . . . . . . 398
Chapter 12 Asynchronous Serial Interface A (UARTA) . . . . . . . . . . . . . . . . . . . . . . . . 403
12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
12.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .404
12.2.1 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
12.3 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
12.4 Interrupt Request Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
12.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
12.5.1 Data format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
12.5.2 UART transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
12.5.3 Procedure of continuous transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
12.5.4 UART reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
12.5.5 Reception errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
12.5.6 Types and operation of parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
12.5.7 Noise filter of receive data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
12.6 Dedicated Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
12.7 Caution for Use in On-chip Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Chapter 13 3-Wire Serial Interface (CSIB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
13.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431
13.3 Control Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
13.4 Control Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
13.5 Transfer Data Length Change Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
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13.6 Interrupt Request Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
13.7 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
13.7.1 Single transfer mode (master mode, transmission/reception mode) . . . . . . . . 443
13.7.2 Single transfer mode (master mode, reception mode) . . . . . . . . . . . . . . . . . . . 444
13.7.3 Continuous mode (master mode, transmission/reception mode) . . . . . . . . . . . 445
13.7.4 Continuous mode (master mode, reception mode) . . . . . . . . . . . . . . . . . . . . . 446
13.7.5 Continuous reception mode (error). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
13.7.6 Continuous mode (slave mode, transmission/reception mode) . . . . . . . . . . . . 448
13.7.7 Continuous mode (slave mode, reception mode) . . . . . . . . . . . . . . . . . . . . . . . 449
13.7.8 Clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
13.7.9 Output pin status with operation disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
13.8 Operation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
13.9 Prescaler 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
13.9.1 Control registers of prescaler 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
13.9.2 Generation of count clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
Chapter 14 Queued CSI (CSI30, CSI31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
14.1.1 Queued CSI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
14.1.2 Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
14.2 Queued CSI Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
14.3 Explanation of Queued CSI Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
14.3.1 Transmit Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
14.3.2 Serial Data Direction Select Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
14.3.3 Data Length Select Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
14.3.4 Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
14.3.5 Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
14.3.6 Transmission Clock Select Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
14.3.7 Description of the Single Buffer Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . 481
14.3.8 Description of the FIFO Buffer Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . 483
14.3.9 Description of the Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
14.3.10 Additional Timing and Delay Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
14.3.11 Default Pin Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
14.3.12 Transmit Buffer Overflow Interrupt Signal (INTC3nO) . . . . . . . . . . . . . . . . . . . 490
14.4 Operating Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
Chapter 15 DMA Functions (DMA Controller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
15.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .504
15.3 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
15.4 DMA Transfer Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
15.4.1 Transfer targets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
15.4.2 DMA channel priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
15.4.3 DMA transfer start factors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
15.4.4 DMA transfer end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
15.5 Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
15.5.1 Single transfer mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
15.5.2 Fixed channel transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
15.5.3 Block transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
15.5.4 Summary on the transfer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
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12 User’s Manual U16702EE3V2UD00
Chapter 16 FCAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
16.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
16.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
16.1.2 Overview of Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
16.1.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
16.2 CAN Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .528
16.2.1 Frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
16.2.2 Frame types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
16.2.3 Data frame and remote frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
16.2.4 Error frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
16.2.5 Overload frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
16.3 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
16.3.1 Determining bus priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
16.3.2 Bit stuffing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
16.3.3 Multi masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
16.3.4 Multi cast. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
16.3.5 CAN sleep mode/CAN stop mode function. . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
16.3.6 Error control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
16.3.7 Baud rate control function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
16.4 Connection with Target System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
16.5 Internal Registers of CAN controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
16.5.1 CAN controller configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
16.5.2 Register access type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
16.5.3 Register bit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
16.6 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
16.7 Bit Set/Clear Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
16.8 CAN Controller Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
16.8.1 Initialization of CAN module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
16.8.2 Initialization of message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
16.8.3 Redefinition of message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
16.8.4 Transition from initialization mode to operation mode . . . . . . . . . . . . . . . . . . . 627
16.8.5 Resetting error counter CnERC of CAN module . . . . . . . . . . . . . . . . . . . . . . . 628
16.9 Message Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
16.9.1 Message reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
16.9.2 Receive history list function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
16.9.3 Mask function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
16.9.4 Multi buffer receive block function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634
16.9.5 Remote frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
16.10 Message Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636
16.10.1 Message transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636
16.10.2 Transmit history list function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
16.10.3 Automatic block transmission (ABT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
16.10.4 Transmission abort process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
16.10.5 Remote frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
16.11 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
16.11.1 CAN sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
16.11.2 CAN stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
16.11.3 Example of using power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
16.12 Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
16.13 Diagnosis Functions and Special Operational Modes . . . . . . . . . . . . . . . . . . . . . . . 648
16.13.1 Receive-only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
16.13.2 Single-shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
16.13.3 Self-test mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
16.14 Time Stamp Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
16.14.1 Time stamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
16.15 Baud Rate Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
16.15.1 Bit rate setting conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
16.15.2 Representative examples of baud rate settings . . . . . . . . . . . . . . . . . . . . . . . . 656
16.16 Operation of CAN Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
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User’s Manual U16702EE3V2UD00
Chapter 17 Interrupt/Exception Processing Function . . . . . . . . . . . . . . . . . . . . . . . . . 685
17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
17.2 Non-Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
17.2.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
17.2.2 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
17.2.3 NP flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
17.2.4 Eliminating noise on NMI pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
17.2.5 Function to detect edge of NMI pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
17.3 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
17.3.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
17.3.2 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
17.3.3 Priorities of maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
17.3.4 Interrupt control register (xxICn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
17.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3) . . . . . . . . . . . . . . . . . . . . . . . . 704
17.3.6 In-service priority register (ISPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
17.3.7 Maskable interrupt status flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
17.3.8 Watchdog timer mode register 2 (WDTM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
17.3.9 Eliminating noise on INTP0 to INTP7 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
17.3.10 Function to detect edge of INTP0 to INTP7 pins . . . . . . . . . . . . . . . . . . . . . . . 708
17.4 Software Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714
17.4.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714
17.4.2 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
17.4.3 Exception status flag (EP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
17.5 Exception Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
17.5.1 Illegal opcode definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
17.5.2 Debug trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
17.6 Interrupt Acknowledge Time of CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
17.7 Periods in Which Interrupts Are Not Acknowledged by CPU . . . . . . . . . . . . . . . . . 722
Chapter 18 Standby Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
18.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
18.2 Status Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
18.3 HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .727
18.3.1 Setting and operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
18.3.2 Releasing HALT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
18.4 IDLE1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .729
18.4.1 Setting and operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
18.4.2 Releasing IDLE1 mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
18.5 IDLE2 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .731
18.5.1 Setting and operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
18.5.2 Releasing IDLE2 mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
18.5.3 Securing setup time when releasing IDLE2 mode . . . . . . . . . . . . . . . . . . . . . . 733
18.6 STOP Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .734
18.6.1 Setting and operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
18.6.2 Releasing STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
18.7 Securing Oscillation Stabilization Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
18.8 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
Chapter 19 RESET Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
19.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
19.2 Registers to Check Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
19.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
19.3.1 Reset operation by RESET pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
19.3.2 Reset operation by WDT2RES signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
19.3.3 Reset operation by Low Voltage Detector and Power On Clear. . . . . . . . . . . . 745
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Chapter 20 Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
20.1 Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
20.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
Chapter 21 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
21.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
21.2 Erasure Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
21.2.1 Address assignment in the memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
21.3 Writing with Flash Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
21.4 Programming Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
21.5 Communication Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
21.6 Pin Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756
21.6.1 FLMD0 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756
21.6.2 FLMD1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
21.6.3 Serial interface pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
21.6.4 RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
21.6.5 Port pins (including NMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
21.6.6 Other signal pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
21.6.7 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
21.7 Recommended Circuit Example of the Flash Write Mode . . . . . . . . . . . . . . . . . . . . 761
21.8 Programming Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
21.8.1 Flash memory control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
21.8.2 Flash memory programming mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763
21.8.3 Selection of communication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764
21.8.4 Communication command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764
Chapter 22 On-Chip Debug Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
22.1 Functional Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
22.1.1 Type of on-chip debug unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
22.1.2 Debug functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
22.2 Security Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
22.3 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771
22.4 Operation of On-Chip Debug Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773
22.5 Connection to N-Wire Emulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774
22.5.1 KEL connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774
22.6 Restrictions and Cautions on On-Chip Debug Function . . . . . . . . . . . . . . . . . . . . . 778
Chapter 23 Power-On-Clear Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
23.1 Functions of Power-on-Clear Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
23.2 Configuration of Power-on-Clear Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
23.3 Operation of Power-on-Clear Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
Chapter 24 Low-Voltage Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
24.1 Functions of Low-Voltage Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
24.2 Configuration of Low-Voltage Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
24.3 Registers Controlling Low-Voltage Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
24.4 Operation of Low-Voltage Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
24.4.1 To use for internal reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
24.4.2 To use for interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
24.5 RAM Retention Voltage Detection Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
Chapter 25 Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
25.1 Functions of Clock Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
25.2 Configuration of Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
25.3 Register Controlling Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790
25.4 Operation of Clock Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791
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Chapter 26 CRC Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
26.1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
26.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .793
26.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794
26.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
26.5 Usage Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796
Chapter 27 Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
27.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
27.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
27.2.1 Absolute maximum ratings (µPD70F3402). . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
27.2.2 Absolute maximum ratings (µPD70F3403, µPD70F3403A) . . . . . . . . . . . . . . . 800
27.3 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .800
27.4 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
27.4.1 Recommended operating conditions (µPD70F3402) . . . . . . . . . . . . . . . . . . . . 801
27.4.2 Recommended operating conditions (µPD70F3403, µPD70F3403A) . . . . . . . 801
27.5 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
27.5.1 General condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
27.5.2 Oscillator timing and recommended oscillator connection . . . . . . . . . . . . . . . . 802
27.6 Voltage Regulator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
27.6.1 General condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
27.6.2 Regulator 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
27.6.3 Regulator 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
27.7 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
27.7.1 General condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
27.7.2 DC input/output level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
27.7.3 DC power supply current (µPD70F3402) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806
27.7.4 DC power supply current (µPD70F3403, µPD70F3403A) . . . . . . . . . . . . . . . . 806
27.8 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
27.8.1 General condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
27.8.2 AC test input waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
27.8.3 Input waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
27.8.4 Output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
27.8.5 RESET, NMI, Interrupt and FLMD0 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
27.8.6 Timer P and Timer Q input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
27.8.7 Bus interface timing (µPD70F3403, µPD70F3403A only) . . . . . . . . . . . . . . . . 811
27.8.8 CSIBn timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815
27.8.9 UARTAn timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
27.8.10 CAN Interface timing (µPD70F3402) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
27.8.11 CAN Interface timing (µPD70F3403, µPD70F3403A) . . . . . . . . . . . . . . . . . . . 817
27.8.12 CAN Interface timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
27.8.13 CSI3n timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
27.8.14 A/D Converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
27.8.15 Power-on-clear (POC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
27.8.16 Low-Voltage Indicator (LVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
27.9 Power on Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
27.10 Flash Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
27.10.1 General condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
27.10.2 Basic Flash characteristics (µPD70F3402). . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
27.10.3 Basic Flash characteristics (µPD70F3403, µPD70F3403A) . . . . . . . . . . . . . . . 828
27.10.4 External Flash programmer serial write operation characteristics . . . . . . . . . . 829
27.10.5 Flash programming characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830
Chapter 28 Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
Chapter 29 Recommended Soldering Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
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Appendix A Instruction Set List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
Appendix B Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
Appendix C Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849
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List of Tables
Figure 1-1: Pin Configuration......................................................................................................... 33
Figure 1-2: Internal Block Diagram ................................................................................................ 35
Figure 2-1: Pin I/O Circuits ............................................................................................................ 60
Figure 3-1: CPU Register Set ........................................................................................................ 62
Figure 3-2: Program Counter (PC) Format .................................................................................... 63
Figure 3-3: Interrupt Status Saving Registers (EIPC and EIPSW) Format.................................... 65
Figure 3-4: NMI Status Saving Registers (FEPC and FEPSW) Format ........................................ 66
Figure 3-5: Interrupt Source Register (ECR) Format..................................................................... 66
Figure 3-6: Program Status Word (PSW) Format (1/2).................................................................. 67
Figure 3-7: CALLT Execution Status Saving Registers (CTPC and CTPSW) Format................... 68
Figure 3-8: Exception/Debug Trap Status Saving Registers (DBPC and DBPSW) Format .......... 69
Figure 3-9: CALLT Base Pointer (CTBP) Format .......................................................................... 69
Figure 3-10: Command Register (PRCMD) Format ........................................................................ 72
Figure 3-11: System Status Register (SYS) Format ....................................................................... 73
Figure 3-12: CPU Address Space ...................................................................................................75
Figure 3-13: Image on Address Space ............................................................................................ 76
Figure 3-14: Program Space ........................................................................................................... 77
Figure 3-15: Data Space.................................................................................................................. 77
Figure 3-16: Data Memory Map (Physical Addresses) .................................................................... 78
Figure 3-17: Program Memory Map................................................................................................. 79
Figure 3-18: Memory Map Area for µPD70F3402, µPD70F3403 and µPD70F3403A..................... 80
Figure 3-19: Internal ROM Area ...................................................................................................... 81
Figure 3-20: Internal RAM Area (10 KB).......................................................................................... 82
Figure 3-21: Internal RAM Area (16 KB).......................................................................................... 82
Figure 3-22: Internal Peripheral I/O Area......................................................................................... 83
Figure 3-23: Wrap-Around Using µPD70F3402 / µPD70F3403 / µPD70F3403A............................ 84
Figure 3-24: Recommended Memory Map ...................................................................................... 85
Figure 3-25: System Wait Control Register (VSWC) Format .......................................................... 86
Figure 3-26: On-Chip Debug Mode Register (OCDM) Format ....................................................... 87
Figure 3-27: Timing Chart When On-Chip Debug Function Is Not Used......................................... 88
Figure 3-28: Timing Chart of Transition to Normal Operation Mode................................................ 88
Figure 3-29: Timing Chart of Transition to On-Chip Debug Mode ................................................... 89
Figure 3-30: Programmable Peripheral I/O Control Register (BPC) Format ................................... 92
Figure 4-1: Port Configuration Diagram....................................................................................... 105
Figure 4-2: Port Function Swap Control Register Format ........................................................... 111
Figure 4-3: Port Register 0 (P0) Format ..................................................................................... 112
Figure 4-4: Port Mode Register 0 (PM0) Format ......................................................................... 113
Figure 4-5: Port Mode Control Register 0 (PMC0) Format (1/2) ................................................. 113
Figure 4-6: Port Function Control Register 0 (PFC0) Format ..................................................... 114
Figure 4-7: Pull-up Resistor Option Register 0 (PU0) Format .................................................... 115
Figure 4-8: Pull-down Resistor Option Register 0 (PD0) Format ................................................ 115
Figure 4-9: External Interrupt Falling Edge Specification Register 0 (INTF0) Format ................ 116
Figure 4-10: External Interrupt Rising Edge Specification Register 0 (INTR0) Format ................. 117
Figure 4-11: Port Register 1 (P1) Format ..................................................................................... 118
Figure 4-12: Port Mode Register 1 (PM1) Format ........................................................................ 119
Figure 4-13: Port Mode Control Register 1 (PMC1) Format ......................................................... 119
Figure 4-14: Port Function Control Register 1 (PFC1) Format ..................................................... 120
Figure 4-15: Port Function Control Extended Register 1 (PFCE1) Format ................................... 120
Figure 4-16: Pull-up Resistor Option Register 1 (PU1) Format .................................................... 121
Figure 4-17: Pull-down Resistor Option Register 1 (PD1) Format ................................................ 121
Figure 4-18: External Interrupt Falling Edge Specification Register 1 (INTF1) Format ................ 122
Figure 4-19: External Interrupt Rising Edge Specification Register 1 (INTR1) Format ................. 123
Figure 4-20: Port Register 3 (P3) Format ..................................................................................... 125
Figure 4-21: Port Mode Register 3 (PM3) Format ........................................................................ 126
Figure 4-22: Port Mode Control Register 3 (PMC3) Format (1/2) ................................................. 127
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Figure 4-23: Port Function Control Register 3 (PFC3) Format ..................................................... 128
Figure 4-24: Port Function Control Expansion Register 3 (PFCE3) Format ................................. 129
Figure 4-25: Pull-up Resistor Option Register 3 (PU3) Format .................................................... 130
Figure 4-26: Pull-down Resistor Option Register 3 (PD3) Format ................................................ 130
Figure 4-27: External Interrupt Falling Edge Specification Register 3 (INTF3) Format ................ 131
Figure 4-28: External Interrupt Rising Edge Specification Register 3 (INTR3) Format ................. 132
Figure 4-29: Port Register 4 (P4) Format ..................................................................................... 133
Figure 4-30: Port Mode Register 4 (PM4) Format ........................................................................ 134
Figure 4-31: Port Mode Control Register 4 (PMC4) Format ......................................................... 134
Figure 4-32: Pull-up Resistor Option Register 4 (PU4) Format .................................................... 135
Figure 4-33: Pull-down Resistor Option Register 4 (PD4) Format ................................................ 135
Figure 4-34: Port Register 5 (P5) Format ..................................................................................... 136
Figure 4-35: Port Mode Register 5 (PM5) Format ........................................................................ 137
Figure 4-36: Port Mode Control Register 5 (PMC5) Format (1/2) ................................................. 137
Figure 4-37: Port Function Control Register 5 (PFC5) Format ..................................................... 138
Figure 4-38: Pull-up Resistor Option Register 5 (PU5) Format .................................................... 139
Figure 4-39: Pull-down Resistor Option Register 5 (PD5) Format ................................................ 140
Figure 4-40: Port Register 7H, Port Register 7L (P7H, P7L)Format ............................................. 141
Figure 4-41: Port Mode Register 7H, Port Mode Register 7L (PM7H, PM7L)Format ................... 142
Figure 4-42: Port Register 9 (P9) Format ..................................................................................... 144
Figure 4-43: Port Mode Register 9 (PM9) Format ........................................................................ 145
Figure 4-44: Port Mode Control Register 9 (PMC9) Format (1/3) ................................................. 145
Figure 4-45: Port Function Control Register 9 (PFC9) Format ..................................................... 148
Figure 4-46: Port Function Control Expansion Register 9 (PFCE9) Format ................................. 148
Figure 4-47: Pull-up Resistor Option Register 9 (PU9) Format .................................................... 151
Figure 4-48: Pull-down Resistor Option Register 9 (PD9) Format ................................................ 152
Figure 4-49: External Interrupt Falling Edge Specification Register 9H (INTF9H) Format ........... 153
Figure 4-50: External Interrupt Rising Edge Specification Register 9H (INTR9H) Format ........... 154
Figure 4-51: Port Register CM (PCM) Format .............................................................................. 155
Figure 4-52: Port Mode Register CM (PMCM) Format ................................................................. 156
Figure 4-53: Port Mode Control Register CM (PMCCM) Format .................................................. 157
Figure 4-54: Pull-up Resistor Option Register CM (PUCM) Format ............................................. 158
Figure 4-55: Pull-down Resistor Option Register CM (PDCM) Format ......................................... 158
Figure 4-56: Port Register CS (PCS) Format ............................................................................... 159
Figure 4-57: Port Mode Register CS (PMCS) Format .................................................................. 160
Figure 4-58: Port Mode Control Register CS (PMCCS) Format ................................................... 160
Figure 4-59: Pull-up Resistor Option Register CS (PUCS) Format .............................................. 161
Figure 4-60: Pull-down Resistor Option Register CS (PDCS) Format .......................................... 161
Figure 4-61: Port Register CT (PCT) Format ................................................................................ 162
Figure 4-62: Port Mode Register CT (PMCT) Format ................................................................... 163
Figure 4-63: Port Mode Control Register CT (PMCCT) Format .................................................... 164
Figure 4-64: Pull-up Resistor Option Register CT (PUCT) Format ............................................... 165
Figure 4-65: Pull-down Resistor Option Register CT (PDCT) Format .......................................... 165
Figure 4-66: Port Register DL (PDL) Format ................................................................................ 166
Figure 4-67: Port Mode Register DL (PMDL) Format ................................................................... 167
Figure 4-68: Port Mode Control Register DL (PMCDL) Format .................................................... 168
Figure 4-69: Type E-SD1 Block Diagram....................................................................................... 173
Figure 4-70: Type E-SD4 Block Diagram....................................................................................... 174
Figure 4-71: Type E-SD7E Block Diagram .................................................................................... 175
Figure 4-72: Type E-SDW4 Block Diagram ................................................................................... 176
Figure 4-73: Type N-SDW7 Block Diagram................................................................................... 177
Figure 4-74: Type N-SD7 Block Diagram ...................................................................................... 178
Figure 4-75: Type L-SD1 Block Diagram ....................................................................................... 179
Figure 4-76: Type G-SD7 Block Diagram ...................................................................................... 180
Figure 4-77: Type U-SD8 Block Diagram ...................................................................................... 181
Figure 4-78: Type N-SD2 Block Diagram ...................................................................................... 182
Figure 4-79: Type E-SDW10 Block diagram.................................................................................. 183
Figure 4-80: Type E-SD1L Block Diagram..................................................................................... 184
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User’s Manual U16702EE3V2UD00
Figure 4-81: Type W-SDW11 Block Diagram ................................................................................ 185
Figure 4-82: Type E-SD7 Block Diagram ...................................................................................... 186
Figure 4-83: Type A-1 Block Diagram ........................................................................................... 187
Figure 4-84: Type U-SDW11E Block Diagram............................................................................... 188
Figure 4-85: Type G-SD7A Block Diagram.................................................................................... 189
Figure 4-86: Type G-SDW8E Block Diagram ................................................................................ 190
Figure 4-87: Type G-SD6 Block Diagram ...................................................................................... 191
Figure 4-88: Type G-SDJ2 Block Diagram .................................................................................... 192
Figure 4-89: Type G-SDJ5 Block Diagram .................................................................................... 193
Figure 4-90: Type G-SDJ8E Block Diagram.................................................................................. 194
Figure 4-91: Type E-DWJ4 Block Diagram.................................................................................... 195
Figure 4-92: Type U-SDW11 Block Diagram................................................................................. 196
Figure 4-93: Type W-SD11 Block Diagram ................................................................................... 197
Figure 4-94: Type W-SD12E Block Diagram ................................................................................. 198
Figure 4-95: Type U-SDW10 Block Diagram................................................................................. 199
Figure 4-96: Type G-SDW6 Block Diagram................................................................................... 200
Figure 4-97: Type E-D1 Block Diagram......................................................................................... 201
Figure 4-98: Type E-D4 Block Diagram......................................................................................... 202
Figure 4-99: Type D-7E Block Diagram......................................................................................... 203
Figure 4-100: Type C-D1 Block Diagram......................................................................................... 204
Figure 4-101: Type B Block Diagram...............................................................................................205
Figure 5-1: Data Memory Map..................................................................................................... 209
Figure 5-2: Bus Size Configuration Register (BSC) Format ....................................................... 212
Figure 5-3: Little-Endian Address in Word................................................................................... 213
Figure 5-4: Data Wait Control Register 0 (DWC0) Format ......................................................... 219
Figure 5-5: Example of Inserting Wait States in Separate Bus Mode.......................................... 220
Figure 5-6: Address Wait Control Register (AWC) Format ......................................................... 221
Figure 5-7: Bus Cycle Control Register (BCC) Format ............................................................... 222
Figure 5-8: Bus Hold Status Transition Procedure ...................................................................... 224
Figure 5-9: Bus Read Timing (Bus Size: 16 bit, 16-bit Access)................................................... 226
Figure 5-10: Bus Read Timing (Bus Size: 8 bit) ............................................................................ 227
Figure 5-11: Bus Write Timing (Bus Size: 16 bit, 16-bit Access) ................................................... 228
Figure 5-12: Bus Write Timing (Bus Size: 8 bit)............................................................................. 229
Figure 5-13: Address Wait Timing (Bus Size: 16 bit)..................................................................... 230
Figure 5-14: Bus Hold Timing (Bus Size: 16 bit)............................................................................ 231
Figure 6-1: Clock Generator ........................................................................................................ 234
Figure 6-2: Main Peripheral Clock Control Register (MPCCTL) Format (1/2) ............................ 235
Figure 6-3: Extension Clock Select Register (EXCKSEL) Format .............................................. 237
Figure 6-4: Power Save Mode Register (PSMR) Format ............................................................ 238
Figure 6-5: Processor Clock Control Register (PCC) Format ..................................................... 239
Figure 6-6: CPU Operation Clock Status Register (CCLS) Format ............................................ 240
Figure 6-7: Ring-OSC Mode Register (RCM) Format ................................................................. 240
Figure 6-8: Oscillation Stabilization Time Select Register (OSTS) Format ................................. 241
Figure 6-9: Clock Selection Register 2 (OCKS2) Format ........................................................... 242
Figure 6-10: PLL Control Register (PLLCTL0) Format ................................................................. 245
Figure 6-11: PLL Control Register (PLLCTL1) Format ................................................................. 245
Figure 6-12: PLL Lockup Time Specification Register (PLLS) ...................................................... 246
Figure 6-13: Clock Control Register (CKC) Format ...................................................................... 247
Figure 6-14: Clock Selection Register 0 (OCKS0) Format ........................................................... 248
Figure 6-15: Clock Selection Register 1 (OCKS1) Format ........................................................... 249
Figure 6-16: Programmable Clock Mode Register (PCLM) Format .............................................. 250
Figure 6-17: Clock Selection Register 3 (OCKS3) Format ........................................................... 251
Figure 7-1: Block Diagram of Timer P ......................................................................................... 257
Figure 7-2: Capture/Compare Register 0 (TPnCCR0) Format ................................................... 258
Figure 7-3: Capture/Compare Register 1 (TPnCCR1) Format ................................................... 259
Figure 7-4: TMPn Timer Read Buffer Register (TPnCNT) Format ............................................. 260
Figure 7-5: TMPn Control Register 0 (TPnCTL0) Format ........................................................... 261
Figure 7-6: TMPn Control Register 1 (TPnCTL1) Format (1/2) .................................................. 262
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20 User’s Manual U16702EE3V2UD00
Figure 7-7: TMPn Dedicated I/O Control Register 0 (TPnIOC0) Format .................................... 264
Figure 7-8: TMPn Dedicated I/O Control Register 1 (TPnIOC1) Format .................................... 265
Figure 7-9: TMPn Dedicated I/O Control Register 2 (TPnIOC2) Format .................................... 266
Figure 7-10: TMPn Option Register 0 (TPnOPT0) Format ........................................................... 267
Figure 7-11: Selector Operation Control Register 0 (SELCNT0) Format ...................................... 268
Figure 7-12: TIPnm Pin Noise Elimination Control Register n (PnmNFC) Format ....................... 269
Figure 7-13: Flowchart of Basic Operation for Anytime Write........................................................ 271
Figure 7-14: Timing Diagram for Anytime Write............................................................................. 272
Figure 7-15: Flowchart of Basic Operation for Reload................................................................... 273
Figure 7-16: Timing Chart for Reload ............................................................................................ 274
Figure 7-17: Flowchart of Basic Operation in Interval Timer Mode................................................ 275
Figure 7-18: Basic Operation Timing in Interval Timer Mode (1/2) ................................................ 276
Figure 7-19: Flowchart of Basic Operation in External Event Counter Mode ................................ 278
Figure 7-20: Basic Operation Timing in External Event Counter Mode (1/2)................................. 279
Figure 7-21: Flowchart of Basic Operation in External Trigger Pulse Output Mode ...................... 282
Figure 7-22: Basic Operation Timing in External Trigger Pulse Output Mode
(TPnOE0 = 1, TPnOE1 = 1, TPnOL0 = 0, TPnOL1 = 0) ........................................... 283
Figure 7-23: Flowchart of Basic Operation in One-Shot Pulse Mode ............................................ 285
Figure 7-24: Timing of Basic Operation in One-Shot Pulse Mode
(TPnOE0 = 1, TPnOE1 = 1, TPnOL0 = 0, TPnOL1 = 0) ........................................... 286
Figure 7-25: Flowchart of Basic Operation in PWM Mode (1/2) .................................................... 287
Figure 7-26: Basic Operation Timing in PWM Mode (1/2) ............................................................. 289
Figure 7-27: Flowchart of Basic Operation in Free-Running Mode................................................ 292
Figure 7-28: Basic Operation Timing in Free-Running Mode (TPnCCS1 = 0, TPnCCS0 = 0)
(TPnOE0 = 1, TPnOE1 = 1, TPnOL0 = 0, TPnOL1 = 0) ........................................... 293
Figure 7-29: Basic Operation Timing in Free-Running Mode (TPnCCS1 = 1, TPnCCS0 = 1)
(TPnOE0 = 1, TPnOE1 = 1, TPnOL0 = 0, TPnOL1 = 0) ........................................... 294
Figure 7-30: Basic Operation Timing in Free-Running Mode (TPnCCS1 = 1, TPnCCS0 = 0)
(TPnOE0 = 1, TPnOE1 = 1, TPnOL0 = 0, TPnOL1 = 0) ........................................... 295
Figure 7-31: Basic Operation Timing in Free-Running Mode (TPnCCS1 = 0, TPnCCS0 = 1)
(TPnOE0 = 1, TPnOE1 = 1, TPnOL0 = 0, TPnOL1 = 0) ........................................... 296
Figure 7-32: Flowchart of Basic Operation in Pulse Width Measurement Mode ........................... 297
Figure 7-33: Basic Operation Timing in Pulse Width Measurement Mode
(TPnOE0 = 0, TPnOE1 = 0, TPnOL0 = 0, TPnOL1 = 0) ........................................... 298
Figure 7-34: Tuned Operation Image (TMP2, TMP3, TMQ0) ........................................................ 301
Figure 7-35: Basic Operation Timing of Tuned PWM Function (TMP2, TMP3, TMQ0)................. 302
Figure 8-1: Block Diagram of Timer Q ......................................................................................... 305
Figure 8-2: Capture/Compare Register 0 (TQnCCR0) Format ................................................... 306
Figure 8-3: Capture/Compare Register 1 (TQnCCR1) Format ................................................... 307
Figure 8-4: Capture/Compare Register 2 (TQnCCR2) Format ................................................... 308
Figure 8-5: Capture/Compare Register 3 (TQnCCR3) Format ................................................... 309
Figure 8-6: Timer Read Buffer Register (TQnCNT) Format ........................................................ 310
Figure 8-7: Timer Qn Control Register 0 (TQnCTL0) Format ..................................................... 311
Figure 8-8: Timer Q Control Register 1 (TQnCTL1) Format (1/2) ............................................... 312
Figure 8-9: Timer Q Dedicated I/O Control Register 0 (TQnIOC0) Format ................................ 314
Figure 8-10: Timer Q Dedicated I/O Control Register 1 (TQnIOC1) Format ................................ 315
Figure 8-11: Timer Q Dedicated I/O Control Register 2 (TQnIOC2) Format ................................ 316
Figure 8-12: Timer Q Option Register 0 (TQnOPT0) Format ....................................................... 317
Figure 8-13: TIQnm Pin Noise Elimination Control Register n (QnmNFC) Format ....................... 318
Figure 8-14: Flowchart of Basic Operation for Anytime Write........................................................ 320
Figure 8-15: Timing Chart of Any Time Write ................................................................................ 321
Figure 8-16: Flowchart of Basic Operation for Reload................................................................... 322
Figure 8-17: Timing Chart of Reload..............................................................................................323
Figure 8-18: Flowchart of Basic Operation in Interval Timer Mode................................................ 324
Figure 8-19: Basic Operation Timing in Interval Timer Mode (1/2) ................................................ 325
Figure 8-20: Flowchart of Basic Operation in External Event Counter Mode ................................ 328
Figure 8-21: Basic Operation Timing in External Event Counter Mode (1/2)................................. 329
Figure 8-22: Flowchart of Basic Operation in External Trigger Pulse Output Mode ...................... 332
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