NEC V850E/CA1 ATOMIC User manual

Preliminary User’s Manual
V850E/CA1TM ATOMIC
32-/16-bit Single-Chip Microcontroller
Hardware
µPD703123,
µPD70F3123
Document No. U14913EE1V0UM00
Date Published October 2001
NEC Corporation 2001
Printed in Germany

2Preliminary User’s Manual U14913EE1V0UM00
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimatelydegradethedeviceoperation. Stepsmustbetakentostopgenerationofstaticelectricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulatorsthateasilybuildstaticelectricity. Semiconductordevicesmustbestoredandtransported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wriststrap. Semiconductordevicesmust notbetouchedwithbarehands. Similarprecautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
totheinput pins, it is possible that aninternalinputlevelmaybegenerated due to noise, etc., hence
causingmalfunction. CMOSdevicesbehave differentlythanBipolarorNMOSdevices. Inputlevels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.

3
Preliminary User’s Manual U14913EE1V0UM00
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M5 2000.03
The information in this document is current as of 20.09.2001. The information is subject to change without
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4Preliminary User’s Manual U14913EE1V0UM00
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J99.1

5
Preliminary User’s Manual U14913EE1V0UM00
Preface
Readers This manual is intended for users who want to understand the functions of the
V850E/CA1 (nickname Atomic) (µPD70F3123, µPD703123).
Purpose This manual presents the hardware manual of V850E/CA1.
Organization This system specification describes the following sections:
•Pin function
•CPU function
•Internal peripheral function
•Flash memory
Legend Symbols and notation are used as follows:
Weight in data notation : Left is high-order column, right is low order column
Active low notation : xxx (pin or signal name is over-scored) or
/xxx (slash before signal name)
Memory map address: : High order at high stage and low order at low stage
Note : Explanation of (Note) in the text
Caution : Item deserving extra attention
Remark : Supplementary explanation to the text
Numeric notation : Binary . . . xxxx or xxxB
Decimal . . . xxxx
Hexadecimal . . . xxxxH or 0x xxxx
Prefixes representing powers of 2 (address space, memory capacity)
K (kilo): 210 = 1024
M (mega): 220 = 10242= 1,048,576
G (giga): 230 = 10243= 1,073.741,824

6Preliminary User’s Manual U14913EE1V0UM00
[MEMO]

7
Preliminary User’s Manual U14913EE1V0UM00
Table of Contents
Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.2 Device Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.3 Application Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.5 Pin Configuration (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.6 Configuration of Function Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.6.1 Block Diagram of µPD70(F)3123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.6.2 On-chip units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Chapter 2 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.1 List of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2 Description of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.3 Types of Pin I/O Circuit and Connection of Unused Pin . . . . . . . . . . . . . . . . . . . . . . 48
Chapter 3 CPU Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.2 CPU Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.2.1 Program register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.2.2 System register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.3 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.3.1 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.3.2 Operation mode specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.4 Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
3.4.1 CPU address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.4.2 Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
3.4.3 Wrap-around of CPU address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.4.4 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.4.5 Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
3.4.6 External memory expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.4.7 Recommended use of address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.4.8 Peripheral I/O registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.4.9 Programmable peripheral I/O registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.5 Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
3.5.1 Command Register (PRCMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
3.5.2 Peripheral Command Register (PHCMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
3.5.3 Peripheral Status Register (PHS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
3.5.4 Internal peripheral function wait control register VSWC . . . . . . . . . . . . . . . . . . . 118
Chapter 4 Bus Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.2 Bus Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.3 Memory Block Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.3.1 Chip Select Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.4 Bus Cycle Type Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.4.1 Bus cycle type configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.5 Bus Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
4.5.1 Number of access clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
4.5.2 Bus sizing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
4.5.3 Endian control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.5.4 Bus width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.6 Wait Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
4.6.1 Programmable wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
4.6.2 External wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
4.6.3 Relationship between programmable wait and external wait . . . . . . . . . . . . . . . . 140

8Preliminary User’s Manual U14913EE1V0UM00
4.7 Idle State Insertion Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
4.8 Bus Priority Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
4.9 Boundary Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
4.9.1 Program space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
4.9.2 Data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
Chapter 5 Memory Access Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.1 SRAM, External ROM, External I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
5.1.2 SRAM connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
5.1.3 SRAM, external ROM, external I/O access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
5.2 Page ROM Controller (ROMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
5.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
5.2.2 Page ROM connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
5.2.3 On-page/off-page judgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
5.2.4 Page ROM configuration register (PRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
5.2.5 Page ROM access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
Chapter 6 DMA Functions (DMA Controller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
6.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
6.3 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
6.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3) . . . . . . . . . . . . . . . . . . . .165
6.3.2 DMA destination address registers 0 to 3 (DDA0 to DDA3) . . . . . . . . . . . . . . . . 167
6.3.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3) . . . . . . . . . . . . . . . . . . . . .169
6.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3) . . . . . . . . . . . . . . .170
6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3) . . . . . . . . . . . . . . . . . 171
6.3.6 DMA disable status register (DDIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
6.3.7 DMA restart register (DRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
6.3.8 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) . . . . . . . . . . . . . . . . . . . .173
6.4 DMA Bus States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6.4.1 Types of bus states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6.4.2 DMAC bus cycle state transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
6.5 Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
6.5.1 Single transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
6.5.2 Single-step transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
6.5.3 Block transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
6.6 Transfer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
6.6.1 Two-cycle transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
6.7 Transfer Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
6.7.1 Transfer type and transfer object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
6.8 DMA Channel Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.9 Next Address Setting Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
6.10 DMA Transfer Start Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6.11 Forcible Interruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6.12 DMA Transfer End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.12.1 DMA transfer end interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
6.12.2 Terminal count output upon DMA transfer end . . . . . . . . . . . . . . . . . . . . . . . . . .182
6.13 Forcible Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.14 Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
Chapter 7 Interrupt/Exception Processing Function . . . . . . . . . . . . . . . . . . . . . . . . . 183
7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
7.2 Non-Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
7.2.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
7.2.2 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
7.2.3 Non-maskable interrupt status flag (NP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
7.2.4 Edge detection function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194

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7.3 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
7.3.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
7.3.2 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
7.3.3 Priorities of maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
7.3.4 Interrupt control register (PICn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
7.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3) . . . . . . . . . . . . . . . . . . . . . . . . . . 205
7.3.6 In-service priority register (ISPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
7.3.7 Maskable interrupt status flag (ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
7.4 Noise Elimination Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
7.4.1 Analog Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
7.4.2 Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.4.3 Interrupt trigger mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
7.4.4 Filter Edge Detect Mode Register (FEM0n to FEM5n)
for Timer E Input Pins (n=0 to 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
7.4.5 Filter Edge Detect Mode Register (FEM0n to FEM5n)
for INT0, INT1 and INT2 Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
7.5 Software Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
7.5.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
7.5.2 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
7.5.3 Exception status flag (EP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
7.6 Exception Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
7.6.1 Illegal opcode definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
7.6.2 Debug trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
7.7 Multiple Interrupt Processing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
7.8 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
7.9 Periods in Which Interrupts Are Not Acknowledged . . . . . . . . . . . . . . . . . . . . . . . . 223
Chapter 8 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
8.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
8.3 Main system clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
8.4 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
8.4.1 Clock Control Register (CKC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
8.4.2 PLL Status Register (PSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
8.4.3 Clock select pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
8.5 Power Saving Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
8.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
8.5.2 Power Save Modes Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
8.5.3 HALT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
8.5.4 IDLE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
8.5.5 WATCH mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
8.5.6 Software STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
8.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
8.6.1 Power Save Control Register (PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
8.6.2 Power Save Mode Register (PSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
8.7 Securing Oscillation Stabilization Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
8.7.1 Oscillation stabilization time security specification . . . . . . . . . . . . . . . . . . . . . . . . 243
8.7.2 Time base counter (TBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Chapter 9 Timer / Counter (Real Time Pulse Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
9.1 Timer D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
9.1.1 Features (timer D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
9.1.2 Function overview (timer D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
9.1.3 Basic configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
9.1.4 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
9.1.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
9.1.6 Application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
9.1.7 Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

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9.2 Timer E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
9.2.1 Features (timer E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
9.2.2 Function overview (timer E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
9.2.3 Basic configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
9.2.4 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266
9.2.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
Chapter 10 Watch Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
10.1 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
10.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300
10.3 Watch Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
10.4 Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
10.4.1 Operation as watch timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303
10.4.2 Operation as interval timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Chapter 11 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
11.1 Watchdog timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
11.2 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306
11.2.1 Watchdog timer mode register (WDTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306
11.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
11.3.1 Operating as watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
Chapter 12 Serial Interface Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
12.2 Asynchronous Serial Interfaces 0 to 2 (UART0, UART1, UART2) . . . . . . . . . . . . . . 310
12.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
12.2.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
12.2.3 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
12.2.4 Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
12.2.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
12.2.6 Dedicated baud rate generators (BRG) of UARTn (n = 0 to 2) . . . . . . . . . . . . . .330
12.2.7 Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
12.3 Clocked Serial Interfaces 0, 1 (CSI0, CSI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
12.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
12.3.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339
12.3.3 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
12.3.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353
12.3.5 Output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364
12.3.6 Dedicated baud rate generators 0, 1 (BRG0, BRG1) . . . . . . . . . . . . . . . . . . . . .365
Chapter 13 FCAN Interface Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
13.2 Outline of the FCAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .370
13.2.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .370
13.2.2 CAN memory and register layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
13.2.3 Clock structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380
13.2.4 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
13.2.5 Time stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382
13.2.6 Message handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
13.2.7 Mask handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389
13.2.8 Remote frame handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
13.2.9 FCAN System Event Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
13.3 Control and Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394
13.3.1 Bit set/clear function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
13.3.2 Common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396
13.3.3 CAN interrupt pending registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .408
13.3.4 CAN message buffer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .413
13.3.5 CAN Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425

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13.4 Operating Condsiderations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
13.4.1 Rules to be observed for correct baud rate settings . . . . . . . . . . . . . . . . . . . . . . 446
13.4.2 Example for baudrate setting of CAN module . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
13.4.3 Ensuring data consistency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
13.4.4 Operating states of the CAN modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
13.4.5 Initialisation routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
13.5 CAN Bridge ELISA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
13.5.1 Principle of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
13.5.2 Implementation details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
13.5.3 Event processing commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
Chapter 14 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
14.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
14.3 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
14.4 Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
14.5 A/D Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
14.5.1 A/D converter basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
14.5.2 Operation modes and trigger modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
14.6 Operation in A/D Trigger Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
14.6.1 Operation in select mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
14.6.2 Operation in scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
14.7 Operation in A/D Trigger Polling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
14.7.1 Operation in select mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
14.7.2 Operation in scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
14.8 Operation in Timer Trigger Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
14.8.1 Operation in select mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
14.8.2 Operation in scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
14.9 Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
14.9.1 Stopping conversion operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
14.9.2 Trigger input during conversion operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
14.9.3 Timer trigger interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
14.9.4 Operation in standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
Chapter 15 LCD Controller/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
15.1 LCD Controller/Driver Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
15.2 LCD Controller/Driver Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
15.3 LCD Controller/Driver Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
15.4 LCD Memory Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
15.5 Common Signals and Segment Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
15.6 Supplying LCD Drive Voltage VLC0, VLC1, and VLC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .520
15.7 Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
15.7.1 4-time-division display example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
Chapter 16 Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
16.2 Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
16.3 Pin Functions of Each Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
16.3.1 Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
16.3.2 Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
16.3.3 Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
16.3.4 Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
16.3.5 Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
16.3.6 Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
16.4 Port AL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
16.5 Port AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
16.6 Port DL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
16.7 Port CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555

12 Preliminary User’s Manual U14913EE1V0UM00
16.8 Port CT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
16.9 Port CM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
Chapter 17 RESET Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
17.2 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .561
17.3 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .563
Chapter 18 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
18.1 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
18.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
Chapter 19 Internal Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
19.2 Voltage Comparator Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .568
19.2.1 Internal voltage comparator control register (VCMPM) . . . . . . . . . . . . . . . . . . . . 570
Chapter 20 Flash Memory (µPD70F3123) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
20.2 Writing by Flash writer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
20.3 Programming Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
20.4 Communication System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
20.5 Flash Programming Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
20.6 Pin Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
20.6.1 VPP0/VPP1 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .575
20.6.2 Serial interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .576
20.6.3 RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .578
20.6.4 NMI pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .578
20.6.5 MODE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .578
20.6.6 Port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
20.6.7 Other signal pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .578
20.6.8 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
20.7 Programming Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
20.7.1 Flash memory control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .579
20.7.2 Selection of communication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .579
20.8 Selfprogramming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
20.9 Secure Selfprogramming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
20.9.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
20.9.2 Signature Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .581
20.9.3 Secure Selfprogramming flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .581
20.9.4 Advantages of Secure Selfprogramming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .583
Appendix A Instruction Set List ....................................................................................... 585
Appendix B Index .............................................................................................................. 593

13
Preliminary User’s Manual U14913EE1V0UM00
List of Figures
Figure 1-1: Pin configuration of the µPD70(F)3123 microcontroller .............................................. 24
Figure 1-2: Block diagram of the µPD70(F)3123 microcontroller .................................................. 26
Figure 2-1: Pin I/O Circuits ........................................................................................................... 51
Figure 3-1: CPU Register Set ....................................................................................................... 54
Figure 3-2: Program Counter (PC) ............................................................................................... 55
Figure 3-3: Interrupt Source Register (ECR) ................................................................................ 56
Figure 3-4: Program Status Word (PSW) ..................................................................................... 57
Figure 3-5: CPU Address Space .................................................................................................. 60
Figure 3-6: Image on Address Space ........................................................................................... 61
Figure 3-7: Wrap-around of Program Space ................................................................................ 62
Figure 3-8: Wrap-around of Data Space ....................................................................................... 62
Figure 3-9: Memory Map (µPD703123, 703F123) ........................................................................ 63
Figure 3-10: Internal RAM Area ...................................................................................................... 67
Figure 3-11: Internal Peripheral I/O Area ........................................................................................ 67
Figure 3-12: Example Application of wrap-around (µPD703123) ................................................... 69
Figure 3-13: Recommended Memory Map ..................................................................................... 70
Figure 3-14: Programmable Peripheral I/O Register (Outline) ........................................................ 81
Figure 3-15: Peripheral Area Selection Control Register (BPC) ..................................................... 82
Figure 4-1: Memory Block Function ............................................................................................ 120
Figure 4-2: Chip Area Select Control Registers 0, 1 (1/2) .......................................................... 121
Figure 4-3: Big Endian Addresses within Word .......................................................................... 125
Figure 4-4: Little Endian Addresses within Word ........................................................................ 125
Figure 4-5: Example of Wait Insertion ........................................................................................ 140
Figure 5-1: Example of Connection to SRAM ............................................................................. 146
Figure 5-2: SRAM, External ROM, External I/O Access Timing (1/6) ......................................... 147
Figure 5-3: Example of Page ROM Connections ........................................................................ 154
Figure 5-4: On-Page/Off-Page Judgment during Page ROM Connection (1/2) ..........................155
Figure 5-5: Page ROM Configuration Register (PRC) ............................................................... 157
Figure 5-6: Page ROM Access Timing (1/4) ............................................................................... 158
Figure 6-1: Block Diagram of DMA Controller Configuration ...................................................... 164
Figure 6-2: DMA Source Address Registers H0 to H3 (DSAH0 to DSAH3) ............................... 165
Figure 6-3: DMA Source Address Registers L0 to L3 (DSAL0 to DSAL3) .................................. 166
Figure 6-4: DMA Destination Address Registers 0H to 3H (DDA0H to DDA3H) ........................ 167
Figure 6-5: DMA Destination Address Registers L0 to L3 (DDAL0 to DDAL3) ........................... 168
Figure 6-6: DMA Transfer Count Registers 0 to 3 (DBC0 to DBC3) ........................................... 169
Figure 6-7: DMA Addressing Control Registers 0 to 3 (DADC0 to DADC3) ............................... 170
Figure 6-8: DMA Channel Control Registers 0 to 3 (DCHC0 to DCHC3) ................................... 171
Figure 6-9: DMA Disable Status Register (DDIS) ....................................................................... 172
Figure 6-10: DMA Restart Register (DRST) ................................................................................. 172
Figure 6-11: DMA Trigger Factor Registers 0 to 3 (DTFR0 to DTFR3) (1/3) ............................... 173
Figure 6-12: DMAC Bus Cycle (Two-Cycle Transfer) State Transition ......................................... 177
Figure 6-13: Buffer Register Configuration ................................................................................... 180
Figure 6-14: Example of Forcible Interruption of DMA Transfer ................................................... 181
Figure 7-1: Processing Configuration of Non-Maskable Interrupt ............................................... 188
Figure 7-2: Acknowledging Non-Maskable Interrupt Request .................................................... 189
Figure 7-3: Example of Non-Maskable Interrupt Request Acknowledgement Operation (1/2) ... 190
Figure 7-4: RETI Instruction Processing ..................................................................................... 192
Figure 7-5: Non-maskable Interrupt Status Flag (NP) ................................................................ 193
Figure 7-6: Voltage Comparator Mode Register (VCMPM) ........................................................ 194
Figure 7-7: Maskable Interrupt Processing ................................................................................. 196
Figure 7-8: RETI Instruction Processing ..................................................................................... 197
Figure 7-9: Example of Processing in Which Another Interrupt Request Is Issued
While an Interrupt Is Being Processed (1/2) ............................................................. 199
Figure 7-10: Example of Processing Interrupt Requests Simultaneously Generated ................... 201
Figure 7-11: Interrupt Control Register (PICn) .............................................................................. 202

14 Preliminary User’s Manual U14913EE1V0UM00
Figure 7-12: Interrupt Mask Registers 0 to 3 (IMR0 to IMR3) ......................................................205
Figure 7-13: In-Service Priority Register (ISPR) ...........................................................................206
Figure 7-14: Maskable Interrupt Status Flag (ID) .........................................................................206
Figure 7-15: Timer E Input Circuit Overview .................................................................................207
Figure 7-16: Port Interrupt Input Circuit Overview ........................................................................208
Figure 7-17: Digital Filter State Machine Diagram ........................................................................209
Figure 7-18: Timer E Input Pin Filter Edge Detect Mode Registers
(FEM0n to FEM5n) (n=0 to 2) (1/2) .........................................................................210
Figure 7-19: INT0, INT1 and INT2 Input Pin Filter Edge Detect Mode Registers
(FEM03 to FEM23) ...................................................................................................212
Figure 7-20: Software Exception Processing ................................................................................213
Figure 7-21: RETI Instruction Processing .....................................................................................214
Figure 7-22: Exception Status Flag (EP) .....................................................................................215
Figure 7-23: Exception Trap Processing .......................................................................................216
Figure 7-24: Restore Processing from Exception Trap .................................................................217
Figure 7-25: Debug Trap Processing ............................................................................................ 218
Figure 7-26: Restore Processing from Debug Trap ......................................................................219
Figure 7-27: Pipeline Operation at Interrupt Request Acknowledgment (Outline) ........................222
Figure 8-1: Block Diagram of the Clock Generator .....................................................................225
Figure 8-2: Main system clock oscillator .....................................................................................226
Figure 8-3: Power Save Mode State Transition Diagram ........................................................... 231
Figure 8-4: WATCH mode release by NMI or INT ......................................................................243
Figure 8-5: STOP mode release by NMI or INT ..........................................................................244
Figure 8-6: WATCH mode release by reset or watchdog timer ..................................................245
Figure 8-7: STOP mode release by RESET pin input .................................................................245
Figure 9-1: Block Diagram of Timer D ........................................................................................248
Figure 9-2: Timer D Registers 0, 1 (TMD0, TMD1) ...................................................................249
Figure 9-3: Timer D Compare Registers 0, 1 (CMD0 to CMD1) .................................................250
Figure 9-4: Example of Timing During TMD Operation ...............................................................251
Figure 9-5: Timer D Control Register 0, 1 (TMCD0 to TMCD1) ................................................. 252
Figure 9-6: TMD Compare Operation Example ..........................................................................254
Figure 9-7: Block Diagram of Timer E .........................................................................................259
Figure 9-8: Timer E Time Base Counter 0 Registers 0 to 2 (TBASE00 to TBASE02) ............... 261
Figure 9-9: Timer E Time Base Counter 1 Registers 0 to 2 (TBASE10 to TBASE12) ............... 261
Figure 9-10: Timer E Sub-Channel 0 Capture/Compare Registers 0 to 2 (CVSE00 to 02) .........262
Figure 9-11: Timer E Sub-Channel x Main Capture/Compare Registers 0 to 2
(CVPEx0 to CVPEx2) (x = 1 to 4) ......................................................................... 263
Figure 9-12: Timer E Sub-Channel x Sub Capture/Compare Registers 0 to 2
(CVSEx0 to CVSEx2) (x = 1 to 4) .......................................................................... 264
Figure 9-13: Timer E Sub-Channel 5 Capture/Compare Registers (CVSE50 to CVSE52) .........265
Figure 9-14: Timer E Clock Stop Registers 0 to 2 (STOPTE0 to STOPTE2) ..............................266
Figure 9-15: Timer E Count Clock/Control Edge Selection Registers 0 to 2 (CSE0 to CSE2) ....267
Figure 9-16: Timer E Sub-Channel Input Event Edge Selection Register 0 to 2
(SESE0 to SESE2) ..................................................................................................268
Figure 9-17: Timer E Time Base Control Registers 0 to 2 (TCRE0 to TCRE2) (1/2) ...................269
Figure 9-18: Timer E Output Control Registers 0 to 2 (OCTLE0 to OCTLE2) ..............................271
Figure 9-19: Timer E Sub-Channel 0, 5 Capture/Compare Control Registers 0 to 2
(CMSE050 to CMSE052) ........................................................................................272
Figure 9-20: Timer E Sub-Channel 1, 2 Capture/Compare Control Registers 0 to 2
(CMSE120 to CMSE122) (1/2) ................................................................................273
Figure 9-21: Timer E Sub-Channel 3, 4 Capture/Compare Control Registers 0 to 2
(CMSE340 to CMSE342) (1/2) ................................................................................275
Figure 9-22: Timer E Time Base Status Register (TBSTATE0 to TBSTATE2) ...........................277
Figure 9-23: Timer E Capture/Compare Status Registers 0 to 2 (CCSTATE0 to CCSTATE2) ...278
Figure 9-24: Timer E Output Delay Registers 0 to 2 (ODELE0 to ODELE2) ...............................279
Figure 9-25: Timer E Software Event Capture Registers 0 to 2 (CSCE0 to CSCE2) .................. 280
Figure 9-26: Edge Detection Timing .............................................................................................281
Figure 9-27: Timer E Up Count Timing .........................................................................................282

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Preliminary User’s Manual U14913EE1V0UM00
Figure 9-28: External Control Timing of Timer E .......................................................................... 283
Figure 9-29: Operation in Timer E Up/Down Count Mode ............................................................ 284
Figure 9-30: Timer E Timing in 32-Bit Cascade Operation Mode ................................................. 285
Figure 9-31: Block Diagram of Timer E Multiplex Count Generation Circuit ................................. 286
Figure 9-32: Timer E Multiplex Count Timing ............................................................................... 287
Figure 9-33: Timer E Capture Operation: 16-Bit Buffer-Less Mode .............................................. 288
Figure 9-34: Timer E Capture Operation: Mode with 16-Bit Buffer ............................................... 289
Figure 9-35: Timer E Capture Operation: 32-Bit Cascade Operation Mode ................................. 290
Figure 9-36: Timer E Capture Operation: Capture Control by Software and Trigger Timing ........ 291
Figure 9-37: Timer E Compare Operation: Buffer-Less Mode ...................................................... 292
Figure 9-38: Timer E Compare Operation: Mode with Buffer ....................................................... 293
Figure 9-39: Timer E Capture Operation: Count Value Read Timing ........................................... 294
Figure 9-40: Timer E Compare Operation: Timing of Compare Match
and Write Operation to Register ............................................................................... 295
Figure 9-41: Timer E Signal Output Operation: Toggle Mode 0 and Toggle Mode 1 ................... 296
Figure 9-42: Timer E Signal Output Operation: Toggle Mode 2 and Toggle Mode 3 ................... 297
Figure 9-43: Timer E Signal Output Operation: During Software Control ..................................... 298
Figure 9-44: Timer E Signal Output Operation: During Delay Output Operation .......................... 298
Figure 10-1: Block Diagram of Watch Timer ................................................................................. 299
Figure 10-2: Watch Timer Mode Control Register (WTM) ............................................................ 301
Figure 10-3: Operation Timing of Watch Timer/Interval Timer ...................................................... 304
Figure 11-1: Block Diagram of Watchdog Timer Unit ................................................................... 305
Figure 12-1: Asynchronous Serial Interfaces 0 to 2 Block Diagram ............................................. 312
Figure 12-2: Asynchronous Serial Interface Mode Registers 0 to 2 (ASIM0 to ASIM2) (1/3) ...... 313
Figure 12-3: Asynchronous Serial Interface Status Registers 0 to 2 (ASIS0 to ASIS2) .............. 316
Figure 12-4: Asynchronous Serial Interface Transmit Status Registers 0 to 2 (ASIF0 to ASIF2) . 317
Figure 12-5: Reception Buffer Registers 0 to 2 (RXB0 to RXB2) ................................................. 318
Figure 12-6: Transmission Buffer Registers 0 to 2 (TXB0 to TXB2) ............................................. 319
Figure 12-7: Asynchronous Serial Interface Transmit/Receive Data Format ................................ 321
Figure 12-8: Asynchronous Serial Interface Transmission Completion Interrupt Timing .............. 322
Figure 12-9: Continuous Transmission Starting Procedure .......................................................... 324
Figure 12-10: Continuous Transmission End Procedure ................................................................ 325
Figure 12-11: Asynchronous Serial Interface Reception Completion Interrupt Timing ................... 326
Figure 12-12: When Reception Error Interrupt Is Separated from INTSRn Interrupt
(ISRM Bit = 0) ........................................................................................................... 327
Figure 12-13: When Reception Error Interrupt Is Included in INTSRn Interrupt (ISRM Bit = 1) ..... 327
Figure 12-14: Noise Filter Circuit .................................................................................................... 329
Figure 12-15: Timing of RXDn Signal Judged as Noise ................................................................. 329
Figure 12-16: Baud Rate Generator (BRG) Configuration of UARTn (n = 0 to 2) .......................... 330
Figure 12-17: Clock Select Registers 1 to 3 (CKSR1 to CKSR3) ................................................... 331
Figure 12-18: Baud Rate Generator Control Registers 0 to 2 (BRGC0 to BRGC2) ....................... 332
Figure 12-19: Allowable Baud Rate Range During Reception ........................................................ 335
Figure 12-20: Transfer Rate During Continuous Transmission ...................................................... 337
Figure 12-21: Block Diagram of Clocked Serial Interfaces ............................................................. 340
Figure 12-22: Clocked Serial Interface Mode Registers 0, 1 (CSIM0, CSIM1) ............................... 341
Figure 12-23: Clocked Serial Interface Clock Selection Registers 0, 1 (CSIC0, CSIC1) ............... 342
Figure 12-24: Clocked Serial Interface Reception Buffer Registers 0, 1 (SIRB0, SIRB1) ............. 343
Figure 12-25: Clocked Serial Interface Reception Buffer Registers L0, L1 (SIRBL0, SIRBL1) ...... 344
Figure 12-26: Clocked Serial Interface Read-Only Reception Buffer Registers 0, 1
(SIRBE0, SIRBE1) ................................................................................................... 345
Figure 12-27: Clocked Serial Interface Read-Only Reception Buffer Registers L0, L1
(SIRBEL0, SIRBEL1) ............................................................................................... 346
Figure 12-28: Clocked Serial Interface Transmission Buffer Registers 0, 1 (SOTB0, SOTB1) ...... 347
Figure 12-29: Clocked Serial Interface Transmission Buffer Registers L0, L1 (SOTBL0, SOTBL1) 348
Figure 12-30: Clocked Serial Interface Initial Transmission Buffer Registers 0, 1
(SOTBF0, SOTBF1) ................................................................................................. 349
Figure 12-31: Clocked Serial Interface Initial Transmission Buffer Registers L0, L1
(SOTBFL0, SOTBFL1) ............................................................................................. 350

16 Preliminary User’s Manual U14913EE1V0UM00
Figure 12-32: Serial I/O Shift Registers 0, 1 (SIO0, SIO1) ............................................................. 351
Figure 12-33: Serial I/O Shift Registers L0, L1 (SIOL0, SIOL1) ..................................................... 352
Figure 12-34: Timing Chart in Single Transfer Mode (1/2) ............................................................. 353
Figure 12-35: Timing Chart According to Clock Phase Selection (1/2) ........................................... 355
Figure 12-36: Timing Chart of Interrupt Request Signal Output in Delay Mode (1/2) ..................... 357
Figure 12-37: Repeat Transfer (Receive-Only) Timing Chart ......................................................... 359
Figure 12-38: Repeat Transfer (Transmission/Reception) Timing Chart ........................................ 360
Figure 12-39: Timing Chart of Next Transfer Reservation Period ................................................... 361
Figure 12-40: Transfer Request Clear and Register Access Contention ........................................ 362
Figure 12-41: Interrupt Request and Register Access Contention ................................................. 363
Figure 12-42: Baud Rate Generators 0, 1 (BRG0, BRG1) Block Diagram ..................................... 365
Figure 12-43: Prescaler Mode Registers 0, 1 (PRSM0, PRSM1) ................................................... 366
Figure 12-44: Prescaler Compare Registers 0, 1 (PRSCM0, PRSCM1) ........................................ 367
Figure 13-1: Functional Blocks of the FCAN Interface .................................................................. 370
Figure 13-2: Memory Area of the FCAN System .......................................................................... 371
Figure 13-3: Clock Structure of the FCAN System ....................................................................... 380
Figure 13-4: FCAN Interrupt Bundling of V850E/CA1 (Atomic) .................................................... 381
Figure 13-5: Time Stamp Capturing at Message Reception ......................................................... 382
Figure 13-6: Time Stamp Capturing at Message Transmission .................................................... 383
Figure 13-7: 16-Bit Data Write Operation for Specific Registers ................................................. 395
Figure 13-8: CAN Stop Register (CSTOP) .................................................................................. 396
Figure 13-9: CAN Main Clock Select Register (CGSC) (1/2) ........................................................ 397
Figure 13-10: Configuration of FCAN System Main Clock .............................................................. 398
Figure 13-11: Configuration of FCAN Global Time System Clock .................................................. 398
Figure 13-12: CAN Global Status Register (CGST) (1/2) ............................................................ 399
Figure 13-13: CAN Global Interrupt Enable Register (CGIE) (1/2) ............................................... 401
Figure 13-14: CAN Timer Event Enable Register (CGTEN) ......................................................... 403
Figure 13-15: CAN Global Time System Counter and event generation ........................................ 403
Figure 13-16: CAN Global Time System Counter (CGTSC) .......................................................... 404
Figure 13-17: CAN Message Search Start Register (CGMSS) ..................................................... 405
Figure 13-18: CAN Message Search Start Register (CGMSS) ..................................................... 406
Figure 13-19: CAN Test Bus Register (CTBR) .............................................................................. 407
Figure 13-20: Internal CAN Test Bus Structure .............................................................................. 407
Figure 13-21: CAN Interrupt Pending Register (CCINTP) ............................................................. 408
Figure 13-22: CAN Global Interrupt Pending Register (CGINTP) (1/2) ........................................ 409
Figure 13-23: CAN 1 to 3 Interrupt Pending Registers (C1INTP to C3INTP) (1/2) ....................... 411
Figure 13-24: Message Identifier Registers L00 to L63 and H00 to H63
(M_IDL00 to M_IDL63, M_IDH00 to M_IDH63) ...................................................... 413
Figure 13-25: Message Configuration Registers 00 to 63 (M_CONF00 to M_CONF63) ............... 414
Figure 13-26: Message Status Registers 00 to 63 (M_STAT00 to M_STAT63) ............................ 415
Figure 13-27: Message Set/Clear Status Registers 00 to 63 (SC_STAT00 to SC_STAT63) ........ 417
Figure 13-28: Message Data Registers m0 to m7 (M_DATAm0 to M_DATAm7) (m = 00 to 63) .. 418
Figure 13-29: Message Data Length Code Registers 00 to 63 (M_DLC00 to M_DLC63) ............. 420
Figure 13-30: Message Control Registers 00 to 63 (M_CTRL00 to M_CTRL63) (1/2) .................. 421
Figure 13-31: Message Time Stamp Registers 00 to 63 (M_TIME00 to M_TIME63) ..................... 423
Figure 13-32: Message Event Registers m0, m1, and m3
(M_EVTm0, M_EVTm1, M_EVm3) (m = 00 to 63) .................................................. 424
Figure 13-33: CAN 1 to 3 Mask 0 to 3 Registers L, H
(CxMASKL0 to CxMASKL3, CxMASKH0 to CxMASKH3) (x = 1 to 3) ................... 425
Figure 13-34: CAN 1 to 3 Control Registers (C1CTRL to C3CTRL) (1/4) ................................... 427
Figure 13-35: CAN 1 to 3 Definition Registers (C1DEF to C3DEF) (1/3) .................................... 431
Figure 13-36: CAN 1 to 3 Information Registers (C1LAST to C3LAST) ........................................ 434
Figure 13-37: CAN 1 to 3 Error Counter Registers (C1ERC to C3ERC) ....................................... 435
Figure 13-38: CAN 1 to 3 Interrupt Enable Registers (C1IE to C3IE) (1/2) ................................. 436
Figure 13-39: CAN 1 to 3 Bus Activity Registers (C1BA to C3BA) (1/2) ........................................ 438
Figure 13-40: CAN 1 to 3 Bit Rate Prescaler Registers (C1BRP to C3BRP) (1/2) ........................ 440
Figure 13-41: CAN Bus Bit Timing .................................................................................................. 442
Figure 13-42: CAN 1 to 3 Synchronization Control Registers (C1SYNC to C3SYNC) (1/2)) ......... 443

17
Preliminary User’s Manual U14913EE1V0UM00
Figure 13-43: CAN 1 to 3 Bus Diagnostic Information Registers (C1DINF to C3DINF) ................ 445
Figure 13-44: Sequential CAN Data Read by CPU ........................................................................ 449
Figure 13-45: State Transition Diagram for CAN Modules ............................................................. 451
Figure 13-46: General Initialisation Sequence for the CAN Interface ............................................. 452
Figure 13-47: Initialisation Sequence for a CAN module ................................................................ 454
Figure 13-48: Setting CAN Module into Initialisation State ............................................................. 456
Figure 13-49: Main Operation of ELISA .......................................................................................... 459
Figure 13-50: Event Processing by ELISA ..................................................................................... 460
Figure 13-51: End of Event Processing .......................................................................................... 461
Figure 13-52: Example for Event Processing of ELISA .................................................................. 462
Figure 13-53: ELISA Command Format ........................................................................................ 465
Figure 13-54: Timer Event Pointer Registers 0, 1 and 3 (TEP0, TEP1, TEP3) .............................. 480
Figure 13-55: Script Event Pointer And Command Counter Register (SEPCC) ............................ 481
Figure 13-56: ELISA Event Processing Status Register (EEPS) .................................................... 482
Figure 13-57: ELISA Event Processing Status Register (ELSR) (1/2) ........................................... 483
Figure 13-58: ELISA Last Processed Command Register (ELC) ................................................... 485
Figure 13-59: ELISA Temporary Buffer Registers (ETBL, ETBH) .................................................. 486
Figure 14-1: Block Diagram of A/D Converter .............................................................................. 490
Figure 14-2: A/D Scan Mode Register 0 (ADSCM0) (1/2) ............................................................ 491
Figure 14-3: A/D Scan Mode Register 1 (ADSCM1) .................................................................... 493
Figure 14-4: A/D Voltage Detection Mode Register (ADETM) ..................................................... 496
Figure 14-5: A/D Conversion Result Registers 0 to 11 (ADCR0 to ADCR11) .............................. 497
Figure 14-6: Relationship Between Analog Input Voltages and A/D Conversion Results ............ 498
Figure 14-7: Example of Select Mode Operation Timing (ANI1) ................................................... 502
Figure 14-8: Example of Scan Mode Operation Timing (4-Channel Scan (ANI0 to ANI3)) .......... 503
Figure 14-9: Example of Select Mode (A/D Trigger Select) Operation (ANI2) ............................. 504
Figure 14-10: Example of Scan Mode (A/D Trigger Scan) Operation (ANI2-ANI5) ........................ 505
Figure 14-11: Example of Select Mode (A/D Trigger Polling Select) Operation (ANI2) .................. 506
Figure 14-12: Example of Scan Mode (A/D Trigger Polling Scan) Operation (ANI2 to ANI5) ........ 507
Figure 14-13: Example of Timer Trigger Select Mode Operation (ANI4) ....................................... 508
Figure 14-14: Example of Timer Trigger Scan Mode Operation (ANI1 to ANI4) ............................. 510
Figure 15-1: LCD Controller/Driver Block Diagram ....................................................................... 514
Figure 15-2: LCD Clock Select Circuit Block Diagram .................................................................. 514
Figure 15-3: LCD Display Mode Register (LCDM) Format ........................................................... 515
Figure 15-4: Port LCD Segment Selector Registers 0 to 4 (LSEG0 to LSEG4) ........................... 516
Figure 15-5: Common Signal Waveform ...................................................................................... 519
Figure 15-6: Common Signal and Segment Signal Voltages and Phases ................................... 519
Figure 15-7: Example of Connection of LCD Drive Power Supply ................................................ 521
Figure 15-8: 4-Time-Division LCD Display Pattern and Electrode Connections ........................... 522
Figure 15-9: 4-Time-Division LCD Panel Connection Example .................................................... 523
Figure 15-10: 4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) ....................... 524
Figure 16-1: Type A Block Diagram .............................................................................................. 530
Figure 16-2: Type B Block Diagram .............................................................................................. 531
Figure 16-3: Type C Block Diagram ............................................................................................. 532
Figure 16-4: Type D Block Diagram ............................................................................................. 533
Figure 16-5: Type E Block Diagram .............................................................................................. 534
Figure 16-6: Type F Block Diagram .............................................................................................. 535
Figure 16-7: Type G Block Diagram ............................................................................................. 536
Figure 16-8: Type H Block Diagram ............................................................................................. 537
Figure 16-9: Port 1 (P1) ................................................................................................................ 538
Figure 16-10: Port 1 Mode Register (PM1) ..................................................................................... 538
Figure 16-11: Port 1 Mode Control Register (PMC1) ...................................................................... 539
Figure 16-12: Port 2 (P2) ................................................................................................................ 540
Figure 16-13: Port 2 Mode Register (PM2) ..................................................................................... 540
Figure 16-14: Port 2 Mode Control Register (PMC2) ...................................................................... 541
Figure 16-15: Port 3 (P3) ................................................................................................................ 542
Figure 16-16: Port 3 Mode Register (PM3) ..................................................................................... 542
Figure 16-17: Port 3 Mode Control Register (PMC3) ...................................................................... 543

18 Preliminary User’s Manual U14913EE1V0UM00
Figure 16-18: Port 4 (P4) ................................................................................................................ 544
Figure 16-19: Port 4 Mode Register (PM4) ..................................................................................... 544
Figure 16-20: Port 4 Mode Control Register (PMC4) ...................................................................... 545
Figure 16-21: Port 5 (P5) ................................................................................................................ 546
Figure 16-22: Port 5 Mode Register (PM5) ..................................................................................... 546
Figure 16-23: Port 5 Mode Control Register (PMC5) ...................................................................... 547
Figure 16-24: Port 6 (P6) ................................................................................................................ 548
Figure 16-25: Port 6 Mode Register (PM6) ..................................................................................... 548
Figure 16-26: Port 6 Mode Control Register (PMC6) ...................................................................... 549
Figure 16-27: Port AL (PAL) ........................................................................................................... 550
Figure 16-28: Port AL Mode Register (PMAL) ................................................................................ 550
Figure 16-29: Port AL Mode Control Register (PMCAL) ................................................................. 550
Figure 16-30: Port AH (PAH) .......................................................................................................... 551
Figure 16-31: Port AH Mode Register (PMAH) ............................................................................... 551
Figure 16-32: Port AH Mode Control Register (PMCAH) ................................................................ 552
Figure 16-33: Port DL (PDL) ........................................................................................................... 553
Figure 16-34: Port DL Mode Register (PMDL) ................................................................................ 553
Figure 16-35: Port DL Mode Control Register (PMCDL) ................................................................ 554
Figure 16-36: Port CS (PCS) .......................................................................................................... 555
Figure 16-37: Port CS Mode Register (PMCS) ............................................................................... 555
Figure 16-38: Port CS Mode Control Register (PMCCS) ................................................................ 556
Figure 16-39: Port CT (PCT) ........................................................................................................... 557
Figure 16-40: Port CT Mode Register (PMCT) ............................................................................... 557
Figure 16-41: Port CT Mode Control Register (PMCCT) ................................................................ 558
Figure 16-42: Port CM (PCM) ......................................................................................................... 559
Figure 16-43: Port CM Mode Register (PMCM) .............................................................................. 559
Figure 16-44: Port CM Mode Control Register (PMCCM) .............................................................. 560
Figure 17-1: Reset signal acknowledgment .................................................................................. 562
Figure 17-2: Reset at power-on .................................................................................................... 562
Figure 18-1: Regulator .................................................................................................................. 565
Figure 19-1: Block Diagram of Voltage Comparator ..................................................................... 567
Figure 19-2: Internal Voltage Comparator .................................................................................... 569
Figure 20-1: Programming Environment in Conjunction with External Flash Writer ..................... 572
Figure 20-2: Flash Writer Communication via CSI0 ...................................................................... 573
Figure 20-3: Application Example for Flash Selfprogramming ...................................................... 574
Figure 20-4: Pin Handling of VPP0/VPP1 pins ................................................................................ 575
Figure 20-5: Conflict between Flash Writer and Other Output Pin ................................................ 576
Figure 20-6: Malfunction of Other Input Pins ................................................................................ 577
Figure 20-7: Conflict between Flash Writer Reset Line and Reset Signal Generation Circuit ...... 578
Figure 20-8: Flow Chart of Flash Memory Manipulation ............................................................... 579
Figure 20-9: Configuration in Selfprogramming Mode .................................................................. 580
Figure 20-10: Secure Selfprogramming Flow (1/2) ......................................................................... 582

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Preliminary User’s Manual U14913EE1V0UM00
List of Tables
Table 3-1: Program Registers ......................................................................................................... 55
Table 3-2: System Register Numbers ............................................................................................. 56
Table 3-3: Register Initial Values by Operation Modes .................................................................. 58
Table 3-4: List of Peripheral I/O Registers (Sheet 1 of 10) ............................................................ 71
Table 3-5: List of programmable peripheral I/O registers (Sheet 1 of 32) ..................................... 83
Table 4-1: Number of Bus Access Clocks .................................................................................... 124
Table 4-2: Bus Priority Order ....................................................................................................... 142
Table 6-1: Relationship Between Transfer Type and Transfer Object .......................................... 179
Table 7-1: Interrupt/Exception Source List (Sheet 1 of 3) ............................................................ 184
Table 7-2: Addresses and Bits of Interrupt Control Registers (Sheet 1 of 2) ............................... 203
Table 7-3: Interrupt Response Time ............................................................................................. 222
Table 8-1: PLL mode / direct mode .............................................................................................. 228
Table 8-2: Relation system clock to resonator frequency ............................................................229
Table 8-3: CESEL setting ............................................................................................................. 229
Table 8-4: Power Saving Modes Overview ................................................................................... 230
Table 8-5: Power Saving Mode Frequencies ............................................................................... 232
Table 8-6: Operating states in HALT mode .................................................................................. 234
Table 8-7: Operation after HALT mode release by interrupt request ............................................ 235
Table 8-8: Operating States in IDLE Mode ................................................................................... 236
Table 8-9: Operating States in WATCH Mode .............................................................................. 237
Table 8-10: Operation after WATCH mode release by interrupt request ........................................ 238
Table 8-11: Operating States in STOP Mode ................................................................................. 239
Table 8-12: Counting Time Examples ........................................................................................... 246
Table 9-1: Timer D Configuration List .......................................................................................... 248
Table 9-2: Timer E Configuration List .......................................................................................... 258
Table 9-3: Meaning of Signals in Block Diagram ......................................................................... 260
Table 10-1: Interval Time of Interval Timer (fSUB = 4 MHz) ............................................................ 300
Table 10-2: Configuration of Watch Timer ...................................................................................... 300
Table 10-3: Interval Time of Interval Timer ..................................................................................... 303
Table 11-1: Runaway Detection Time by Watchdog Timer ............................................................ 305
Table 11-2: Runaway Detection Time by Watchdog Timer ............................................................ 307
Table 12-1: Generated Interrupts and Default Priorities ................................................................. 320
Table 12-2: Transmission Status and Whether or Not Writing Is Enabled ..................................... 323
Table 12-3: Reception Error Causes .............................................................................................. 327
Table 12-4: Baud Rate Generator Setting Data ............................................................................. 334
Table 12-5: Maximum and Minimum Allowable Baud Rate Error ................................................... 336
Table 12-6: Baud Rate Generator Setting Data .............................................................................. 368
Table 13-1: Configuration of the CAN Message Buffer Section .................................................... 372
Table 13-2: CAN Message Buffer Registers Layout ...................................................................... 373
Table 13-3: Relative Addresses of CAN Interrupt Pending Registers ........................................... 374
Table 13-4: Relative Addresses of CAN Common Registers ........................................................ 375
Table 13-5: Relative Addresses of CAN Module 1 Registers ........................................................ 376
Table 13-6: Relative Addresses of CAN Module 2 Registers ....................................................... 377
Table 13-7: Relative Addresses of CAN Module 3 Registers ....................................................... 378
Table 13-8: Relative Addresses of CAN Bridge ELISA Registers ................................................. 379
Table 13-9: Transmitted Data On the CAN Bus (ATS = 1) ............................................................. 383
Table 13-10: Example for Automatic Transmission Priority Detection .............................................385
Table 13-11: Example for Transmit Buffer Allocation When More Than 5 Buffers
Linked to a CAN Module .............................................................................................. 386
Table 13-12: Storage Priority for Reception of Data Frames ............................................................ 387
Table 13-13: Storage priority for Reception of Remote Frames ....................................................... 387
Table 13-14: Inner Storage Priority Within a Priority Class .............................................................. 388
Table 13-15: Remote Frame Handling upon Reception into a Transmit Message Buffer ................ 392
Table 13-16: CAN Message Processing by TRQ and RDY Bits ...................................................... 416
Table 13-17: Address Offsets of the CAN 1 to 3 Mask Registers .................................................... 426

20 Preliminary User’s Manual U14913EE1V0UM00
Table 13-18: Format of 64-bit Temporary Buffer .............................................................................. 464
Table 13-19: Format of Temporary Sum ..........................................................................................464
Table 14-1: Correspondence between ADCRm (m = 0 to 11) Register Names and Addresses ....497
Table 14-2: Correspondence between each Analog Input Pin and ADCRm Registers .................498
Table 15-1: Maximum Number of Display Pixels ............................................................................513
Table 15-2: LCD Controller/Driver Configuration ............................................................................513
Table 15-3: Relationship between LCD Display Data Memory Contents
and Segment/Common Outputs ..................................................................................517
Table 15-4: Memory Layout of LCD Segments ..............................................................................517
Table 15-5: COM Signals ...............................................................................................................518
Table 15-6: LCD Drive Voltage .......................................................................................................518
Table 15-7: Drive Voltage Supply ...................................................................................................520
Table 15-8: Selection and Non-Selection Voltages (COM0 to COM3) ...........................................522
Table 17-1: Operation Status of Each Pin During Reset Period ..................................................... 561
Table 17-2: Initial Values of CPU and Internal RAM After Reset ...................................................563
Table 19-1: Power Supply Voltage Operating Modes .....................................................................568
Table 20-1: List of Communication Systems ..................................................................................579