NEC MuPD754202 User manual

The µ PD754202isamemberofthe75XLSeriesof4-bitsingle-chipmicrocontrollersthatenabledataprocessing
equivalent to that of an 8-bit microcontroller.
ItfeaturesexpandedCPUfunctionscomparedtothe75XSeriesandenableshigh-speed,low-voltageoperation
at 1.8 V, making it suitable for battery-driven applications.
The
µ PD754202(A) is a higher-reliability product compared to the µ PD754202.
Detailed function descriptions, etc., are provided in the following user’s manual. Be sure to read it
when designing.
µ PD754202 User’s Manual: U11132E
FEATURES
•Key return reset function for keyless entry
•Low-voltage operation: VDD = 1.8 to 6.0 V
•On-chip memory
• Program memory (ROM): 2048 ×8 bits
• Data memory (RAM) : 128 ×4 bits
•Variable instruction execution time useful for high-speed operation and power save
• 0.95, 1.91, 3.81, 15.3 µ s (at 4.19-MHz operation)
• 0.67, 1.33, 2.67, 10.7 µ s (at 6.0-MHz operation)
•Compact package (20-pin plastic shrink SOP (300 mil, 0.65-mm pitch))
APPLICATIONS
Automotive electronics such as keyless entry units
The µ PD754202 and µ PD754202(A) have different quality grades. Unless otherwise specified, descriptions in
this data sheet apply to the
µ PD754202.
MOS INTEGRATED CIRCUIT
µ PD754202, 754202(A)
Document No. U12181EJ1V0DS00 (1st edition)
Date Published May 1997 N
Printed in Japan
4-BIT SINGLE-CHIP MICROCONTROLLERS
©
1997
DATA SHEET
The information in this document is subject to change without notice.

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µ PD754202, 754202(A)
ORDERING INFORMATION
Part Number Package Quality Grade
µ PD754202GS-×××-BA5 20-pin plastic SOP (300 mil, 1.27-mm pitch) Standard
µ PD754202GS-×××-GJG 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) Standard
µ PD754202GS(A)-×××-BA5 20-pin plastic SOP (300 mil, 1.27-mm pitch) Special
µ PD754202GS(A)-×××-GJG 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) Special
Remark ××× indicates the ROM code suffix.
Differences between µ PD754202 and µ PD754202(A)
Part Number
µ PD754202 µ PD754202(A)
Item
Quality grade Standard Special
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

3
µ PD754202, 754202(A)
FUNCTION LIST
Parameter Function
Instruction execution time • 0.95, 1.91, 3.81, 15.3 µ s (system clock: at 4.19-MHz operation)
• 0.67, 1.33, 2.67, 10.7 µ s (system clock: at 6.0-MHz operation)
On-chip memory ROM 2048 ×8 bits
RAM 128 ×4 bits
General-purpose register • 4-bit manipulation: 8 ×4 banks
• 8-bit manipulation: 4 ×4 banks
I/O port CMOS input 4 Mask option-specifiable on-chip pull-up resistor
CMOS input/output 9 Software-specifiable on-chip pull-up resistor connection
Total 13
Timer 4 channels
• 8-bit timer counter: 3 channels
(Usable as 16-bit timer counter)
• Basic interval timer/watchdog timer: 1 channel
Bit sequential buffer (BSB) 16 bits
Vectored interrupt External: 1, Internal: 4
Test input External: 1 (key return reset function provided)
System clock oscillation circuit Ceramic/crystal oscillation circuit
Standby function STOP/HALT mode
Operating ambient temperature TA= –40 to +85 ˚C
Supply voltage VDD = 1.8 to 6.0 V
Package • 20-pin plastic SOP (300 mil, 1.27-mm pitch)
• 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch)

4
µ PD754202, 754202(A)
CONTENTS
1. PIN CONFIGURATION (Top View) ....................................................................................................6
2. BLOCK DIAGRAM...............................................................................................................................7
3. PIN FUNCTION ....................................................................................................................................8
3.1 Port Pins ......................................................................................................................................8
3.2 Non-port Pins ..............................................................................................................................9
3.3 Pin Input/Output Circuits .........................................................................................................10
3.4 Recommended Connection of Unused Pins ..........................................................................11
4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE .......................................12
4.1 Differences between Mk I Mode and Mk II Mode....................................................................12
4.2 Setting Method of Stack Bank Select Register (SBS) ...........................................................13
5. MEMORY CONFIGURATION ............................................................................................................14
6. PERIPHERAL HARDWARE FUNCTION .........................................................................................17
6.1 Digital I/O Port ...........................................................................................................................17
6.2 Clock Generator ........................................................................................................................17
6.3 Basic Interval Timer/Watchdog Timer.....................................................................................19
6.4 Timer Counter ...........................................................................................................................20
6.5 Bit Sequential Buffer ................................................................................................................24
7. INTERRUPT FUNCTION AND TEST FUNCTION ...........................................................................25
8. STANDBY FUNCTION.......................................................................................................................27
9. RESET FUNCTION ............................................................................................................................28
9.1 Configuration and Operation Status of Reset Function........................................................28
9.2 Watchdog Flag (WDF), Key Return Flag (KRF) ......................................................................32
10. MASK OPTION ..................................................................................................................................34
11. INSTRUCTION SETS.........................................................................................................................35
12. ELECTRICAL SPECIFICATIONS......................................................................................................44
13. CHARACTERISTIC CURVES (REFERENCE VALUES) ................................................................53
14. PACKAGE DRAWINGS......................................................................................................................55
15. RECOMMENDED SOLDERING CONDITIONS..................................................................................57

5
µ PD754202, 754202(A)
APPENDIX A. µ PD754202, 75F4264 FUNCTION LIST .....................................................................58
APPENDIX B. DEVELOPMENT TOOLS ..............................................................................................59
APPENDIX C. RELATED DOCUMENTS ..............................................................................................62

6
µ PD754202, 754202(A)
1. PIN CONFIGURATION (Top View)
• 20-pin plastic SOP (300 mil, 1.27-mm pitch)
µ PD754202GS-×××-BA5
µ PD754202GS(A)-×××-BA5
• 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch)
µ PD754202GS-×××-GJG
µ PD754202GS(A)-×××-GJG
IC: Internally Connected (Connect directly to VDD)
Pin Identification
IC : Internally Connected
INT0 : External Vectored Interrupt
KR4 to KR7 : Key Return 4 to 7
KRREN : Key Return Reset Enable
P30 to P33 : Port 3
P60 to P63 : Port 6
P70 to P73 : Port 7
P80 : Port 8
PTO0 to PTO2 : Programmable Timer Output 0 to 2
RESET : Reset
VDD : Positive Power Supply
VSS : Ground
X1, X2 : System Clock (Ceramic/Crystal)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RESET
X1
X2
V
SS 
IC
V
DD 
P60
P61/INT0
P62
P63
KRREN
P80
P30/PTO0
P31/PTO1
P32/PTO2
P33
P70/KR4
P71/KR5
P72/KR6
P73/KR7

7
µ PD754202, 754202(A)
2. BLOCK DIAGRAM
BASIC INTERVAL
TIMER/WATCHDOG
TIMER
8-BIT TIMER
COUNTER#0
8-BIT
TIMER
COUNTER# 1
8-BIT
TIMER
COUNTER#2
CASCADED
16-BIT
TIMER
COUNTER
INTERRUPT
CONTROL
INTBT RESET
INTT0 TOUT
INTT1
INTT2
PTO0/P30
PTO1/P31
PTO2/P32
INT0/P61
KR4/P70-
KR7/P73
ALU
PROGRAM COUNTER
PROGRAM MEMORY
(ROM)
2048
× 8 BITS
DECODE
AND
CONTROL
CY
SP (8)
SBS
BANK
GENERAL REG.
DATA MEMORY
(RAM)
128
× 4 BITS
PORT3 4
PORT6 4
PORT7 4
PORT8 1
BIT SEQ. BUFFER (16)
P30-P33
P60-P63
P70-P73
P80
CLOCK
DIVIDER SYSTEM CLOCK GENERATOR
STAND BY
CONTROL
f X /2
N
X1 X2
Φ
CPU CLOCK
IC V
DD V SS RESET
4
KRREN

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µ PD754202, 754202(A)
3. PIN FUNCTION
3.1 Port Pins
Pin Name Input/Output Alternate Function 8-bit After Reset
I/O Circuit
Function I/O TypeNote
P30 Input/Output PTO0 – Input E-B
P31 PTO1
P32 PTO2
P33 –
P60 Input/Output – – Input F -A
P61 INT0
P62 –
P63 –
P70 Input KR4 – Input B -A
P71 KR5
P72 KR6
P73 KR7
P80 Input/Output – – Input F -A
Note Circled characters indicate Schmitt trigger input.
Programmable 4-bit input/output port
(PORT3).
This port can be specified input/output bit-
wise.
On-chip pull-up resistor can be specified by
software in 4-bit units.
Programmable4-bitinput/outputport (PORT6).
This port can be specified input/output bit-wise.
On-chip pull-up resistor can be specified by
software in 4-bit units.
Noise eliminator can be selected on P61/
INT0.
4-bit input port (PORT7).
On-chip pull-up resistor can be specified
bit-wise (mask option).
1-bit input/output port (PORT8).
On-chip pull-up resistor can be specified by
software.

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µ PD754202, 754202(A)
3.2 Non-port Pins
Pin Name Input/Output Alternate Function After Reset
I/O Circuit
Function TypeNote
PTO0 Output P30 Timer counter output Input E-B
PTO1 P31
PTO2 P32
INT0 Input P61 Edge detection vectored Noise eliminator/ Input F -A
interrupt input (detected asynchronous
edge is selectable) selectable
Noise eliminator
selectable
KR4 to KR7 Input P70 to P73 Falling edge detection testable input Input B -A
KRREN Input – Key return reset enable. Input B
When KRREN = high level in STOP mode, reset
signal is generated at falling edge of KRn.
X1 Input – System clock oscillation crystal/ceramic – –
connection pin.
X2 – If using an external clock, input to X1 and reverse
input to X2.
RESET Input – System reset input (low-level active). – B -A
Pull-up resistor can be incorporated on-chip
(mask option).
IC – – Internally connected. Connect directly to VDD.––
VDD – – Positive power supply – –
VSS – – Ground potential – –
Note Circled characters indicate Schmitt trigger input.

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µ PD754202, 754202(A)
3.3 Pin Input/Output Circuits
The µ PD754202 pin input/output circuits are shown schematically.
TYPE A
TYPE B
TYPE D
TYPE E-B 
TYPE B-A TYPE F-A
V
DD
IN P-ch
N-ch
data
output
disable N-ch
P-ch
IN
OUT
V
DD
P-ch
output
disable
data
P.U.R.
enable
Type D
Type A
IN/OUT
V
DD
P.U.R. (Mask Option)
IN
V
DD
P.U.R.
P.U.R.
enable P-ch
IN/OUT
Type D
Type B
output
disable
data
P.U.R. : Pull-Up Resistor
P.U.R. : Pull-Up Resistor
P.U.R. : Pull-Up Resistor
Schmitt trigger input with hysteresis characteristics
CMOS standard input buffer Push-pull output that can be placed in output  high-impedance (both P-ch and N-ch off).
P.U.R.

V
DD

11
µ PD754202, 754202(A)
3.4 Recommended Connection of Unused Pins
Table 3-1. List of Recommended Connection of Unused Pins
Pin Recommended Connecting Method
P30/PTO0 Input state : Independently connect to VSS or VDD via a resistor.
P31/PTO1 Output state: Leave open.
P32/PTO2
P33
P60
P61/INT0
P62
P63
P70/KR4 Connect to VDD.
P71/KR5
P72/KR6
P73/KR7
P80 Input state : Independently connect to VSS or VDD via a resistor.
Output state: Leave open.
KRREN When this pin is connected to VDD, internal reset signal is gener-
ated at the falling edge of the KRn pin in the STOP mode.
When this pin is connected to VSS, internal reset signal is not
generated even if the falling edge of KRn pin is detected in the
STOP mode.
IC Connect directly to VDD.

12
µ PD754202, 754202(A)
4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE
4.1 Differences between Mk I Mode and Mk II Mode
The µ PD754202 75XL CPU has the following two modes: Mk I and Mk II, either of which can be selected. The
mode can be switched by bit 3 of the stack bank select register (SBS).
• Mk I mode : Instructions are compatible with the 75X Series. Can be used in the 75XL CPU with a ROM
capacity of up to 16 Kbytes.
• Mk II mode: Incompatible with 75X Series. Can be used in all the 75XL CPU’s including those products
whose ROM capacity is more than 16 Kbytes.
Table 4-1. Differences between Mk I Mode and Mk II Mode
Mk I mode Mk II mode
Number of stack bytes 2 bytes 3 bytes
for subroutine instructions
BRA !addr1 instruction Not available Available
CALLA !addr1 instruction
CALL !addr instruction 3 machine cycles 4 machine cycles
CALLF !faddr instruction 2 machine cycles 3 machine cycles
Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL
Series. Therefore, this mode is effective for enhancing software compatibility with
products that have a program area of more than 16 Kbytes.
The number of stack bytes (usable area) during execution of subroutine call instruc-
tions increases by 1 byte per stack compared to the Mk I mode when the Mk II mode
is selected.
However, when the CALL !addr and CALL !faddr instructions are used, the machine
cycle becomes longer by 1 machine cycle. Therefore, if more emphasis is placed on
RAM use efficiency and processing performance than on software compatibility, the
Mk I mode should be used.

13
µ PD754202, 754202(A)
4.2 Setting Method of Stack Bank Select Register (SBS)
Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format.
The SBS is set by a 4-bit memory manipulation instruction.
When using the Mk I mode, the SBS must be initialized to 1000B at the beginning of a program. When using
the Mk II mode, it must be initialized to 0000B.
Figure 4-1. Stack Bank Select Register Format
SBS3 SBS2 SBS1 SBS0
3210
Symbol
SBS
Address
F84H
00
0
1
0
Memory bank 0
Other than above setting prohibited
0 must be set in the bit 2 position.
Stack area specification
Mk II mode
Mk I mode
Mode switching specification
Caution Because SBS.3 is set to “1” after a RESET signal is generated, the CPU operates in the
Mk I mode. When executing an instruction in the Mk II mode, set SBS.3 to “0” to select
the Mk II mode.

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µ PD754202, 754202(A)
5. MEMORY CONFIGURATION
•Program Memory (ROM): 2048 ×8 bits (0000H-07FFH)
• Addresses 0000H and 0001H
Vectortable wherein theprogram start addressand thevalues set for the RBE and MBE at the time a RESET
signal is generated are written. Reset start is possible from any address.
• Addresses 0002H to 000DH
VectortablewhereintheprogramstartaddressandvaluessetfortheRBEandMBEbythevectoredinterrupts
are written. Interrupt service can start from any address.
• Addresses 0020H to 007FH
Table area referenced by the GETI instructionNote.
Note The GETI instruction realizes a 1-byte instruction on behalf of any 2-byte instruction, 3-byte
instruction, or two 1-byte instructions. It is used to decrease the number of program steps.
•Data Memory (RAM)
• Data area: 128 words ×4 bits (000H-07FH)
• Peripheral hardware area: 128 words ×4 bits (F80H-FFFH)

15
µ PD754202, 754202(A)
Figure 5-1. Program Memory Map
Note Can be used in Mk II mode only.
Remark In addition to the above, a branch can be made to an address with only the low-order 8 bits of the PC
changed by means of a BR PCDE or BR PCXA instruction.
7 6 0
MBE RBE Internal reset start address (high-order 3 bits)
Internal reset start address (low-order 8 bits)
MBE RBE INTBT start address (high-order 3 bits)
INTBT start address (low-order 8 bits)
MBE RBE INT0 start address (high-order 3 bits)
INT0 start address (low-order 8 bits)
MBE RBE INTT0 start address (high-order 3 bits)
INTT0 start address (low-order 8 bits)
MBE RBE INTT1/INTT2 start address (high-order 3 bits)
INTT1/INTT2 start address (low-order 8 bits)
GETI instruction reference table
0000H
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
000AH
000BH
000CH
000DH
0020H
007FH
0080H
07FFH
CALLF !faddr instruction
entry address
Branch address of
BR !addr
BRCB !caddr
BR BCDE
BR BCXA
BRA !addr1
Note

CALL !addr
CALLA !addr1
Note

instructions

GETI branch/call
address

BR $addr instruction
relative branch address
(–15 to –1, +2 to +16)
Address
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
5 4 3

16
µ PD754202, 754202(A)
Figure 5-2. Data Memory Map
000H
01FH
020H
07FH
080H
0FFH
F80H
FFFH
128 × 4
Not incorporated
128 × 4

(96 × 4)
(32 × 4)
0
15
General-purpose
register area
Stack area
Data area
static RAM (128 × 4)
Peripheral hardware area
Data memory Memory bank

17
µ PD754202, 754202(A)
6. PERIPHERAL HARDWARE FUNCTION
6.1 Digital I/O Port
The following two types of I/O ports are provided.
• CMOS Input (PORT7) : 4
• CMOS Input/Output (PORT3, 6, 8) : 9
Total 13
Table 6-1. Types and Features of Digital Ports
Port Name Function Operation and Features Remarks
PORT3 4-bit I/O Can be set to input or output mode bit-wise. Also used for PTO0 to PTO2
pins.
PORT6 Also used for INT0 pin.
PORT7 4-bit input 4-bit input only port Also used for KR4 to KR7 pins.
On-chip pull-up resistor can be specified by mask
option bit-wise.
PORT8 1-bit I/O Can be set to input or output mode bit-wise. –
6.2 Clock Generator
The clock generator provides the clock signals to the CPU and peripheral hardware. Its configuration is shown
in Figure 6-1.
The operation of the clock generator is set with the processor clock control register (PCC). The instruction
execution time can be changed as follows.
• 0.95, 1.91, 3.81, 15.3
µ s (system clock operating at 4.19 MHz)
• 0.67, 1.33, 2.67, 10.7 µ s (system clock operating at 6.0 MHz)

18
µ PD754202, 754202(A)
Figure 6-1. Clock Generator Block Diagram
Note Instruction execution
Remarks 1. fX: System clock frequency
2. Φ= CPU clock
3. PCC: Processor Clock Control Register
4. One clock cycle (tCY) of the CPU clock is equal to one machine cycle of the instruction.
X1
X2
System
clock
oscillator
Oscillation stops
1/2 1/41/16
f
X
Divider
1/4 Φ
HALT F/F
S
R Q
S
R
Q
STOPF/F
PCC0
PCC1
PCC2
PCC3
PCC2,
PCC3
clear
HALT
Note
STOP
Note
Wait release signal from BT
Reset signal
Standby release signal from
interrupt control circuit
PCC
4
· Basic interval timer (BT)
· Timer counter
· INT0 noise eliminator
1/1 to 1/4096
· CPU
· INT0 noise
eliminator
Divider
Selector
Internal bus

19
µ PD754202, 754202(A)
6.3 Basic Interval Timer/Watchdog Timer
The basic interval timer/watchdog timer has the following functions.
(a) Interval timer operation to generate a reference time interrupt
(b) Watchdog timer operation to detect a runaway of program and reset the CPU
(c) Selects and counts the wait time when the standby mode is released
(d) Reads the contents of counting
Figure 6-2. Basic Interval Timer/Watchdog Timer Block Diagram
Note Instruction execution
From clock
generator
fX/25
fX/27
fX/29
fX/212
MPX
BTM3 BTM2 BTM1 BTM0 BTM
4
SET1Note
Internal bus
81
Basic interval timer
(8-bit frequency divider)
Clear
BT
Wait release signal
when standby is
released.
Set
Clear
3
WDTM SET1Note
Internal reset
signal
Vectored
interrupt
request signal
BT
interrupt
request flag
IRQBT

20
µ PD754202, 754202(A)
6.4 Timer Counter
The µ PD754202 incorporates three timer counters. Its configuration is shown in Figures 6-3, 6-4, and 6-5. The
timer counter functions are shown below.
(a) Programmable interval timer operation
(b) Square wave output of any frequency to PTO0-PTO2 pins
(c) Count value read function
The timer counter can operate in the following four modes as set by the mode register.
Table 6-2. Mode List
Mode Channel
Channel 0 Channel 1 Channel 2 TM11 TM10 TM21 TM20
8-bit timer counter mode 0000
PWM pulse generator mode ×× 0001
16-bit timer counter mode ×1010
Carrier generator mode ×0011
Remark : Available
×: Not available