NEC mPD780208 Subseries User manual

µ PD780208 Subseries
8-Bit Single-Chip Microcontrollers
µ PD780204
µ PD780204A
µ PD780205
µ PD780205A
µ PD780206
µ PD780208
µ PD78P0208
Document No. U11302EJ4V0UM00 (4th edition)
Date Published July 2003 N CP(K)
Printed in Japan
User’s Manual
c

2User’s Manual U11302EJ4V0UM
[MEMO]

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User’s Manual U11302EJ4V0UM
FIP and IEBus are trademarks of NEC Electronics Corporation.
MS-DOS, Windows, and Windows NT are either registered trademarks or trademarks of Microsoft Corporation
in the United States and/or other countries.
IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
TRON stands for The Realtime Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.

4User’s Manual U11302EJ4V0UM
The information in this document is current as of January, 2003. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
•
•
•
•
•
•
M8E 02. 11-1
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.

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User’s Manual U11302EJ4V0UM
Regional Information
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html
NEC Electronics America, Inc. (U.S.)
Santa Clara, California
Tel: [phone]
800-366-9782
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: [phone]
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: [phone]
NEC Electronics Shanghai, Ltd.
Shanghai, P.R. China
Tel: [phone]
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: [phone]
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: [phone]
J03.4
N EC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: [phone]
•Sucursal en España
Madrid, Spain
Tel: [phone]
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Tel: [phone]
•Succursale Française
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Tel: [phone]
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Tel: [phone]
•Tyskland Filial
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Tel: [phone]
•United Kingdom Branch
Milton Keynes, UK
Tel: [phone]
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:

6User’s Manual U11302EJ4V0UM
Major Revisions in This Edition
Page Description
Throughout Addition of the following products to target products
•
µ PD780204A
• µ PD780205A
Deletion of the following package from target products
• µ PD78P0208KL-T (100-pin ceramic WQFN)
CHAPTER 1 OUTLINE
p.29 • Update of 1.6 78K/0 Series Lineup
p.32 • Addition of Note in 1.8 Overview of Functions
p.33 • Addition of Caution in Table 1-1 Mask Options in Mask ROM Versions
CHAPTER 2 PIN FUNCTIONS
p.42 • Addition of 2.2.12 VLOAD
p.43 • Modification of Table 2-1 Types of Pin I/O Circuits
CHAPTER 3 CPU ARCHITECTURE
p.48 • Addition of Caution in 3.1 Memory Space
p.67 • Modification of Note in Table 3-3 Special-Function Register List
CHAPTER 4 PORT FUNCTIONS
p.90 • Addition of Caution in 4.2.6 Port 8
p.91 • Addition of Caution in 4.2.7 Port 9
p.92 • Addition of Caution in 4.2.8 Port 10
p.93 • Addition of Caution in 4.2.9 Port 11
p.94 • Addition of Caution in 4.2.10 Port 12
CHAPTER 5 CLOCK GENERATOR
p.103 • Addition of Note in Figure 5-3 Format of Processor Clock Control Register
CHAPTER 6 16-BIT TIMER/EVENT COUNTER
p.133 • Modification of Caution in Figure 6-8 Format of External Interrupt Mode Register
p.144 • Modification of 6.6 (5) Valid edge setting
CHAPTER 8 WATCH TIMER
p.171 • Modification of Caution in Figure 8-2 Format of Timer Clock Select Register 2
CHAPTER 9 WATCHDOG TIMER
p.178 • Modification of Caution in Figure 9-2 Format of Timer Clock Select Register 2
CHAPTER 11 BUZZER OUTPUT CONTROLLER
p.188 • Modification of Caution in Figure 11-2 Format of Timer Clock Select Register 2
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS
p.340 • Addition of Caution in Figure 16-2 Format of Interrupt Request Flag Register
p.343 • Modification of Caution in Figure 16-5 Format of External Interrupt Mode Register
CHAPTER 17 STANDBY FUNCTION
p.361 • Addition of description in Table 17-1 HALT Mode Operating Status
p.364 • Addition of description in Table 17-3 STOP Mode Operating Status
CHAPTER 19 µ PD78P0208
p.373 • Modification of Table 19-2 Internal Memory Size Switching Register Setting Values
APPENDIX A DIFFERENCES BETWEEN µ PD78044H, 780228, AND 780208 SUBSERIES
p.398 • Modification of description in Table A-1 Major Differences Between µ PD78044H, 780228, and
780208 Subseries
APPENDIX B DEVELOPMENT TOOLS
p.399 • Modification of description
The mark shows major revised points.

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User’s Manual U11302EJ4V0UM
INTRODUCTION
Readers This manual has been prepared for user engineers who wish to understand the functions of the
µ PD780208 Subseries and design and develop its application systems and programs.
Purpose This manual is intended to give users an understanding of the functions described in the Organization
below.
Organization The
µ PD780208 Subseries manual consists of two parts: this manual and Instructions (common to
the 78K/0 Series)
µ PD780208 Subseries 78K/0 Series
User’s Manual Instructions
(This manual) User’s Manual
• Pin functions • CPU functions
• Internal block functions • Instruction set
• Interrupts • Explanation of each instruction
• Other on-chip peripheral functions
How to Read This Manual
It is assumed that the reader of this manual has general knowledge in the fields of electrical
engineering, logic circuits, and microcontrollers.
•For an understanding of functions in general:
→ Read this manual in the order of the CONTENTS.
•For how to interpret the register format:
→ For a bit number enclosed in angle brackets, the bit name is defined as a reserved word in the
RA78K0, and is defined in the header file named sfrbit.h in the CC78K0.
•To confirm the details of a register whose register name is known:
→Refer to APPENDIX C REGISTER INDEX.
•For the details of
µ PD780208 Subseries instruction functions:
→Refer to 78K/0 Series Instructions User’s Manual (U12326E).
•For the electrical specifications of the µ PD780208 Subseries:
→Refer to the separate
µ PD780204, 780205, 780206, 780208 Data Sheet (U10436E) and
µ PD78P0208 Data Sheet (U11295E).
•For application examples of the µ PD780208 Subseries:
→Refer to the separate 78K/0 Series Basics (II) Application Note (U10121E).
Conventions Data significance: Higher digits on the left and lower digits on the right
Active low representation: xxx (overscore over pin or signal name)
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numerical representation: Binary .................. xxxx or xxxxB
Decimal ............... xxxx
Hexadecimal ....... xxxxH

8User’s Manual U11302EJ4V0UM
Related Documents
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name Document No.
µ PD780204, 780205, 780206, 780208 Data Sheet U10436E
µ PD78P0208 Data Sheet U11295E
µ PD780208 Subseries User’s Manual This manual
78K/0 Series Instructions User’s Manual U12326E
78K/0 Series Basic (II) Application Note U10121E
Documents Related to Software Development Tools (User’s Manuals)
Document Name Document No.
RA78K0 Assembler Package Operation U14445E
Language U14446E
Structured Assembly Language U11789E
CC78K0 C Compiler Operation U14297E
Language U14298E
SM78K Series System Simulator Ver. 2.30 or Later Operation (WindowsTM Based) U15373E
External Part User Open Interface Specification U15802E
ID78K Series Integrated Debugger Ver. 2.30 or Later Operation (Windows Based) U15185E
RX78K0 Real-Time OS Fundamentals U11537E
Installation U11536E
Project Manager Ver. 3.12 or Later (Windows Based) U14610E
Documents Related to Hardware Development Tools (User’s Manuals)
Document Name Document No.
IE-78K0-NS In-Circuit Emulator U13731E
IE-78K0-NS-A In-Circuit Emulator U14889E
IE-780208-NS-EM1 Emulation Board U13691E
IE-78001-R-A In-Circuit Emulator U14142E
IE-780208-R-EM Emulation Board EEU-1501
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.

9
User’s Manual U11302EJ4V0UM
Documents Related to PROM Writing (User’s Manuals)
Document Name Document No.
PG-1500 PROM Programmer U11940E
PG-1500 Controller PC-9800 Series (MS-DOSTM Based) EEU-1291
IBM PC Series (PC DOSTM Based) U10540E
Other Related Documents
Document Name Document No.
SEMICONDUCTOR SELECTION GUIDE - Products and Packages - X13769X
Semiconductor Device Mount Manual Note
Quality Grades on NEC Semiconductor Devices C11531E
NEC Semiconductor Device Reliability/Quality Control System C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E
Note See the “Semiconductor Device Mount Manual”website (http://www.necel.com/pkg/en/mount/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.

10 User’s Manual U11302EJ4V0UM
CONTENTS
CHAPTER 1 OUTLINE ......................................................................................................................... 24
1.1 Features ............................................................................................................................... 24
1.2 Applications ......................................................................................................................... 25
1.3 Ordering Information .......................................................................................................... 25
1.4 Quality Grade ...................................................................................................................... 25
1.5 Pin Configuration (Top View)............................................................................................ 26
1.6 78K/0 Series Lineup ........................................................................................................... 29
1.7 Block Diagram ..................................................................................................................... 31
1.8 Overview of Functions ....................................................................................................... 32
1.9 Mask Options ...................................................................................................................... 33
CHAPTER 2 PIN FUNCTIONS .............................................................................................................. 34
2.1 Pin Function List................................................................................................................. 34
2.1.1 Normal operating mode pins .................................................................................................. 34
2.1.2 PROM programming mode pins (
µ PD78P0208 only) ........................................................... 37
2.2 Description of Pin Functions ............................................................................................ 38
2.2.1 P00 to P04 (Port 0) ................................................................................................................. 38
2.2.2 P10 to P17 (Port 1) ................................................................................................................. 38
2.2.3 P20 to P27 (Port 2) ................................................................................................................. 39
2.2.4 P30 to P37 (Port 3) ................................................................................................................. 39
2.2.5 P70 to P74 (Port 7) ................................................................................................................. 40
2.2.6 P80 to P87 (Port 8) ................................................................................................................. 40
2.2.7 P90 to P97 (Port 9) ................................................................................................................. 40
2.2.8 P100 to P107 (Port 10) ........................................................................................................... 41
2.2.9 P110 to P117 (Port 11) ........................................................................................................... 41
2.2.10 P120 to P127 (Port 12) ........................................................................................................... 41
2.2.11 FIP0 to FIP12 .......................................................................................................................... 41
2.2.12 VLOAD ........................................................................................................................................ 42
2.2.13 AVREF ....................................................................................................................................... 42
2.2.14 AVDD ......................................................................................................................................... 42
2.2.15 AVSS ......................................................................................................................................... 42
2.2.16 RESET ..................................................................................................................................... 42
2.2.17 X1 and X2 ................................................................................................................................42
2.2.18 XT1 and XT2 ........................................................................................................................... 42
2.2.19 VDD ........................................................................................................................................... 42
2.2.20 VSS ............................................................................................................................................ 42
2.2.21 VPP ( µ PD78P0208 only) .......................................................................................................... 42
2.2.22 IC (mask ROM version only) .................................................................................................. 42
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ............................... 43
CHAPTER 3 CPU ARCHITECTURE ....................................................................................................48
3.1 Memory Space ..................................................................................................................... 48
3.1.1 Internal program memory space ............................................................................................ 53
3.1.2 Internal data memory space ................................................................................................... 54
3.1.3 Special-function register (SFR) area ...................................................................................... 54

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User’s Manual U11302EJ4V0UM
3.1.4 Data memory addressing ........................................................................................................ 55
3.2 Processor Registers ........................................................................................................... 60
3.2.1 Control registers ...................................................................................................................... 60
3.2.2 General-purpose registers ...................................................................................................... 63
3.2.3 Special-function registers (SFRs)........................................................................................... 64
3.3 Instruction Address Addressing ...................................................................................... 68
3.3.1 Relative addressing................................................................................................................. 68
3.3.2 Immediate addressing ............................................................................................................. 69
3.3.3 Table indirect addressing........................................................................................................ 70
3.3.4 Register addressing ................................................................................................................ 71
3.4 Operand Address Addressing .......................................................................................... 72
3.4.1 Implied addressing .................................................................................................................. 72
3.4.2 Register addressing ................................................................................................................ 73
3.4.3 Direct addressing .................................................................................................................... 74
3.4.4 Short direct addressing ........................................................................................................... 75
3.4.5 Special-function register (SFR) addressing ........................................................................... 76
3.4.6 Register indirect addressing ................................................................................................... 77
3.4.7 Based addressing.................................................................................................................... 78
3.4.8 Based indexed addressing ..................................................................................................... 79
3.4.9 Stack addressing ..................................................................................................................... 79
CHAPTER 4 PORT FUNCTIONS ......................................................................................................... 80
4.1 Port Functions..................................................................................................................... 80
4.2 Port Configuration .............................................................................................................. 83
4.2.1 Port 0 ....................................................................................................................................... 83
4.2.2 Port 1 ....................................................................................................................................... 85
4.2.3 Port 2 ....................................................................................................................................... 86
4.2.4 Port 3 ....................................................................................................................................... 88
4.2.5 Port 7 ....................................................................................................................................... 89
4.2.6 Port 8 ....................................................................................................................................... 90
4.2.7 Port 9 ....................................................................................................................................... 91
4.2.8 Port 10 ..................................................................................................................................... 92
4.2.9 Port 11 ..................................................................................................................................... 93
4.2.10 Port 12 ..................................................................................................................................... 94
4.3 Port Function Control Registers ...................................................................................... 95
4.4 Port Function Operations .................................................................................................. 98
4.4.1 Writing to I/O port .................................................................................................................... 98
4.4.2 Reading from I/O port ............................................................................................................. 98
4.4.3 Operations on I/O port ............................................................................................................ 98
4.5 Selection of Mask Option .................................................................................................. 99
CHAPTER 5 CLOCK GENERATOR .................................................................................................... 100
5.1 Clock Generator Functions ............................................................................................... 100
5.2 Clock Generator Configuration......................................................................................... 100
5.3 Clock Generator Control Registers.................................................................................. 102
5.4 System Clock Oscillator .................................................................................................... 109
5.4.1 Main system clock oscillator ................................................................................................... 109
5.4.2 Subsystem clock oscillator ..................................................................................................... 110

12 User’s Manual U11302EJ4V0UM
5.4.3 Divider ...................................................................................................................................... 113
5.4.4 When subsystem clock is not used ........................................................................................ 113
5.5 Clock Generator Operations ............................................................................................. 114
5.5.1 Main system clock operations ................................................................................................ 115
5.5.2 Subsystem clock operations ................................................................................................... 116
5.6 Changing System Clock and CPU Clock Settings......................................................... 117
5.6.1 Time required for switchover between system clock and CPU clock .................................. 117
5.6.2 System clock and CPU clock switching procedure ............................................................... 118
CHAPTER 6 16-BIT TIMER/EVENT COUNTER ................................................................................... 119
6.1 Outline of Timers Incorporated in µ PD780208 Subseries ............................................ 119
6.2 16-Bit Timer/Event Counter Functions ............................................................................ 120
6.3 16-Bit Timer/Event Counter Configuration ..................................................................... 122
6.4 16-Bit Timer/Event Counter Control Registers .............................................................. 127
6.5 16-Bit Timer/Event Counter Operations .......................................................................... 135
6.5.1 Interval timer operations ......................................................................................................... 135
6.5.2 PWM output operations .......................................................................................................... 137
6.5.3 Pulse width measurement operations .................................................................................... 138
6.5.4 External event counter operation ........................................................................................... 140
6.5.5 Square-wave output operation ............................................................................................... 142
6.6 16-Bit Timer/Event Counter Operating Precautions ...................................................... 143
CHAPTER 7 8-BIT TIMER/EVENT COUNTER .................................................................................... 145
7.1 8-Bit Timer/Event Counter Functions .............................................................................. 145
7.1.1 8-bit timer/event counter mode............................................................................................... 145
7.1.2 16-bit timer/event counter mode ............................................................................................ 148
7.2 8-Bit Timer/Event Counter Configuration ....................................................................... 150
7.3 8-Bit Timer/Event Counter Control Registers................................................................. 153
7.4 8-Bit Timer/Event Counter Operations ............................................................................ 158
7.4.1 8-bit timer/event counter mode............................................................................................... 158
7.4.2 16-bit timer/event counter mode ............................................................................................ 162
7.5 8-Bit Timer/Event Counter Operating Precautions ........................................................ 166
CHAPTER 8 WATCH TIMER ............................................................................................................... 168
8.1 Watch Timer Functions ...................................................................................................... 168
8.2 Watch Timer Configuration ............................................................................................... 169
8.3 Watch Timer Control Registers ........................................................................................ 169
8.4 Watch Timer Operations .................................................................................................... 173
8.4.1 Watch timer operation ............................................................................................................. 173
8.4.2 Interval timer operation ........................................................................................................... 173
CHAPTER 9 WATCHDOG TIMER ....................................................................................................... 174
9.1 Watchdog Timer Functions ............................................................................................... 174
9.2 Watchdog Timer Configuration ........................................................................................ 175
9.3 Watchdog Timer Control Registers ................................................................................. 177
9.4 Watchdog Timer Operations ............................................................................................. 180
9.4.1 Watchdog timer operation....................................................................................................... 180
9.4.2 Interval timer operation ........................................................................................................... 181

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User’s Manual U11302EJ4V0UM
CHAPTER 10 CLOCK OUTPUT CONTROLLER ................................................................................. 182
10.1 Clock Output Controller Functions .................................................................................. 182
10.2 Clock Output Controller Configuration ........................................................................... 183
10.3 Clock Output Function Control Registers ...................................................................... 183
CHAPTER 11 BUZZER OUTPUT CONTROLLER .............................................................................. 186
11.1 Buzzer Output Controller Functions ................................................................................ 186
11.2 Buzzer Output Controller Configuration ......................................................................... 186
11.3 Buzzer Output Function Control Registers .................................................................... 187
CHAPTER 12 A/D CONVERTER ......................................................................................................... 190
12.1 A/D Converter Functions ................................................................................................... 190
12.2 A/D Converter Configuration ............................................................................................ 190
12.3 A/D Converter Control Registers ..................................................................................... 194
12.4 A/D Converter Operations ................................................................................................. 197
12.4.1 Basic operations of A/D converter ......................................................................................... 197
12.4.2 Input voltage and conversion results ..................................................................................... 199
12.4.3 A/D converter operating mode ............................................................................................... 200
12.5 A/D Converter Precautions ............................................................................................... 202
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 ............................................................................... 205
13.1 Functions of Serial Interface Channel 0.......................................................................... 206
13.2 Configuration of Serial Interface Channel 0 ................................................................... 207
13.3 Control Registers of Serial Interface Channel 0 ............................................................ 211
13.4 Operations of Serial Interface Channel 0 ........................................................................ 217
13.4.1 Operation stop mode .............................................................................................................. 217
13.4.2 3-wire serial I/O mode operation ............................................................................................ 218
13.4.3 SBI mode operation ................................................................................................................ 223
13.4.4 2-wire serial I/O mode operation ............................................................................................ 249
13.4.5 SCK0/P27 pin output manipulation ........................................................................................ 255
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 ............................................................................... 256
14.1 Functions of Serial Interface Channel 1.......................................................................... 256
14.2 Configuration of Serial Interface Channel 1 ................................................................... 257
14.3 Control Registers of Serial Interface Channel 1 ............................................................ 260
14.4 Operations of Serial Interface Channel 1 ........................................................................ 268
14.4.1 Operation stop mode .............................................................................................................. 268
14.4.2 3-wire serial I/O mode operation ............................................................................................ 269
14.4.3 3-wire serial I/O mode operation with automatic transmit/receive function ......................... 272
CHAPTER 15 VFD CONTROLLER/DRIVER ........................................................................................ 299
15.1 VFD Controller/Driver Functions ...................................................................................... 299
15.2 VFD Controller/Driver Configuration ............................................................................... 301
15.3 VFD Controller/Driver Control Registers ........................................................................ 303
15.3.1 Control registers ...................................................................................................................... 303
15.3.2 One-display period and cut width ........................................................................................... 310
15.4 Selecting Display Mode ..................................................................................................... 311
15.5 Display Mode and Display Output.................................................................................... 312
15.6 Display Data Memory ......................................................................................................... 313

14 User’s Manual U11302EJ4V0UM
15.7 Key Scan Flag and Key Scan Data .................................................................................. 314
15.7.1 Key scan flag ........................................................................................................................... 314
15.7.2 Key scan data.......................................................................................................................... 314
15.8 Light Leakage of VFD......................................................................................................... 315
15.9 Display Examples ............................................................................................................... 317
15.9.1 Segment type (display mode 1: DSPM05 = 0) ...................................................................... 318
15.9.2 Dot type (display mode 1: DSPM05 = 0) ............................................................................... 320
15.9.3 Display type in which a segment spans two or more grids
(display mode 2: DSPM05 = 1) .............................................................................................. 322
15.10 Calculating Total Power Dissipation............................................................................... 326
15.10.1 Segment type (display mode 1: DSPM05 = 0) ...................................................................... 326
15.10.2 Dot type (display mode 1: DSPM05 = 0) ............................................................................... 329
15.10.3 Display type in which a segment spans two or more grids
(display mode 2: DSPM05 = 1) .............................................................................................. 332
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS .......................................................................... 335
16.1 Interrupt Function Types ................................................................................................... 335
16.2 Interrupt Sources and Configuration............................................................................... 336
16.3 Interrupt Function Control Registers .............................................................................. 339
16.4 Interrupt Servicing Operations ......................................................................................... 347
16.4.1 Non-maskable interrupt request acknowledgment operation................................................ 347
16.4.2 Maskable interrupt request acknowledgment operation........................................................ 350
16.4.3 Software interrupt request acknowledgment operation ......................................................... 352
16.4.4 Multiple interrupt servicing ...................................................................................................... 353
16.4.5 Interrupt request hold .............................................................................................................. 356
16.5 Test Functions .................................................................................................................... 357
16.5.1 Test function control registers ................................................................................................ 357
16.5.2 Test input signal acknowledgment operation ........................................................................ 358
CHAPTER 17 STANDBY FUNCTION ................................................................................................... 359
17.1 Standby Function and Configuration .............................................................................. 359
17.1.1 Standby function...................................................................................................................... 359
17.1.2 Standby function control register............................................................................................ 360
17.2 Standby Function Operations ........................................................................................... 361
17.2.1 HALT mode ............................................................................................................................. 361
17.2.2 STOP mode ............................................................................................................................. 364
CHAPTER 18 RESET FUNCTION ........................................................................................................ 367
18.1 Reset Function .................................................................................................................... 367
CHAPTER 19 µ PD78P0208 .................................................................................................................. 371
19.1 Internal Memory Size Switching Register ....................................................................... 372
19.2 Internal Expansion RAM Size Switching Register ......................................................... 374
19.3 PROM Programming ........................................................................................................... 375
19.3.1 Operating modes ..................................................................................................................... 375
19.3.2 PROM write procedure ........................................................................................................... 377
19.3.3 PROM read procedure ............................................................................................................ 381
19.4 Screening of One-Time PROM Version ........................................................................... 382

15
User’s Manual U11302EJ4V0UM
CHAPTER 20 INSTRUCTION SET ....................................................................................................... 383
20.1 Conventions ........................................................................................................................ 384
20.1.1 Operand identifiers and description methods ........................................................................ 384
20.1.2 Description of “operation” column .......................................................................................... 385
20.1.3 Description of “flag operation” column ................................................................................... 385
20.2 Operation List...................................................................................................................... 386
20.3 Instructions Listed by Addressing Type ......................................................................... 394
APPENDIX A DIFFERENCES BETWEEN µ PD78044H, 780228, AND 780208 SUBSERIES ............ 398
APPENDIX B DEVELOPMENT TOOLS .............................................................................................. 399
B.1 Software Package ............................................................................................................... 401
B.2 Language Processing Software........................................................................................ 401
B.3 Control Software ................................................................................................................. 402
B.4 PROM Programming Tools ................................................................................................ 403
B.4.1 Hardware ................................................................................................................................. 403
B.4.2 Software ................................................................................................................................... 403
B.5 Debugging Tools (Hardware) ............................................................................................ 404
B.5.1 When using in-circuit emulator IE-78K0-NS, IE-78K0-NS-A ................................................ 404
B.5.2 When using in-circuit emulator IE-78001-R-A ....................................................................... 405
B.6 Debugging Tools (Software) ............................................................................................. 406
B.7 Embedded Software ........................................................................................................... 407
B.8 Method for Upgrading from Former In-Circuit Emulator for 78K/0 Series to
IE-78001-R-A ........................................................................................................................ 408
B.9 Conversion Socket (EV-9200GF-100) Package Drawing and Recommended
Footprint............................................................................................................................... 409
B.10 Notes on Target System Design....................................................................................... 411
APPENDIX C REGISTER INDEX ......................................................................................................... 413
C.1 Register Index (by Register Name) .................................................................................. 413
C.2 Register Index (by Register Symbol) ............................................................................... 415
APPENDIX D REVISION HISTORY .......................................................................................................417

16 User’s Manual U11302EJ4V0UM
LIST OF FIGURES (1/6)
Figure No. Title Page
2-1 Pin I/O Circuits ................................................................................................................................45
3-1 Memory Map (
µ PD780204 and µ PD780204A) .............................................................................. 48
3-2 Memory Map (
µ PD780205 and µ PD780205A) .............................................................................. 49
3-3 Memory Map (
µ PD780206)............................................................................................................. 50
3-4 Memory Map (
µ PD780208)............................................................................................................. 51
3-5 Memory Map (
µ PD78P0208) .......................................................................................................... 52
3-6 Data Memory Addressing (
µ PD780204 and µ PD780204A) .......................................................... 55
3-7 Data Memory Addressing (
µ PD780205 and µ PD780205A) .......................................................... 56
3-8 Data Memory Addressing (
µ PD780206) ........................................................................................ 57
3-9 Data Memory Addressing (
µ PD780208) ........................................................................................ 58
3-10 Data Memory Addressing ( µ PD78P0208) ...................................................................................... 59
3-11 Program Counter Format ................................................................................................................ 60
3-12 Program Status Word Format ......................................................................................................... 60
3-13 Stack Pointer Format ...................................................................................................................... 61
3-14 Data to Be Saved to Stack Memory ............................................................................................... 62
3-15 Data to Be Reset from Stack Memory ........................................................................................... 62
3-16 General-Purpose Register Configuration ....................................................................................... 63
4-1 Port Types ....................................................................................................................................... 80
4-2 Block Diagram of P00 and P04 ...................................................................................................... 84
4-3 Block Diagram of P01 to P03 ......................................................................................................... 84
4-4 Block Diagram of P10 to P17 ......................................................................................................... 85
4-5 Block Diagram of P20, P21, P23 to P26........................................................................................ 86
4-6 Block Diagram of P22 and P27 ...................................................................................................... 87
4-7 Block Diagram of P30 to P37 ......................................................................................................... 88
4-8 Block Diagram of P70 to P74 ......................................................................................................... 89
4-9 Block Diagram of P80 to P87 ......................................................................................................... 90
4-10 Block Diagram of P90 to P97 ......................................................................................................... 91
4-11 Block Diagram of P100 to P107 ..................................................................................................... 92
4-12 Block Diagram of P110 to P117 ..................................................................................................... 93
4-13 Block Diagram of P120 to P127 ..................................................................................................... 94
4-14 Format of Port Mode Register ........................................................................................................ 96
4-15 Format of Pull-up Resistor Option Register ................................................................................... 97
5-1 Clock Generater Block Diagram ..................................................................................................... 101
5-2 Feedback Resistor of Subsystem Clock ........................................................................................ 102
5-3 Format of Processor Clock Control Register ................................................................................. 103
5-4 Format of Display Mode Register 0 ............................................................................................... 105
5-5 Format of Display Mode Register 1 ............................................................................................... 108
5-6 External Circuit of Main System Clock Oscillator .......................................................................... 109
5-7 External Circuit of Subsystem Clock Oscillator ............................................................................. 110
5-8 Examples of Incorrect Resonator Connection ............................................................................... 111
5-9 Main System Clock Stop Function ................................................................................................. 115
5-10 System Clock and CPU Clock Switching ....................................................................................... 118

17
User’s Manual U11302EJ4V0UM
LIST OF FIGURES (2/6)
Figure No. Title Page
6-1 Block Diagram of 16-Bit Timer/Event Counter (Timer Mode) ....................................................... 123
6-2 Block Diagram of 16-Bit Timer/Event Counter (PWM Mode)........................................................ 124
6-3 Block Diagram of 16-Bit Timer/Event Counter Output Controller ................................................. 125
6-4 Format of Timer Clock Select Register 0....................................................................................... 128
6-5 Format of 16-Bit Timer Mode Control Register ............................................................................. 130
6-6 Format of 16-Bit Timer Output Control Register ........................................................................... 131
6-7 Format of Port Mode Register 3 ..................................................................................................... 132
6-8 Format of External Interrupt Mode Register .................................................................................. 133
6-9 Format of Sampling Clock Select Register .................................................................................... 134
6-10 Interval Timer Configuration Diagram ............................................................................................ 135
6-11 Interval Timer Operation Timing ..................................................................................................... 136
6-12 Example of D/A Converter Configuration with PWM Output......................................................... 137
6-13 TV Tuner Application Circuit Example ........................................................................................... 138
6-14 Configuration Diagram for Pulse Width Measurement in Free-Running Mode............................ 139
6-15 Timing of Pulse Width Measurement Operation in Free-Running Mode
(with Both Edges Specified) ........................................................................................................... 139
6-16 Timing of Pulse Width Measurement Operation by Means of Restart
(with Both Edges Specified) ........................................................................................................... 140
6-17 External Event Counter Configuration Diagram ............................................................................ 141
6-18 External Event Counter Operation Timing (with Rising Edge Specified) ..................................... 141
6-19 Square-Wave Output Operation Timing ......................................................................................... 142
6-20 16-Bit Timer Register Start Timing ................................................................................................. 143
6-21 Timing After Compare Register Change During Timer Count Operation..................................... 143
6-22 Capture Register Data Retention Timing ....................................................................................... 144
7-1 Block Diagram of 8-Bit Timer/Event Counter................................................................................. 151
7-2 Block Diagram of 8-Bit Timer/Event Counter Output Controller 1 ................................................ 152
7-3 Block Diagram of 8-Bit Timer/Event Counter Output Controller 2 ................................................ 152
7-4 Format of Timer Clock Select Register 1....................................................................................... 154
7-5 Format of 8-Bit Timer Mode Control Register ............................................................................... 155
7-6 Format of 8-Bit Timer Output Control Register.............................................................................. 156
7-7 Format of Port Mode Register 3 ..................................................................................................... 157
7-8 Interval Timer Operation Timing ..................................................................................................... 158
7-9 External Event Counter Operation Timing (with Rising Edge Specified) ..................................... 160
7-10 Square-Wave Output Operation Timing ......................................................................................... 161
7-11 Interval Timer Operation Timing ..................................................................................................... 162
7-12 External Event Counter Operation Timing (with Rising Edge Specified) ..................................... 164
7-13 Square-Wave Output Operation Timing ......................................................................................... 165
7-14 8-Bit Timer Register Start Timing ................................................................................................... 166
7-15 External Event Counter Operation Timing ..................................................................................... 166
7-16 Timing After Compare Register Change During Timer Count Operation..................................... 167

18 User’s Manual U11302EJ4V0UM
LIST OF FIGURES (3/6)
Figure No. Title Page
8-1 Watch Timer Block Diagram ........................................................................................................... 170
8-2 Format of Timer Clock Select Register 2....................................................................................... 171
8-3 Format of Watch Timer Mode Control Register ............................................................................. 172
9-1 Watchdog Timer Block Diagram ..................................................................................................... 176
9-2 Format of Timer Clock Select Register 2....................................................................................... 178
9-3 Format of Watchdog Timer Mode Register .................................................................................... 179
10-1 Remote Controlled Output Application Example ........................................................................... 182
10-2 Clock Output Controller Block Diagram ......................................................................................... 183
10-3 Format of Timer Clock Select Register 0....................................................................................... 184
10-4 Format of Port Mode Register 3 ..................................................................................................... 185
11-1 Buzzer Output Controller Block Diagram ....................................................................................... 186
11-2 Format of Timer Clock Select Register 2....................................................................................... 188
11-3 Format of Port Mode Register 3 ..................................................................................................... 189
12-1 A/D Converter Block Diagram ........................................................................................................ 191
12-2 Format of A/D Converter Mode Register ....................................................................................... 195
12-3 Format of A/D Converter Input Select Register ............................................................................. 196
12-4 Basic Operation of A/D Converter .................................................................................................. 198
12-5 Relationship Between Analog Input Voltage and A/D Conversion Result ................................... 199
12-6 A/D Conversion by Hardware Start ................................................................................................ 200
12-7 A/D Conversion by Software Start ................................................................................................. 201
12-8 Example of Method of Reducing Power Consumption in Standby Mode .................................... 202
12-9 Analog Input Pin Processing .......................................................................................................... 203
12-10 A/D Conversion End Interrupt Request Generation Timing .......................................................... 204
12-11 AVDD Pin Connection ....................................................................................................................... 204
13-1 Block Diagram of Serial Interface Channel 0 ................................................................................ 208
13-2 Format of Timer Clock Select Register 3....................................................................................... 212
13-3 Format of Serial Operating Mode Register 0 ................................................................................. 213
13-4 Format of Serial Bus Interface Control Register ........................................................................... 214
13-5 Format of Interrupt Timing Specification Register ......................................................................... 216
13-6 3-Wire Serial I/O Mode Timing ....................................................................................................... 221
13-7 RELT and CMDT Operations .......................................................................................................... 222
13-8 Circuit for Switching Transfer Bit Order ......................................................................................... 222
13-9 Example of Serial Bus Configuration with SBI .............................................................................. 224
13-10 SBI Transfer Timing ........................................................................................................................ 226
13-11 Bus Release Signal ......................................................................................................................... 227
13-12 Command Signal ............................................................................................................................. 227
13-13 Address ............................................................................................................................................ 228
13-14 Slave Selection by Address ............................................................................................................ 228
13-15 Commands ....................................................................................................................................... 229

19
User’s Manual U11302EJ4V0UM
LIST OF FIGURES (4/6)
Figure No. Title Page
13-16 Data .................................................................................................................................................. 229
13-17 Acknowledge Signal ........................................................................................................................ 230
13-18 BUSY and READY Signals ............................................................................................................. 231
13-19 RELT, CMDT, RELD, and CMDD Operations (Master) ................................................................ 236
13-20 RELD and CMDD Operations (Slave) ............................................................................................ 236
13-21 ACKT Operation .............................................................................................................................. 237
13-22 ACKE Operations ............................................................................................................................ 238
13-23 ACKD Operations ............................................................................................................................ 239
13-24 BSYE Operation .............................................................................................................................. 239
13-25 Pin Configuration ............................................................................................................................. 242
13-26 Address Transmission from Master Device to Slave Device (WUP = 1) ..................................... 244
13-27 Command Transmission from Master Device to Slave Device .................................................... 245
13-28 Data Transmission from Master Device to Slave Device.............................................................. 246
13-29 Data Transmission from Slave Device to Master Device.............................................................. 247
13-30 Serial Bus Configuration Example Using 2-Wire Serial I/O Mode................................................ 249
13-31 2-Wire Serial I/O Mode Timing ....................................................................................................... 253
13-32 RELT and CMDT Operations .......................................................................................................... 254
13-33 SCK0/P27 Pin Configuration .......................................................................................................... 255
14-1 Block Diagram of Serial Interface Channel 1 ................................................................................ 258
14-2 Format of Timer Clock Select Register 3....................................................................................... 261
14-3 Format of Serial Operating Mode Register 1 ................................................................................. 262
14-4 Format of Automatic Data Transmit/Receive Control Register ..................................................... 264
14-5 Format of Automatic Data Transmit/Receive Interval Specification Register .............................. 265
14-6 3-Wire Serial I/O Mode Timing ....................................................................................................... 270
14-7 Circuit for Switching Transfer Bit Order ......................................................................................... 271
14-8 Basic Transmission/Reception Mode Operation Timing ............................................................... 279
14-9 Basic Transmission/Reception Mode Flowchart ............................................................................ 280
14-10 Buffer RAM Operation in 6-Byte Transmission/Reception
(in Basic Transmission/Reception Mode)....................................................................................... 281
14-11 Basic Transmission Mode Operation Timing ................................................................................. 283
14-12 Basic Transmission Mode Flowchart.............................................................................................. 284
14-13 Buffer RAM Operation in 6-Byte Transmission (in Basic Transmission Mode) ........................... 285
14-14 Repeat Transmission Mode Operation Timing .............................................................................. 287
14-15 Repeat Transmission Mode Flowchart ........................................................................................... 288
14-16 Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmission Mode) ........................ 289
14-17 Automatic Transmission/Reception Suspension and Restart ....................................................... 291
14-18 System Configuration with Busy Control Option ........................................................................... 292
14-19 Operation Timing When Using Busy Control Option (BUSY0 = 0) .............................................. 293
14-20 Busy Signal and Clearing Wait (BUSY0 = 0) ................................................................................ 293
14-21 Operation Timing When Using Busy & Strobe Control Option (BUSY0 = 0) ............................... 294
14-22 Operation Timing of Bit Slippage Detection Function Using Busy Signal (BUSY0 = 1) ............. 295
14-23 Automatic Transmit/Receive Interval .............................................................................................. 296
14-24 Operation Timing When Automatic Transmit/Receive Function Is Operating with
Internal Clock................................................................................................................................... 297

20 User’s Manual U11302EJ4V0UM
LIST OF FIGURES (5/6)
Figure No. Title Page
15-1 VFD Controller Operation Timing in Display Mode 1 (DSPM05 = 0) ........................................... 300
15-2 VFD Controller/Driver Block Diagram ............................................................................................ 302
15-3 Format of Display Mode Register 0 ............................................................................................... 305
15-4 Format of Display Mode Register 1 ............................................................................................... 307
15-5 Format of Display Mode Register 2 ............................................................................................... 308
15-6 Cut Width of Segment/Digit Signal ................................................................................................. 310
15-7 VFD Controller Display Start Timing .............................................................................................. 310
15-8 Selection of Display Mode .............................................................................................................. 311
15-9 Pin Configuration for 14-Segment Display ..................................................................................... 312
15-10 Relationship Between Display Data Memory Contents and Segment Output ............................. 313
15-11 Light Leakage due to Short Blanking Time.................................................................................... 315
15-12 Light Leakage due to CSG ............................................................................................................... 316
15-13 Waveform of Light Leakage due to CSG ......................................................................................... 316
15-14 Display Data Memory Configuration and Segment Data Reading Order
(Segment Type) ............................................................................................................................... 318
15-15 Relationship Between Display Data Memory Contents and Segment Outputs
in 10-Segment x 11-Digit Display Mode ........................................................................................ 319
15-16 Display Data Memory Configuration and Segment Data Reading Order (Dot Type) .................. 320
15-17 Relationship Between Display Data Memory Contents and Segment Outputs
in 35-Segment x 16-Digit Display Mode ........................................................................................ 321
15-18 Display Data Memory Configuration and Data Reading Order (Display Mode 2) ....................... 322
15-19 Segment Connection Example ....................................................................................................... 323
15-20 Grid Driving Timing ......................................................................................................................... 324
15-21 Data Memory Status in 23-Segment x 5-Grid Display Mode ........................................................ 325
15-22 Allowable Total Power Dissipation PT(TA= –40 to +85°C) .......................................................... 326
15-23 Relationship Between Display Data Memory Contents and Segment Outputs
in 10-Segment x 11-Digit Display Mode ........................................................................................ 328
15-24 Relationship Between Display Data Memory Contents and Segment Outputs
in 35-Segment x 16-Digit Display Mode ........................................................................................ 331
15-25 Grid Driving Timing ......................................................................................................................... 333
15-26 Data Memory Status in 23-Segment x 5-Grid Display Mode ........................................................ 334
16-1 Basic Configuration of Interrupt Function ...................................................................................... 337
16-2 Format of Interrupt Request Flag Register .................................................................................... 340
16-3 Format of Interrupt Mask Flag Register ......................................................................................... 341
16-4 Format of Priority Specification Flag Register ............................................................................... 342
16-5 Format of External Interrupt Mode Register .................................................................................. 343
16-6 Format of Sampling Clock Select Register .................................................................................... 344
16-7 Noise Eliminator I/O Timing (When Rising Edge Is Detected) ..................................................... 345
16-8 Format of Program Status Word .................................................................................................... 346
16-9 Non-Maskable Interrupt Request Acknowledgment Flowchart ..................................................... 348
16-10 Non-Maskable Interrupt Request Acknowledgment Timing .......................................................... 348
16-11 Non-Maskable Interrupt Request Acknowledgment Operation ..................................................... 349