NEC mPD780024AS Series User manual

µ PD780024AS, 780034AS Subseries
8-Bit Single-Chip Microcontrollers
µ PD780021AS
µ PD780022AS
µ PD780023AS
µ PD780024AS
µ PD780031AS
µ PD780032AS
µ PD780033AS
µ PD780034AS
µ PD78F0034BS
Document No. U16035EJ1V0UM00 (1st edition)
Date Published June 2002 N CP(K)
Preliminary User's Manual
Printed in Japan
©2002

2Preliminary User’s Manual U16035EJ1V0UM
[MEMO]

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Preliminary User’s Manual U16035EJ1V0UM
FIP, EEPROM, and IEBus are trademarks of NEC Corporation.
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
Ethernet is a trademark of Xerox Corporation.
OSF/Motif is a trademark of OpenSoftware Foundation, Inc.
TRON stands for The Realtime Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.

4Preliminary User’s Manual U16035EJ1V0UM
License not needed: µ PD78F0034BSGB-8ET
The customer must judge the need for a license for the following products:
µ PD780021ASGB-xxx-8ET, 780022ASGB-xxx-8ET, 780023ASGB-xxx-8ET, 780024ASGB-xxx-8ET,
780031ASGB-xxx-8ET, 780032ASGB-xxx-8ET, 780033ASGB-xxx-8ET, 780034ASGB-xxx-8ET
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
• The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
• Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M5D 98. 12

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Preliminary User’s Manual U16035EJ1V0UM
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: [phone]
800-366-9782
Fax: [phone]
800-729-9288
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: [phone]
Fax: [phone]
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: [phone]
Fax: [phone]
NEC Electronics Shanghai, Ltd.
Shanghai, P.R. China
Tel: [phone]
Fax: [phone]
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: [phone]
Fax: [phone]
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: [phone]
Fax: [phone]
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP, Brasil
Tel: [phone]
Fax: [phone]
J02.4
NEC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: [phone]
Fax: [phone]
• Sucursal en España
Madrid, Spain
Tel: [phone]
Fax: [phone]
Vélizy-Villacoublay, France
Tel: [phone]
Fax: [phone]
• Succursale Française
• Filiale Italiana
Milano, Italy
Tel: [phone]
Fax: [phone]
• Branch The Netherlands
Eindhoven, The Netherlands
Tel: [phone]
Fax: [phone]
• Branch Sweden
Taeby, Sweden
Tel: [phone]
Fax: [phone]
• United Kingdom Branch
Milton Keynes, UK
Tel: [phone]
Fax: [phone]

6Preliminary User’s Manual U16035EJ1V0UM
INTRODUCTION
Readers This manual has been prepared for user engineers who understand the functions of the
µ PD780024AS, 780034AS Subseries and wish to design and develop application
systems and programs for these devices.
µ PD780024AS Subseries: µ PD780021AS, 780022AS, 780023AS, 780024AS
µ PD780034AS Subseries: µ PD780031AS, 780032AS, 780033AS, 780034AS, 78F0034BS
Purpose This manual is intended to give users an understanding of the functions described in the
Organization below.
Organization The
µ PD780024AS, 780034AS Subseries manual is separated into two parts: this
manual and the instructions edition (common to the 78K/0 Series).
µ PD780024AS, 780034AS Subseries 78K/0 Series
User’s Manual User’s Manual
(This Manual) Instructions
• Pin functions • CPU functions
• Internal block functions • Instruction set
• Interrupt • Explanation of each instruction
• Other on-chip peripheral functions
How to Read This Manual It is assumed that the reader of this manual has general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
• To gain a general understanding of functions:
→Read this manual in the order of the Contents.
• How to interpret the register format:
→For the bit number enclosed in square, the bit name is defined as a reserved word
in RA78K0, and in CC78K0, already defined in the header file named sfrbit.h.
• To check the details of a register when you know the register name.
→Refer to APPENDIX D REGISTER INDEX.
Differences Between
µ PD780024AS and 780034AS Subseries
The resolution of the A/D converter differ between the µ PD780024AS and 780034AS Subseries products.
Subseries µ PD780024AS µ PD780034AS
Item
A/D converter 8-bit resolution 10-bit resolution

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Preliminary User’s Manual U16035EJ1V0UM
Conventions Data significance: Higher digits on the left and lower digits on the right
Active low representation: ××× (overscore over pin or signal name)
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numerical representation: Binary ··· ×××× or ××××B
Decimal ··· ××××
Hexadecimal ··· ××××H

8Preliminary User’s Manual U16035EJ1V0UM
Related Documents
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
Documents Related to Devices
Document Name Document No.
µ PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY Data Sheet U14042E
µ PD780021A(A), 780022A(A), 780023A(A), 780024A(A), 780021AY(A), 780022AY(A), 780023AY(A), U15131E
780024AY(A) Data Sheet
µ PD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY Data Sheet U14044E
µ PD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A), U15132E
780034AY(A) Data Sheet
µ PD78F0034A, 78F0034AY Data Sheet U14040E
78K/0 Series Instructions User’s Manual U12326E
78K/0 Series Basic (I) Application Note U12704E
Documents Related to Development Software Tools (User’s Manuals)
Document Name Document No.
RA78K0 Assembler Package Operation U14445E
Language U14446E
Structured Assembly Language U11789E
CC78K0 C Compiler Operation U14297E
Language U14298E
SM78K0S, SM78K0 System Simulator Ver. 2.10 or Later Operation U14611E
WindowsTM Based
SM78K Series System Simulator Ver. 2.10 or Later External Part User Open Interface Specifications U15006E
ID78K0-NS Integrated Debugger Ver. 2.00 or Later Operation U14379E
Windows Based
ID78K0 Integrated Debugger Windows Based Reference U11539E
Guide U11649E
RX78K0 Real-time OS Fundamentals U11537E
Installation U11536E
MX78K0 Embedded OS Windows Based Fundamental U12257E
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.

9
Preliminary User’s Manual U16035EJ1V0UM
Documents Related to Development Hardware Tools (User’s Manuals)
Document Name Document No.
IE-78K0-NS In-Circuit Emulator U13731E
IE-78K0-NS-A In-Circuit Emulator U14889E
IE-780034-NS-EM1 Emulation Board U14642E
Documents Related to Flash Memory Writing
Document Name Document No.
PG-FP3 Flash Memory Programmer User’s Manual U13502E
Other Related Documents
Document Name Document No.
SEMICONDUCTOR SELECTION GUIDE - Products & Packages - X13769E
Semiconductor Device Mounting Technology Manual C10535E
Quality Grades on NEC Semiconductor Devices C11531E
NEC Semiconductor Device Reliability/Quality Control System C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.

10 Preliminary User’s Manual U16035EJ1V0UM
CONTENTS
CHAPTER 1 OUTLINE ....................................................................................................................... 24
1.1 Features .................................................................................................................................... 24
1.2 Applications ............................................................................................................................. 25
1.3 Ordering Information ............................................................................................................... 25
1.4 Pin Configuration (Top View) ................................................................................................. 26
1.5 78K/0 Series Lineup................................................................................................................. 28
1.6 Block Diagram.......................................................................................................................... 30
1.7 Outline of Function .................................................................................................................. 31
CHAPTER 2 PIN FUNCTION ............................................................................................................ 33
2.1 Pin Function List ...................................................................................................................... 33
2.2 Description of Pin Functions .................................................................................................. 36
2.2.1 P00 to P03 (Port 0) ........................................................................................................................ 36
2.2.2 P10 to P13 (Port 1) ........................................................................................................................ 36
2.2.3 P20 to P25 (Port 2) ........................................................................................................................ 37
2.2.4 P34 to P36 (Port 3) ........................................................................................................................ 37
2.2.5 P40 to P47 (Port 4) ........................................................................................................................ 38
2.2.6 P50 to P57 (Port 5) ........................................................................................................................ 38
2.2.7 P70 to P75 (Port 7) ........................................................................................................................ 39
2.2.8 AVREF ............................................................................................................................................. 39
2.2.9 AVDD .............................................................................................................................................. 39
2.2.10 AVSS ............................................................................................................................................. 39
3.2.11 RESET ........................................................................................................................................ 39
2.2.12 X1 and X2 ................................................................................................................................... 40
2.2.13 XT1 and XT2 ............................................................................................................................... 40
2.2.14 VDD0 and VDD1 .............................................................................................................................. 40
2.2.15 VSS0 and VSS1 ............................................................................................................................... 40
2.2.16 VPP (flash memory versions only) ................................................................................................ 40
2.2.17 IC (mask ROM version only) ....................................................................................................... 40
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ....................................... 41
CHAPTER 3 CPU ARCHITECTURE ................................................................................................. 43
3.1 Memory Spaces ....................................................................................................................... 43
3.1.1 Internal program memory space ................................................................................................... 48
3.1.2 Internal data memory space .......................................................................................................... 49
3.1.3 Special function register (SFR) area ............................................................................................. 49
3.1.4 External memory space ................................................................................................................ 49
3.1.5 Data memory addressing .............................................................................................................. 50
3.2 Processor Registers ................................................................................................................ 55
3.2.1 Control registers ............................................................................................................................ 55
3.2.2 General-purpose registers ............................................................................................................ 58
3.2.3 Special function register (SFR) ..................................................................................................... 59

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Preliminary User’s Manual U16035EJ1V0UM
3.3 Instruction Address Addressing ............................................................................................ 62
3.3.1 Relative addressing ....................................................................................................................... 62
3.3.2 Immediate addressing ................................................................................................................... 63
3.3.3 Table indirect addressing ............................................................................................................... 64
3.3.4 Register addressing ...................................................................................................................... 64
3.4 Operand Address Addressing ................................................................................................ 65
3.4.1 Implied addressing ........................................................................................................................ 65
3.4.2 Register addressing ...................................................................................................................... 66
3.4.3 Direct addressing .......................................................................................................................... 67
3.4.4 Short direct addressing ................................................................................................................. 68
3.4.5 Special function register (SFR) addressing ................................................................................... 69
3.4.6 Register indirect addressing .......................................................................................................... 70
3.4.7 Based addressing ......................................................................................................................... 71
3.4.8 Based indexed addressing ............................................................................................................ 72
3.4.9 Stack addressing ........................................................................................................................... 72
CHAPTER 4 PORT FUNCTIONS ...................................................................................................... 73
4.1 Port Functions ......................................................................................................................... 73
4.2 Configuration of Ports ............................................................................................................. 75
4.2.1 Port 0 ............................................................................................................................................. 75
4.2.2 Port 1 ............................................................................................................................................. 76
4.2.3 Port 2 ............................................................................................................................................. 77
4.2.4 Port 3 ............................................................................................................................................. 79
4.2.5 Port 4 ............................................................................................................................................. 81
4.2.6 Port 5 ............................................................................................................................................. 82
4.2.7 Port 7 ............................................................................................................................................. 83
4.3 Registers to Control Port Function ........................................................................................ 85
4.4 Operations of Port Function ................................................................................................... 89
4.4.1 Writing to I/O port .......................................................................................................................... 89
4.4.2 Reading from I/O port .................................................................................................................... 89
4.4.3 Operations on I/O port ................................................................................................................... 89
CHAPTER 5 CLOCK GENERATOR ................................................................................................. 90
5.1 Functions of Clock Generator ................................................................................................ 90
5.2 Configuration of Clock Generator .......................................................................................... 90
5.3 Registers to Control Clock Generator ................................................................................... 92
5.4 System Clock Oscillator.......................................................................................................... 94
5.4.1 Main system clock oscillator .......................................................................................................... 94
5.4.2 Subsystem clock oscillator ............................................................................................................ 95
5.4.3 Divider ........................................................................................................................................... 98
5.4.4 When no subsystem clocks are used ............................................................................................ 98
5.5 Clock Generator Operations ................................................................................................... 99
5.5.1 Main system clock operations ....................................................................................................... 100
5.5.2 Subsystem clock operations .......................................................................................................... 101
5.6 Changing System Clock and CPU Clock Settings................................................................ 101
5.6.1 Time required for switchover between system clock and CPU clock ............................................. 101

12 Preliminary User’s Manual U16035EJ1V0UM
5.6.2 System clock and CPU clock switching procedure ........................................................................ 103
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 .......................................................................... 104
6.1 Functions of 16-Bit Timer/Event Counter 0 ........................................................................... 104
6.2 Configuration of 16-Bit Timer/Event Counter 0 .................................................................... 105
6.3 Registers to Control 16-Bit Timer/Event Counter 0 .............................................................. 108
6.4 Operations of 16-Bit Timer/Event Counter 0 ......................................................................... 114
6.4.1 Interval timer operations ................................................................................................................ 114
6.4.2 PPG output operations .................................................................................................................. 116
6.4.3 Pulse width measurement operations ........................................................................................... 117
6.4.4 External event counter operation .................................................................................................. 124
6.4.5 Square-wave output operation ...................................................................................................... 125
6.5 Cautions for 16-Bit Timer/Event Counter 0 ........................................................................... 128
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 .......................................................... 132
7.1 Functions of 8-Bit Timer/Event Counters 50 and 51 ............................................................ 132
7.2 Configurations of 8-Bit Timer/Event Counters 50 and 51 .................................................... 134
7.3 Registers to Control 8-Bit Timer/Event Counters 50 and 51 ............................................... 135
7.4 Operations of 8-Bit Timer/Event Counters 50 and 51........................................................... 140
7.4.1 Interval timer (8-bit) operation ....................................................................................................... 140
7.4.2 External event counter operation .................................................................................................. 144
7.4.3 Square-wave output (8-bit resolution) operation ........................................................................... 145
7.4.4 8-bit PWM output operation........................................................................................................... 146
7.4.5 Interval timer (16-bit) operation ..................................................................................................... 149
7.5 Cautions for 8-Bit Timer/Event Counters 50 and 51 ............................................................. 150
CHAPTER 8 WATCH TIMER ............................................................................................................ 152
8.1 Functions of Watch Timer ....................................................................................................... 152
8.2 Configuration of Watch Timer ................................................................................................ 153
8.3 Register to Control Watch Timer ............................................................................................ 154
8.4 Operations of Watch Timer ..................................................................................................... 155
8.4.1 Watch timer operation ................................................................................................................... 155
8.4.2 Interval timer operation.................................................................................................................. 155
CHAPTER 9 WATCHDOG TIMER .................................................................................................... 157
9.1 Functions of Watchdog Timer ................................................................................................ 157
9.2 Configuration of Watchdog Timer .......................................................................................... 159
9.3 Registers to Control Watchdog Timer ................................................................................... 159
9.4 Watchdog Timer Operations ................................................................................................... 163
9.4.1 Watchdog timer operation ............................................................................................................. 163
9.4.2 Interval timer operation.................................................................................................................. 164
CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER ............................................ 165
10.1 Functions of Clock Output/Buzzer Output Controller ........................................................ 165

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Preliminary User’s Manual U16035EJ1V0UM
10.2 Configuration of Clock Output/Buzzer Output Controller ................................................. 166
10.3 Registers to Control Clock Output/Buzzer Output Controller ........................................... 166
10.4 Operations of Clock Output/Buzzer Output Controller ...................................................... 169
10.4.1 Operation as clock output ............................................................................................................ 169
10.4.2 Operation as buzzer output ......................................................................................................... 169
CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) ......................................... 170
11.1 Functions of A/D Converter .................................................................................................. 170
11.2 Configuration of A/D Converter ............................................................................................ 172
11.3 Registers to Control A/D Converter ..................................................................................... 174
11.4 Operations of A/D Converter ................................................................................................ 177
11.4.1 Basic operations of A/D converter ............................................................................................... 177
11.4.2 Input voltage and conversion results ........................................................................................... 179
11.4.3 A/D converter operation mode .................................................................................................... 180
11.5 How to Read A/D Converter Characteristics Table ............................................................ 183
11.6 Cautions for A/D Converter .................................................................................................. 186
CHAPTER 12 10-BIT A/D CONVERTER ( µ PD780034AS SUBSERIES) ...................................... 193
12.1 Functions of A/D Converter .................................................................................................. 193
12.2 Configuration of A/D Converter ............................................................................................ 194
12.3 Registers to Control A/D Converter ..................................................................................... 195
12.4 Operations of A/D Converter ................................................................................................ 198
12.4.1 Basic operations of A/D converter ............................................................................................... 198
12.4.2 Input voltage and conversion results ........................................................................................... 200
12.4.3 A/D converter operation mode .................................................................................................... 201
12.5 How to Read A/D Converter Characteristics Table ............................................................ 203
12.6 Cautions for A/D Converter .................................................................................................. 206
CHAPTER 13 SERIAL INTERFACE (UART0)................................................................................. 213
13.1 Functions of Serial Interface ............................................................................................... 213
13.2 Configuration of Serial Interface ......................................................................................... 215
13.3 Registers to Control Serial Interface .................................................................................. 216
13.4 Operations of Serial Interface.............................................................................................. 220
13.4.1 Operation stop mode ................................................................................................................... 220
13.4.2 Asynchronous serial interface (UART) mode .............................................................................. 221
13.4.3 Infrared data transfer mode ......................................................................................................... 233
CHAPTER 14 SERIAL INTERFACE (SIO3) .................................................................................... 236
14.1 Functions of Serial Interface ............................................................................................... 236
14.2 Configuration of Serial Interface ......................................................................................... 237
14.3 Registers to Control Serial Interface .................................................................................. 238
14.4 Operations of Serial Interface.............................................................................................. 242
14.4.1 Operation stop mode ................................................................................................................... 242
14.4.2 3-wire serial I/O mode ................................................................................................................. 243

14 Preliminary User’s Manual U16035EJ1V0UM
CHAPTER 15 INTERRUPT FUNCTIONS ......................................................................................... 246
15.1 Interrupt Function Types ...................................................................................................... 246
15.2 Interrupt Sources and Configuration ................................................................................... 246
15.3 Registers to Control Interrupt Function .............................................................................. 250
15.4 Interrupt Servicing Operations ............................................................................................. 256
15.4.1 Non-maskable interrupt request acknowledge operation ............................................................ 256
15.4.2 Maskable interrupt request acknowledge operation .................................................................... 259
15.4.3 Software interrupt request acknowledge operation .................................................................... 261
15.4.4 Nesting interrupt servicing ........................................................................................................... 262
15.4.5 Interrupt request hold .................................................................................................................. 265
CHAPTER 16 STANDBY FUNCTION ............................................................................................... 266
16.1 Standby Function and Configuration .................................................................................. 266
16.1.1 Standby function .......................................................................................................................... 266
16.1.2 Standby function control register ................................................................................................. 267
16.2 Operations of Standby Function .......................................................................................... 268
16.2.1 HALT mode ................................................................................................................................. 268
16.2.2 STOP mode ................................................................................................................................. 271
CHAPTER 17 RESET FUNCTION .................................................................................................... 274
17.1 Reset Function ....................................................................................................................... 274
CHAPTER 18 µ PD78F0034BS ........................................................................................................... 278
18.1 Memory Size Switching Register ......................................................................................... 279
18.2 Flash Memory Programming ................................................................................................ 280
18.2.1 Selection of communication mode .............................................................................................. 280
18.2.2 Flash memory programming function .......................................................................................... 281
18.2.3 Connection of Flashpro III ........................................................................................................... 282
CHAPTER 19 INSTRUCTION SET ................................................................................................... 284
19.1 Conventions ........................................................................................................................... 285
19.1.1 Operand identifiers and specification methods ........................................................................... 285
19.1.2 Description of “operation” column ................................................................................................ 286
19.1.3 Description of “flag operation” column ......................................................................................... 286
19.2 Operation List ........................................................................................................................ 287
19.3 Instructions Listed by Addressing Type ............................................................................. 295
APPENDIX A DIFFERENCES BETWEEN µ PD780024A, 780024AS, 780034A,
AND 780034AS SUBSERIES ...................................................................................... 299
APPENDIX B DEVELOPMENT TOOLS ........................................................................................... 300
B.1 Language Processing Software............................................................................................. 302

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Preliminary User’s Manual U16035EJ1V0UM
B.2 Flash Memory Writing Tools .................................................................................................. 303
B.3 Debugging Tools ..................................................................................................................... 304
B.3.1 Hardware ...................................................................................................................................... 304
B.3.2 Software ........................................................................................................................................ 305
APPENDIX C EMBEDDED SOFTWARE .......................................................................................... 306
APPENDIX D REGISTER INDEX ...................................................................................................... 307
D.1 Register Name Index ............................................................................................................... 307
D.2 Register Symbol Index ........................................................................................................... 309

16 Preliminary User’s Manual U16035EJ1V0UM
LIST OF FIGURES (1/6)
Figure No. Title Page
2-1 Pin I/O Circuit List ................................................................................................................................ 42
3-1 Memory Map (
µ PD780021AS, 780031AS) .......................................................................................... 43
3-2 Memory Map (
µ PD780022AS, 780032AS) .......................................................................................... 44
3-3 Memory Map (
µ PD780023AS, 780033AS) .......................................................................................... 45
3-4 Memory Map (
µ PD780024AS, 780034AS) .......................................................................................... 46
3-5 Memory Map (
µ PD78F0034BS) .......................................................................................................... 47
3-6 Data Memory Addressing (
µ PD780021AS, 780031AS) ...................................................................... 50
3-7 Data Memory Addressing (
µ PD780022AS, 780032AS) ...................................................................... 51
3-8 Data Memory Addressing (
µ PD780023AS, 780033AS) ...................................................................... 52
3-9 Data Memory Addressing (
µ PD780024AS, 780034AS) ...................................................................... 53
3-10 Data Memory Addressing (
µ PD78F0034BS) ....................................................................................... 54
3-11 Format of Program Counter ................................................................................................................. 55
3-12 Format of Program Status Word .......................................................................................................... 55
3-13 Format of Stack Pointer ....................................................................................................................... 57
3-14 Data to Be Saved to Stack Memory ..................................................................................................... 57
3-15 Data to Be Restored from Stack Memory ............................................................................................ 57
3-16 Configuration of General-Purpose Register ......................................................................................... 58
4-1 Port Types ............................................................................................................................................ 73
4-2 Block Diagram of P00 to P03 ............................................................................................................... 76
4-3 Block Diagram of P10 to P13 ............................................................................................................... 76
4-4 Block Diagram of P20, P22, P23, and P25 .......................................................................................... 77
4-5 Block Diagram of P21 and P24 ............................................................................................................ 78
4-6 Block Diagram of P34 and P36 ............................................................................................................ 79
4-7 Block Diagram of P35 .......................................................................................................................... 80
4-8 Block Diagram of P40 to P47 ............................................................................................................... 81
4-9 Block Diagram of Falling Edge Detector .............................................................................................. 81
4-10 Block Diagram of P50 to P57 ............................................................................................................... 82
4-11 Block Diagram of P70 to P73 ............................................................................................................... 83
4-12 Block Diagram of P74 and P75 ............................................................................................................ 84
4-13 Format of Port Mode Register (PM0, PM2 to PM5, PM7) .................................................................... 86
4-14 Format of Pull-Up Resistor Option Register (PU0, PU2 to PU5, PU7) ................................................ 88
5-1 Block Diagram of Clock Generator....................................................................................................... 91
5-2 Subsystem Clock Feedback Resistor .................................................................................................. 92
5-3 Format of Processor Clock Control Register (PCC) ............................................................................ 93
5-4 External Circuit of Main System Clock Oscillator ................................................................................. 94
5-5 External Circuit of Subsystem Clock Oscillator .................................................................................... 95
5-6 Examples of Incorrect Resonator Connection ..................................................................................... 96
5-7 Main System Clock Stop Function ....................................................................................................... 100

17
Preliminary User’s Manual U16035EJ1V0UM
LIST OF FIGURES (2/6)
Figure No. Title Page
5-8 System Clock and CPU Clock Switching ............................................................................................. 103
6-1 Block Diagram of 16-Bit Timer/Event Counter 0 .................................................................................. 105
6-2 Format of 16-Bit Timer Mode Control Register 0 (TMC0) .................................................................... 109
6-3 Format of Capture/Compare Control Register 0 (CRC0) ..................................................................... 110
6-4 Format of 16-Bit Timer Output Control Register 0 (TOC0) .................................................................. 111
6-5 Format of Prescaler Mode Register 0 (PRM0)..................................................................................... 112
6-6 Format of Port Mode Register 7 (PM7) ................................................................................................ 113
6-7 Control Register Settings for Interval Timer Operation ........................................................................ 114
6-8 Interval Timer Configuration Diagram .................................................................................................. 115
6-9 Timing of Interval Timer Operation....................................................................................................... 115
6-10 Control Register Settings for PPG Output Operation ........................................................................... 116
6-11 Control Register Settings for Pulse Width Measurement with Free-Running Counter
and One Capture Register ................................................................................................................... 117
6-12 Configuration Diagram for Pulse Width Measurement by Free-Running Counter ................................ 118
6-13 Timing of Pulse Width Measurement Operation by Free-Running Counter
and One Capture Register (with Both Edges Specified) ...................................................................... 118
6-14 Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter ............ 119
6-15 CR01 Capture Operation with Rising Edge Specified.......................................................................... 120
6-16 Timing of Pulse Width Measurement Operation with Free-Running Counter
(with Both Edges Specified) ................................................................................................................. 120
6-17 Control Register Settings for Pulse Width Measurement with
Free-Running Counter and Two Capture Registers ............................................................................. 121
6-18 Timing of Pulse Width Measurement Operation by Free-Running Counter
and Two Capture Registers (with Rising Edge Specified) .................................................................... 122
6-19 Control Register Settings for Pulse Width Measurement by Means of Restart ................................... 123
6-20
Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified) .......... 123
6-21 Control Register Settings in External Event Counter Mode ................................................................. 124
6-22 External Event Counter Configuration Diagram ................................................................................... 125
6-23 External Event Counter Operation Timings (with Rising Edge Specified) ............................................ 125
6-24 Control Register Settings in Square-Wave Output Mode ..................................................................... 126
6-25 Square-Wave Output Operation Timing ............................................................................................... 127
6-26 16-Bit Timer Counter 0 (TM0) Start Timing .......................................................................................... 128
6-27 Timings After Change of Compare Register During Timer Count Operation ....................................... 128
6-28 Capture Register Data Retention Timing ............................................................................................. 129
6-29 Operation Timing of OVF0 Flag ........................................................................................................... 130
7-1 Block Diagram of 8-Bit Timer/Event Counter 50 .................................................................................. 133
7-2 Block Diagram of 8-Bit Timer/Event Counter 51 .................................................................................. 133
7-3 Format of Timer Clock Select Register 50 (TCL50) ............................................................................. 135
7-4 Format of Timer Clock Select Register 51 (TCL51) ............................................................................. 136

18 Preliminary User’s Manual U16035EJ1V0UM
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Figure No. Title Page
7-5 Format of 8-Bit Timer Mode Control Register 5n (TMC5n) .................................................................. 137
7-6 Format of Port Mode Register 7 (PM7) ................................................................................................ 139
7-7 Interval Timer Operation Timings ......................................................................................................... 141
7-8 External Event Counter Operation Timing (with Rising Edge Specified) ............................................. 144
7-9 Square-Wave Output Operation Timing ............................................................................................... 145
7-10 PWM Output Operation Timing ............................................................................................................ 147
7-11 Timing of Operation by CR5n Transition .............................................................................................. 148
7-12 16-Bit Resolution Cascade Connection Mode ..................................................................................... 150
7-13 8-Bit Timer Counter Start Timing ......................................................................................................... 150
7-14 Timing After Change of Compare Register During Timer Count Operation ......................................... 151
8-1 Block Diagram of Watch Timer ............................................................................................................. 152
8-2 Format of Watch Timer Operation Mode Register (WTM) ................................................................... 154
8-3 Operation Timing of Watch Timer/Interval Timer .................................................................................. 156
9-1 Block Diagram of Watchdog Timer ....................................................................................................... 157
9-2 Format of Watchdog Timer Clock Select Register (WDCS) ................................................................. 160
9-3 Format of Watchdog Timer Mode Register (WDTM) ............................................................................ 161
9-4 Format of Oscillation Stabilization Time Select Register (OSTS) ........................................................ 162
10-1 Block Diagram of Clock Output/Buzzer Output Controller ................................................................... 165
10-2 Format of Clock Output Select Register (CKS).................................................................................... 167
10-3 Format of Port Mode Register 7 (PM7) ................................................................................................ 168
10-4 Remote Control Output Application Example ...................................................................................... 169
11-1 Block Diagram of 8-Bit A/D Converter ................................................................................................. 171
11-2 Format of A/D Converter Mode Register 0 (ADM0) ............................................................................. 175
11-3 Format of Analog Input Channel Specification Register 0 (ADS0) ...................................................... 176
11-4 Format of External Interrupt Rising Edge Enable Register (EGP) and
External Interrupt Falling Edge Enable Register (EGN) ....................................................................... 176
11-5 Basic Operation of 8-Bit A/D Converter ............................................................................................... 178
11-6 Relationship Between Analog Input Voltage and A/D Conversion Result ............................................ 179
11-7 A/D Conversion by Hardware Start (When Falling Edge Is Specified) ................................................. 181
11-8 A/D Conversion by Software Start ....................................................................................................... 182
11-9 Overall Error ......................................................................................................................................... 183
11-10 Quantization Error ................................................................................................................................ 183
11-11 Zero Scale Offset ................................................................................................................................. 184
11-12 Full Scale Offset................................................................................................................................... 184
11-13 Integral Linearity Error ......................................................................................................................... 184
11-14 Differential Linearity Error .................................................................................................................... 184
11-15 Example of Method of Reducing Current Consumption in Standby Mode ........................................... 186

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Preliminary User’s Manual U16035EJ1V0UM
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Figure No. Title Page
11-16 Analog Input Pin Connection ............................................................................................................... 187
11-17 A/D Conversion End Interrupt Request Generation Timing ................................................................. 188
11-18 Timing of Reading Conversion Result (When Conversion Result Is Undefined) ................................. 189
11-19 Timing of Reading Conversion Result (When Conversion Result Is Normal) ...................................... 189
11-20 AVDD Pin Connection ........................................................................................................................... 190
11-21 Example of Connecting Capacitor to AVREF Pin ................................................................................... 190
11-22 Internal Equivalent Circuit of Pins ANI0 to ANI3 .................................................................................. 191
11-23 Example of Connection If Signal Source Impedance Is High .............................................................. 192
12-1 Block Diagram of 10-Bit A/D Converter ............................................................................................... 193
12-2 Format of A/D Converter Mode Register 0 (ADM0) ............................................................................. 196
12-3 Format of Analog Input Channel Specification Register 0 (ADS0) ...................................................... 197
12-4 Format of External Interrupt Rising Edge Enable Register (EGP) and
External Interrupt Falling Edge Enable Register (EGN) ....................................................................... 197
12-5 Basic Operation of 10-Bit A/D Converter ............................................................................................. 199
12-6 Relationship Between Analog Input Voltage and A/D Conversion Result ............................................ 200
12-7 A/D Conversion by Hardware Start (When Falling Edge Is Specified) ................................................. 201
12-8 A/D Conversion by Software Start ....................................................................................................... 202
12-9 Overall Error ......................................................................................................................................... 203
12-10 Quantization Error ................................................................................................................................ 203
12-11 Zero Scale Offset ................................................................................................................................. 204
12-12 Full Scale Offset................................................................................................................................... 204
12-13 Integral Linearity Error ......................................................................................................................... 204
12-14 Differential Linearity Error .................................................................................................................... 204
12-15 Example of Method of Reducing Current Consumption in Standby Mode ........................................... 206
12-16 Analog Input Pin Connection ............................................................................................................... 207
12-17 A/D Conversion End Interrupt Request Generation Timing ................................................................. 208
12-18 Timing of Reading Conversion Result (When Conversion Result Is Undefined) ................................. 209
12-19 Timing of Reading Conversion Result (When Conversion Result Is Normal) ...................................... 209
12-20 AVDD Pin Connection ........................................................................................................................... 210
12-21 Example of Connecting Capacitor to AVREF Pin ................................................................................... 210
12-22 Internal Equivalent Circuit of Pins ANI0 to ANI3 .................................................................................. 211
12-23 Example of Connection If Signal Source Impedance Is High .............................................................. 212
13-1 Block Diagram of Serial Interface (UART0) .......................................................................................... 214
13-2 Block Diagram of Baud Rate Generator .............................................................................................. 214
13-3 Format of Asynchronous Serial Interface Mode Register 0 (ASIM0) ................................................... 217
13-4 Format of Asynchronous Serial Interface Status Register 0 (ASIS0) .................................................. 218
13-5 Format of Baud Rate Generator Control Register 0 (BRGC0)............................................................. 219
13-6 Baud Rate Error Tolerance (When k = 0), Including Sampling Errors .................................................. 227
13-7 Format of Transmit/Receive Data in Asynchronous Serial Interface .................................................... 228

20 Preliminary User’s Manual U16035EJ1V0UM
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Figure No. Title Page
13-8 Timing of Asynchronous Serial Interface Transmit Completion Interrupt Request ............................... 230
13-9 Timing of Asynchronous Serial Interface Receive Completion Interrupt Request ............................... 231
13-10 Receive Error Timing ........................................................................................................................... 232
13-11 Data Format Comparison Between Infrared Data Transfer Mode and UART Mode ............................ 233
14-1 Block Diagram of Serial Interface (SIO3n) ........................................................................................... 236
14-2 Format of Serial Operation Mode Register 30 (CSIM30) ..................................................................... 239
14-3 Format Serial Operation Mode Register 31 (CSIM31) ......................................................................... 241
14-4 Timing of 3-Wire Serial I/O Mode ........................................................................................................ 245
15-1 Basic Configuration of Interrupt Function ............................................................................................ 248
15-2 Format of Interrupt Request Flag Register (IF0L, IF0H, IF1L) ............................................................. 251
15-3 Format of Interrupt Mask Flag Register (MK0L, MK0H, MK1L) ........................................................... 252
15-4 Format of Priority Specification Flag Register (PR0L, PR0H, PR1L) .................................................. 253
15-5 Format of External Interrupt Rising Edge Enable Register (EGP) and
External Interrupt Falling Edge Enable Register (EGN) ....................................................................... 254
15-6 Format of Memory Expansion Mode Register (MEM) ......................................................................... 254
15-7 Format of Program Status Word .......................................................................................................... 255
15-8 Non-Maskable Interrupt Request Generation to Acknowledge Flowchart ........................................... 257
15-9 Non-Maskable Interrupt Request Acknowledge Timing ....................................................................... 257
15-10 Non-Maskable Interrupt Request Acknowledge Operation .................................................................. 258
15-11 Interrupt Request Acknowledge Processing Algorithm ........................................................................ 260
15-12 Interrupt Request Acknowledge Timing (Minimum Time) .................................................................... 261
15-13 Interrupt Request Acknowledge Timing (Maximum Time) ................................................................... 261
15-14 Nesting Examples ................................................................................................................................ 263
15-15 Interrupt Request Hold ......................................................................................................................... 265
16-1 Format of Oscillation Stabilization Time Select Register (OSTS) ........................................................ 267
16-2 HALT Mode Release by Interrupt Request Generation ........................................................................ 269
16-3 HALT Mode Release by RESET Input ................................................................................................. 270
16-4 STOP Mode Release by Interrupt Request Generation ....................................................................... 272
16-5 STOP Mode Release by RESET Input ................................................................................................ 273
17-1 Block Diagram of Reset Function ........................................................................................................ 274
17-2 Timing of Reset by RESET Input ......................................................................................................... 275
17-3 Timing of Reset Due to Watchdog Timer Overflow ..............................................................................275
17-4 Timing of Reset in STOP Mode by RESET Input.................................................................................275
18-1 Format of Memory Size Switching Register (IMS) ............................................................................... 279
18-2 Format of Communication Mode Selection .......................................................................................... 281
18-3 Connection of Flashpro III in 3-Wire Serial I/O Mode .......................................................................... 282