NEC V850ES/DJ2 User manual

User’s Manual
V850ES/DJ2TM
32-bit System in Package Microcontroller
Hardware
µPD70F3325
Document No. U17763EE1V1UD00
Date Published September 2005
NEC Electronics 2005
Printed in Germany

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User’s Manual U17763EE1V1UD00
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VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate.When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
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The information in this document is current as of September, 2005. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
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The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
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M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
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Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
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for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":

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User’s Manual U17763EE1V1UD00
All (other) product, brand, or trade names used in this pamphlet are the trademarks or
registered trademarks of their respective owners.
Product specifications are subject to change without notice. To ensure that you have
the latest product data, please contact your local NEC Electronics sales office.

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Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics America Inc.
Santa Clara, California
T
el: 408-588-6000
800-366-9782
Fax: [phone]
800-729-9288
NEC Electronics (Europe) GmbH
Duesseldorf, Germany
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User’s Manual U17763EE1V1UD00
Preface
Readers This manual is intented for users who want to understand the functions of the
V850ES/DJ2.
Purpose This manual presents the hardware manual of the V850ES/DJ2.
This User’s Manual is an extension of the F_Line User’s Manual.
F_Line Items:
For all of the items regarding the FG2 please refer to the F_Line User’s
Manual/Data sheet (U17215EJ2V0UD00 (2nd edition) and further releases).
MTRC of D_Line:
In this User’s Manual/Data Sheet all of the MTRC relevant items and the
internal connection or pinout of the D_Line device are regarded.
Organization This system specification describes the following sections:
• Pin function
• Port function
• Internal peripheral function
• Electrical target specification
Legend Symbols and notation are used as follows:
Weight in data notation : Left is high-order column, right is low order column
Active low notation : xxx (pin or signal name is over-scored) or
/xxx (slash before signal name)
Memory map address: : High order at high stage and low order at low stage
Note : Explanation of (Note) in the text
Caution : Item deserving extra attention
Remark : Supplementary explanation to the text
Numeric notation : Binary . . . XXXX or XXXB
Decimal . . . XXXX
Hexadecimal . . . XXXXH or 0x XXXX
Prefixes representing powers of 2 (address space, memory capacity)
K (kilo): 210 = 1024
M (mega): 220 = 10242= 1,048,576
G (giga): 230 = 10243= 1,073,741,824

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Chapter 1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2 Features (V850ES/D_Line) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.3 About the Subject of this User’s Manual. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.4 Internal Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.4.1 System in Package (SiP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5 Communication Between the FG2 and MTRC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.1 Communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.2 Internal or external communication via CSIB1 . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.6 Pinout of DJ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.7 Overview of MTRC Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.8 Peripheral I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Chapter 2 V850ES/FG2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.1 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.2 Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.3 CPU Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.4 Clock Generation Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.5 16-bit Timer/event Counter P. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.6 16-bit Timer/event Counter Q. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.7 16-bit Interval Timer M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.8 Watch Timer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.9 Functions of Watchdog Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.10 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.11 Asynchronous Serial Interface A (UARTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.12 3-Wire Serial Interface (CSIB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.13 CAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
2.14 Interrupt/Exception Processing Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.15 DMA Controller (DMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.16 Key Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.17 Standby Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.18 Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.19 Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2.20 Low-voltage Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.21 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.22 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.23 ROM Mask Options Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.24 On-chip Debug Unit (Flash Memory Versions only). . . . . . . . . . . . . . . . . . . . . . . . . . 64
Chapter 3 Pin Function of MTRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.1 Pin Configuration (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.2 List of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.3 Pin I/O Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.3.1 Type A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.3.2 Type B-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.3.3 Type B-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.3.4 Type D-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.3.5 Type D-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.3.6 Type D-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.3.7 Type D-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.3.8 Type CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.3.9 Type MTCS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.3.10 Type SCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.3.11 Type SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.3.12 Type SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Chapter 4 Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.1 Setting Alternate Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

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4.2 Port MT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.2.1 Port MT0 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.2.2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.3 Port MT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.3.1 Port MT1 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.3.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.4 Port SM1/SM2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
4.4.1 Port SM1/SM2 functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.5 Port MT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.5.1 Port MT2 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.5.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.6 Port MT3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.6.1 Port MT3 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.6.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.7 Port MT4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.7.1 Port MT4 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.7.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Chapter 5 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.1 Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.1.1 Autocalibration function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.1.2 Ring Oscillator states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.2 Ring Oscillator Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.2.1 RingOSC Control Register (MRCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.2.2 RingOSC Calibration Register (MRCAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.3 Calibration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.4 MTRESET Release of the MTRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.5 Standby Mode Release of the Ring Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.6 Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Chapter 6 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.1 Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.2 Command Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.2.1 Command Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.2.2 Data Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
6.3 Serial I/F Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.3.1 Read from MTRC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
6.3.2 Timing of MTRC Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
6.3.3 MTRC Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
6.3.4 Timing of MTRC Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.4 External CSIB1 Function (EXCSI1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.5 Internal CSIB1 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.5.1 Operation of Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Chapter 7 Meter Controller Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
7.1 Meter Controller Driver Function Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
7.2 Register Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
7.2.1 Free Running Counter m (MCNTm, m = 0, 1) . . . . . . . . . . . . . . . . . . . . . . . . .115
7.2.2 Sin Compare Register n0 (MCMPn0, n = 1 to 6) . . . . . . . . . . . . . . . . . . . . . . . 116
7.2.3 Cos Compare Register n1 (MCMPn1, n = 1 to 6). . . . . . . . . . . . . . . . . . . . . . . 117
7.2.4 Compare Control Register (MCMPCn, n = 1 to 6) . . . . . . . . . . . . . . . . . . . . . . 118
7.2.5 Timer Mode Control Register (MCNTm) (m = 0, 1) . . . . . . . . . . . . . . . . . . . . .120
7.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
7.3.1 Count timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
7.3.2 Operation of 1-bit addition circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
7.3.3 PWM output with 1 clock shifted operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .124
7.4 Method of Using. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7.4.1 Macro Standby operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

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User’s Manual U17763EE1V0UD00
Chapter 8 Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
8.1 Separated Reset Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
8.2 External Reset Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
8.2.1 External reset circuitry with pull-down resistor . . . . . . . . . . . . . . . . . . . . . . . . . 128
8.2.2 External reset circuitry with pull-up resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Chapter 9 Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
9.1 Absolute Maximum Ratings (TA= 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
9.2 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
9.3 Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
9.4 Oscillation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.4.1 Main System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . 133
9.4.2 Sub System Clock Oscillation Circuit Characteristics. . . . . . . . . . . . . . . . . . . . 134
9.4.3 MTRC Ring Oscillator Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . 135
9.4.4 PLL Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
9.4.5 Ring-OSC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
9.5 Voltage Regulator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
9.6 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
9.6.1 Input/Output Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
9.6.2 Pin Leak Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
9.6.3 Specific Power Supply Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
9.6.4 Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
9.7 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
9.7.1 EXCLO output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
9.7.2 RESET, Interrupt, FLMD0 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
9.7.3 Key Return timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
9.7.4 Timer Input timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
9.7.5 CSI timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
9.7.6 UART timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
9.7.7 CAN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
9.7.8 AD Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
9.7.9 LVI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
9.7.10 RAM retention flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
9.7.11 Flash Memory Programming characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Chapter 10 Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Chapter 11 Recommended Soldering Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Appendix A Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

12 User’s Manual U17763EE1V0UD00

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User’s Manual U17763EE1V1UD00
Figure 1-1: D_Line SiP .................................................................................................................. 18
Figure 1-2: CS Functionality .......................................................................................................... 20
Figure 1-3: Pinout of DJ2............................................................................................................... 21
Figure 1-4: Block Diagram of the MTRC........................................................................................ 22
Figure 2-1: Block Diagram............................................................................................................. 27
Figure 2-2: Pin I/O Circuit Types (1/2)........................................................................................... 35
Figure 2-3: Figure 2-1. Pin I/O Circuit Types (2/2)........................................................................ 36
Figure 2-4: Port Configuration ....................................................................................................... 37
Figure 2-5: Clock Generator .......................................................................................................... 40
Figure 2-6: Figure 6-1. Block Diagram of Timer P........................................................................ 42
Figure 2-7: Figure 7-1. Block Diagram of Timer Q........................................................................ 44
Figure 2-8: Block Diagram of Timer M........................................................................................... 45
Figure 2-9: Block Diagram of Watch Timer.................................................................................... 46
Figure 2-10: Block Diagram of Prescaler 3...................................................................................... 47
Figure 2-11: Block Diagram of Watchdog Timer 2........................................................................... 48
Figure 2-12: Block Diagram of A/D Converter ................................................................................. 49
Figure 2-13: Block Diagram of Asynchronous Serial Interface A..................................................... 51
Figure 2-14: Block Diagram of 3-Wire Serial Interface .................................................................... 52
Figure 2-15: Block Diagram of CAN Module.................................................................................... 53
Figure 2-16: Block Diagram of DMA Controller................................................................................ 55
Figure 2-17: Key Return Block Diagram.......................................................................................... 56
Figure 2-18: CLM Block Diagram .................................................................................................... 59
Figure 2-19: Block Diagram of Low-Voltage Detector ..................................................................... 60
Figure 2-20: Regulator..................................................................................................................... 61
Figure 2-21: Connection of REGC Pin (REGC = Capacitance)....................................................... 61
Figure 3-1: Pinout of MTRC........................................................................................................... 66
Figure 3-2: Type A-1...................................................................................................................... 71
Figure 3-3: Type B-1...................................................................................................................... 71
Figure 3-4: Type B-2...................................................................................................................... 72
Figure 3-5: Type D-1...................................................................................................................... 72
Figure 3-6: Type D-2...................................................................................................................... 73
Figure 3-7: Type D-3...................................................................................................................... 73
Figure 3-8: Type D-4...................................................................................................................... 74
Figure 3-9: Type CLK .................................................................................................................... 74
Figure 3-10: Type MTCS ................................................................................................................. 74
Figure 3-11: Type SCK.................................................................................................................... 75
Figure 3-12: Type SI........................................................................................................................ 75
Figure 3-13: Type SO ...................................................................................................................... 75
Figure 4-1: Port Register 0 (PMT0) Format .................................................................................. 79
Figure 4-2: Port MT0 Mode Register 0 (PMMT0) Format ............................................................. 79
Figure 4-3: Port Register 1 (PMT1) Format .................................................................................. 81
Figure 4-4: Port Mode Register 1 (PMMT1) Format ..................................................................... 81
Figure 4-5: Port Mode Control Register 1 (PMCMT1) Format ...................................................... 82
Figure 4-6: SM1SM2 Mode Control Register (SM12MC) Format ................................................. 83
Figure 4-7: Port Register 2 (PMT2) Format .................................................................................. 85
Figure 4-8: Port Mode Register 2 (PMMT2) Format ..................................................................... 85
Figure 4-9: Port Mode Control Register 2 (PMCMT2) Format ...................................................... 86
Figure 4-10: Port Register 3 (PMT3) Format .................................................................................. 88
Figure 4-11: Port Mode Control Register 3 (PMMT3) Format ......................................................... 88
Figure 4-12: Port Register 4 (PMT4) Format .................................................................................. 90
Figure 4-13: Port Mode Register 4 (PMMT4) Format ..................................................................... 90
Figure 4-14: Port Mode Control Register 4 (PMCMT4) Format ...................................................... 91
Figure 5-1: RingOSC Control Register (MRCTL) Format (1/2) ..................................................... 93
Figure 5-2: RingOSC Calibration Register (MRCAL) Format ....................................................... 95
Figure 5-3: Flowchart for Frequency Calibration ........................................................................... 96
Figure 5-4: Timing Diagram for Frequency Calibration.................................................................. 97
Figure 5-5: Flowchart for MTRESET Release ............................................................................... 98
Figure 5-6: Timing for MTRES Release......................................................................................... 99

14 User’s Manual U17763EE1V1UD00
Figure 5-7: Flowchart for Standby Mode Release .......................................................................100
Figure 5-8: Timing Diagram for Standby Mode Release.............................................................. 101
Figure 6-1: MTRC Operation Flow on Reading ...........................................................................106
Figure 6-2: MTRC Read Operation (Auto=0)...............................................................................107
Figure 6-3: MTRC Read Operation (Auto bit = 1)........................................................................ 107
Figure 6-4: Operation Flow on MTRC Writing..............................................................................108
Figure 6-5: MTRC Write Operation (Auto bit = 0)........................................................................109
Figure 6-6: MTRC Write Operation (Auto bit = 1)........................................................................109
Figure 6-7: Basic Operation......................................................................................................... 112
Figure 6-8: Continuous Data Transfer ......................................................................................... 112
Figure 7-1: Meter Controller Driver Block Diagram...................................................................... 114
Figure 7-2: Free Running Counter MCNTm Format ................................................................... 115
Figure 7-3: Sin Compare Register MCMPn0 Format ..................................................................116
Figure 7-4: Cos Compare Register MCMPn1 Format .................................................................117
Figure 7-5: Compare Control Register MCMPCn Format (1/2) ..................................................118
Figure 7-6: Timer Mode Control Register (MCNTm) Format (1/2) .............................................. 120
Figure 7-7: Restart Timing after Counting Operation Stopped .................................................... 122
Figure 7-8: Operation of 1-bit Addition.........................................................................................123
Figure 7-9: Output Timing of SM11 to SM44...............................................................................124
Figure 7-10: Output Timing of SM51 to SM64............................................................................... 124
Figure 7-11: Using of the SM......................................................................................................... 125
Figure 7-12: SM Standby Operation..............................................................................................126
Figure 8-1: External Reset Circuitry with Pull-Down Resistor......................................................128
Figure 8-2: External Reset Circuitry with Pull-Up Resistor ..........................................................129
Figure 10-1: V850ES/DJ2..............................................................................................................152

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User’s Manual U17763EE1V0UD00
Table 1-1: Features (V850ES/D_Line) ............................................................................................ 17
Table 1-2: Overview of MTRC Functions......................................................................................... 22
Table 1-3: Peripheral I/O Registers................................................................................................. 23
Table 2-1: Pin I/O Buffer Power Supplies (V850ES/FG2................................................................. 28
Table 2-2: Pin List (Port Pins).......................................................................................................... 28
Table 2-3: Pin List (Non-Port Pins).................................................................................................. 30
Table 2-4: Pin I/O Circuit Types and Recommended Connection of Unused Pins.......................... 33
Table 2-5: Assignment of Key Return Detection Pins...................................................................... 56
Table 2-6: Standby Modes............................................................................................................... 57
Table 2-7: Mask Options.................................................................................................................. 63
Table 3-1: List of Pin Functions....................................................................................................... 67
Table 3-2: List of Pin Functions....................................................................................................... 69
Table 4-1: Alternate Pin Functions .................................................................................................. 76
Table 4-2: Port MT0 Functions........................................................................................................ 78
Table 4-3: Port MT1 Functions........................................................................................................ 80
Table 4-4: Port MT2 Functions........................................................................................................ 83
Table 4-5: Port MT2 Functions........................................................................................................ 84
Table 4-6: Port MT3 Functions........................................................................................................ 87
Table 4-7: Port MT4 Functions........................................................................................................ 89

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User’s Manual U17763EE1V1UD00
Chapter 1 Introduction
The V850ES/DJ2 is a product of the NEC’s V850 D_Line Series of single-chip microcontroller designed
for application with up to 6 stepper motor channels.
It provides low-power operation for real-time control applications especial for automotive Dashboard
applications.
1.1 General
The V850ES/DJ2 is a 32-bit System in Package (SiP) microcontroller that includes a V850ES CPU core
device of the F_Line (V850ES/FG2) and a Meter Controller/Driver (MTRC) in one package.
The F_Line includes peripheral functions such as ROM/RAM, a timer/counter, serial interfaces, and an
A/D converter.
In addition to high real-time response characteristics and 1-clock-pitch basic instructions, the V850ES/
FG2 features multiply instructions, saturated operation instructions, bit manipulation instructions, etc.,
realised by a hardware multiplier, as optimum instructions for digital servo control applications. Moreo-
ver, as a real-time control system, the V850ES/FG2 enables extremely high cost-performance for appli-
cations that require a low power consumption, such as automotive applications.
For an overview of the V850ES/FG3 refer to “V850ES/FG2 Introduction” on page 25.
The integrated MTRC supplies a meter controller driver macro for up to 6 stepper motor channels and
GPIOs. Via the dedicated interface the controlling will be handled with a dedicated protocol.
For this internal interface the 3-wire serial interface CSIB1 of the FG2 device is used for the serial com-
munication and the PCM0 port of the FG2 device is used as the CS function for the MTRC.
1.2 Features (V850ES/D_Line)
Table 1-1: Features (V850ES/D_Line)
Part Number Name FG2 device Pin Internal Memory CAN SM
Flash (KB) RAM (KB)
µPD70F3325 V850ES/DJ2 µPD70F3235(A)/FG2 144 256 12 2 6

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Chapter 1 Introduction
User’s Manual U17763EE1V1UD00
1.3 About the Subject of this User’s Manual
This User’s Manual is an extension of the F_Line User’s Manual.
F_Line Items:
For all of the items regarding the FG2 please refer to the F_Line User’s Manual/Data Sheet
(U17215EJ2V0UD00 (2nd edition) and further releases).
MTRC of D_Line:
In this User’s Manual/Data Sheet all of the MTRC relevant items and the internal connection or pinout
of the D_Line device are regarded.
1.4 Internal Connection
The following pins of the FG2 device are connected to the MTRC:
•CSI I/F: SIB1, SOB1, SCKB1
•Chip select: PCM0 as CS
1.4.1 System in Package (SiP)
Figure 1-1: D_Line SiP
CPU
CSI
CSI
RegCTL
SM
Macro
FG2 Device MTRC
CLK
CS
SCK
SO
SI
CLKOUT
PCM0
SCKB1
SIB1
SOB1
1 chip

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Chapter 1 Introduction
User’s Manual U17763EE1V1UD00
1.5 Communication Between the FG2 and MTRC
The clocked synchronous serial interface CSIB1 of the FG2 device is used for the communication with
the MTRC.
The communication I/F of the MTRC is fixed to the following settings:
•I/F: CSI
•Mode: Slave mode
•Data length: 8-bits
(support continuous data transfer,
therefore the FG2 CSIB1can use 16-bit data
length)
•Transfer: MSB first
•Transmission: transmission/reception mode
1.5.1 Communication
The software for the communication between the FG2 device and the MTRC has to manage the I/F of
the CSIB1 and the PCM0 pin as chip select signal.
The CSI1B of the FG2 device has been set to master mode, because the MTRC CSI is always in slave
mode. Therefore it is necessary, that the CSIB1 sends dummy data if the FG2 device wants to read
data from the MTRC.
The MTRC CSI is always in 8-bit mode but is capable of continuous data transfer. Therefore the 16-bit
mode of the CSIB1 can be used for faster communication for example.

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Chapter 1 Introduction
User’s Manual U17763EE1V1UD00
1.5.2 Internal or external communication via CSIB1
Via the PCM0/CS signal the output functionality of the PMT4 port will be controlled, too.
Figure 1-2: CS Functionality
If the PMT4 port is configured for peripheral mode the PCM0/CS signal controls the output function of
the external CSIB1 (EXCSI1) functionality. The EXCSIB1 provide the FG2 CSIB1 communication for
external components, too. This function can be used, if there’s no internal communication between the
FG2 device and the MTRC.
With special regard to the last byte transfer of the internal communication protocol a switch control will
delay the switching until the last byte was transferred between FG2 and the MTRC.
If PMT4 is in port mode the signal of PMT4 depends only on the settings of the PMT4 SFRs.
PCM0/CS
and
MTCS EX_CSIB1 signals
1 EX_CSIB1 signals are in inactive state regardless to the communication of the CSIB1
0 EX_CSIB1 signals are active, dependent of the communication of the CSIB1
CS
SM
Macro
MTRC
CLK
SO
SI
SCK
V850ES/FG2
CLKOUT
SIB1
SOB1
SCKB1
PCM0
PMT43/EXCLO
PMT40/EXSI1
PMT41/EXSO1
PMT42/EXSCK1
MTCS
EXCSI1
DJ2 pins
Last byte
control