NI PXIe-1075 User manual

INSTALLATION GUIDE
18-Slot NI PXIe-1075 Backplane
This guide describes installation requirements for the 18-slot
NI PXIe-1075 backplane.
Contents
NI PXIe-1075 Backplane Overview ....................................................... 2
Interoperability with CompactPCI................................................... 3
System Controller Slot..................................................................... 3
Hybrid Peripheral Slots.................................................................... 4
PXI Express Peripheral Slots........................................................... 4
System Timing Slot ......................................................................... 4
PXI Local Bus.................................................................................. 5
PXI Trigger Bus............................................................................... 6
System Reference Clock.................................................................. 7
PXIe_SYNC_CTRL ........................................................................ 9
Mechanical Requirements....................................................................... 10
Mounting.......................................................................................... 10
Dimensions ...................................................................................... 10
Cooling............................................................................................. 11
Handling.................................................................................................. 12
Electrical Requirements .......................................................................... 12
PXI Connectors................................................................................ 12
Power ............................................................................................... 13
Connector J505 ......................................................................... 13
Connector J506 ......................................................................... 16
Connector J500 ......................................................................... 16
Connectors J1, J2, J5, and J3 .................................................... 17
Backplane Specifications................................................................. 17
System Synchronization Clock (PXI_CLK10, PXIe_CLK100,
PXIe_SYNC100) Specifications................................................... 18
10 MHz System Reference Clock: PXI_CLK10...................... 18
100 MHz System Reference Clock: PXIe_CLK100 and
PXIe_SYNC100 .................................................................... 18
External Clock Source .............................................................. 19

18-Slot NI PXIe-1075 Backplane Installation Guide 2 ni.com
PXIe_SYNC_CTRL..................................................................19
PXI Differential Star Triggers
(PXIe-DSTARA, PXIe-DSTARB, PXIe-DSTARC) .............20
Pinouts .....................................................................................................20
System Controller Slot Pinouts ........................................................21
System Timing Slot Pinouts .............................................................22
Hybrid Slot Pinouts ..........................................................................24
NI PXIe-1075 Backplane Overview
This section provides an overview of the backplane features for the
NI PXIe-1075 chassis. Figure 1 shows the backplane.
Figure 1. 18-Slot NI PXIe-1075 Backplane

©National Instruments 3 18-Slot NI PXIe-1075 Backplane Installation Guide
Interoperability with CompactPCI
With the NI PXIe-1075, you can use the following devices in a single
PXI Express system:
• PXI Express-compatible products
• CompactPCI Express-compatible 4-Link system controller products
• CompactPCI Express-compatible Type-2 peripheral products
• Hybrid-compatible PXI peripheral products
• Standard CompactPCI peripheral products
Figure 2. NI PXIe-1075 Backplane Architecture
System Controller Slot
The system controller slot is Slot 1 of the chassis and is a 4-Link
configuration system slot as defined by the CompactPCI Express and
PXI Express specifications. It has three system controller expansion slots
for system controller modules that are wider than one slot. These slots
allow the system controller to expand to the left to prevent the system
controller from using peripheral slots.
The backplane routes each of the system slots’ x4 PCI Express (PCIe) links
to a PCIe switch. The four PCIe switches have x4 PCIe links routed to each
peripheral slot as well as x1 links to two (2) PCIe-to-PCI bridges providing
32-bit/33 MHz PCI busses to the hybrid slots. Refer to Figure 2 for the
connectivity of PCIe and PCI.
By default, the system controller controls the power supply with the
PS_ON# signals. A logic low on this line turns on the power supply.
PLX
PEX8533
PCIe Switch
0
8
10
9
2
1
8
10
9
2
0
810
91
2
0
9
8
1
210
1
Link #1
x4
0
HHHH HHHH
12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
PCIe/PCI
Bridge
PCIe/PCI
Bridge
x4 x4 x4 x4x4x4
x4
x4
x4
x1
x4
x4 PLX
PEX8525
PCIe Switch x4
x4
x4
PLX
PEX8533
PCIe Switch
x4
x1
x4 x4
x4 PLX
PEX8533
PCIe Switch
x4
x4
Link #2
Link #3
Link #4

18-Slot NI PXIe-1075 Backplane Installation Guide 4 ni.com
Hybrid Peripheral Slots
The backplane includes eight hybrid peripheral slots as defined by the
PXI-5 PXI Express Hardware Specification: slots 2-5 and 15-18. A hybrid
peripheral slot can accept the following peripheral modules:
• A PXI Express peripheral with a x4 or x1 PCI Express link to the
system slot or through a switch to the system slot.
• A CompactPCI Express Type-2 peripheral with a x4 or x1 PCI Express
link to the system slot or through a switch to the system slot.
• A hybrid-compatible PXI peripheral module modified by replacing the
J2 connector with an XJ4 connector installed in the upper eight rows
of J2. Refer to the PXI Express Specification for details. The PXI
peripheral communicates through the backplane 32-bit PCI bus.
• A CompactPCI 32-bit peripheral on the backplane 32-bit PCI bus.
The hybrid peripheral slots provide full PXI Express functionality and
32-bit PXI functionality except for PXI Local Bus. The hybrid peripheral
slot connects only to PXI Local Bus 6 left and right.
PXI Express Peripheral Slots
There are eight PXI Express peripheral slots: slots 6-9 and 11-14. Slots 6-9
are connected to the system slot link 2 through a PCI Express switch. Slots
11-13 are connected to the system slot link 3 through a PCI Express switch.
Slot 14 is connected to the system slot link 4 through a PCI Express switch.
PXI Express peripheral slots can accept the following modules:
• A PXI Express peripheral with a x4 or x1 PCI Express link to the
system slot or through a switch to the system slot.
• A CompactPCI Express Type-2 peripheral with a x4 or x1 PCI Express
link to the system slot or through a switch to the system slot.
System Timing Slot
The system timing slot is slot 10. The system timing slot accepts the
following peripheral modules:
• A PXI Express system timing module with a x4 or x1 PCI Express link
to the system slot through a PCIe switch.
• A PXI Express peripheral with a x4 or x1 PCI Express link to the
system slot through a PCIe switch.
• A CompactPCI Express Type-2 peripheral with a x4 or x1 PCI Express
link to the system slot through a PCIe switch.

©National Instruments 5 18-Slot NI PXIe-1075 Backplane Installation Guide
The system timing slot has three dedicated differential pairs
(PXIe_DSTAR) connected from the TP1 and TP2 connectors to the XP3
connector for each PXI Express peripheral or hybrid peripheral slot, as well
as routed back to the XP3 connector of the system timing slot, as shown in
Figure 3. You can use the PXIe_DSTAR pairs for high-speed triggering,
synchronization, and clocking. Refer to the PXI Express Specification for
details.
The system timing slot also has a single-ended (PXI Star) trigger connected
to every slot. Refer to Figure 3 for details.
The system timing slot has a pin (PXI_CLK10_IN) through which a system
timing module can source a 10 MHz clock to which the backplane
phase-locks. Refer to the System Reference Clock section for details.
The system timing slot has a pin (PXIe_SYNC_CTRL) through which a
system timing module can control the PXIe_SYNC100 timing. Refer to the
PXI Express Specification and the PXIe_SYNC_CTRL section for details.
Figure 3. PXIe_DSTAR and PXI Star Connectivity Diagram
PXI Local Bus
The PXI backplane local bus is a daisy-chained bus that connects each
peripheral slot with adjacent peripheral slots to the left and right.
The backplane routes PXI Local Bus 6 between adjacent PXI slots. The left
local bus 6 from slot 1 is not routed anywhere, and the right local bus signal
from slot 18 is not routed anywhere.
PXIe_DStar 15
PXIe_DStar 14
PXIe_DStar 13
PXIe_DStar 16
PXIe_DStar 12
PXIe_DStar 11
PXIe_DStar 10
PXIe_DStar 9
PXIe_DStar 3
PXIe_DStar 0
PXI Star 0 PXI Star 10
PXIe_DStar 8
PXIe_DStar 2
PXIe_DStar 1
PXIe_DStar 4
PXIe_DStar 5
PXIe_DStar 7
PXIe_DStar 6
PXI Star 4 PXI Star 14
PXI Star 1 PXI Star 11
PXI Star 3 PXI Star 13
PXI Star 2 PXI Star 12
PXI Star 5 PXI Star 15
PXI Star 7 PXI Star 17
PXI Star 6 PXI Star 16
PXI Star 8
0
HHHH HHHH
12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

18-Slot NI PXIe-1075 Backplane Installation Guide 6 ni.com
Local bus signals may range from high-speed TTL signals to analog signals
as high as 42 V.
Initialization software uses the configuration information specific to each
adjacent peripheral module to evaluate local bus compatibility.
PXI Trigger Bus
All slots on the same PXI bus segment share eight PXI trigger lines. You
can use these trigger lines in a variety of ways. For example, you can use
triggers to synchronize the operation of several different PXI peripheral
modules. In other applications, one module in the system timing slot can
control carefully timed sequences of operations performed on other
modules in the system. Modules can pass triggers to one another, allowing
precisely timed responses to asynchronous external events the system is
monitoring or controlling. Figure 4 shows the PXI trigger bus connectivity.
The PXI trigger lines from adjacent PXI trigger bus segments can be routed
in either direction across the PXI trigger bridges through buffers. This
allows you to send trigger signals to, and receive trigger signals from, every
slot in the chassis. You can configure static trigger routing (user-specified
line and directional assignments) through Measurement & Automation
Explorer (MAX). Dynamic routing of triggers (automatic line assignments)
is supported through certain National Instruments drivers such as
NI-DAQmx.
Note Although you can route any trigger line in either direction, you cannot route it in
more than one direction at a time.
Figure 4. PXI Trigger Bus Connectivity Diagram
PXI
Trigger
Bridge
PXI
Trigger
Bridge
PXI Trigger Bus Segment 2 (Slots 7-12)PXI Trigger Bus Segment 1 (Slots 1-6) PXI Trigger Bus Segment 3 (Slots 13-18)
0
HHHH HHHH
12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

©National Instruments 7 18-Slot NI PXIe-1075 Backplane Installation Guide
System Reference Clock
The NI PXIe-1075 chassis supplies PXI_CLK10, PXIe_CLK100, and
PXIe_SYNC100 to every peripheral slot with an independent driver for
each signal.
An independent buffer (having a source impedance matched to the
backplane and a skew of less than 1 ns between slots) drives PXI_CLK10
to each peripheral slot. You can use this common reference clock signal to
synchronize multiple modules in a measurement or control system.
An independent buffer drives PXIe_CLK100 to each peripheral slot. These
clocks are matched in skew to less than 100 ps. The differential pair must
be terminated on the peripheral with LVPECL termination for the buffer to
drive PXIe_CLK100 so that when there is no peripheral or a peripheral that
does not connect to PXIe_CLK100, no clock is being driven on the pair to
that slot. Refer to Figure 5 for a termination example.
Figure 5. CLK100 Termination
An independent buffer drives PXIe_SYNC100 to each peripheral slot.
The differential pair must be terminated on the peripheral with LVPECL
termination for the buffer to drive PXIe_SYNC100 so that when there is
no peripheral or a peripheral that does not connect to PXIe_SYNC100, no
SYNC100 signal is being driven on the pair to that slot. Refer to Figure 5
for a termination example.
In summary, PXI_CLK10 is driven to every slot. PXIE_CLK100 and
PXIE_SYNC100 are driven to every peripheral slot.
CLK100 +
CLK100 –
50 Ω50 Ω
47 Ω0.01 µF
+
–

18-Slot NI PXIe-1075 Backplane Installation Guide 8 ni.com
PXI_CLK10, PXIe_CLK100, and PXIe_SYNC100 have the default timing
relationship described in Figure 6.
Figure 6. System Reference Clock Default Behavior
To synchronize the system to an external clock, you can drive PXI_CLK10
from an external source through the PXI_CLK10_IN pin on the System
Timing Slot. Refer to Table 11, XP4 Connector Pinout for the System
Timing Slot, for the pinout. When a 10 MHz clock is detected on this pin,
the backplane automatically phase-locks the PXI_CLK10, PXIe_CLK100,
and PXIe_SYNC100 signals to this external clock and distributes these
signals to the slots. Refer to the Backplane Specifications section for the
specification information for an external clock provided on the
PXI_CLK10_IN pin of the system timing slot.
You also can drive a 10 MHz clock on connector J506. Refer to Figure 11
for the location of this connector. When a 10 MHz clock is detected on this
connector, the backplane automatically phase-locks the PXI_CLK10,
PXIe_CLK100, and PXIe_SYNC100 signals to this external clock and
distributes these signals to the slots. Refer to the Backplane Specifications
section for the specification information for an external clock provided on
the 10 MHz REF IN connector on the chassis rear panel.
If the 10 MHz clock is present on both the PXI_CLK10_IN pin of the
System Timing Slot and connector J506, the signal on the System Timing
Slot is selected. Refer to Table 1, which explains how the backplane selects
the 10 MHz clocks.
Table 1. Backplane External Clock Input Truth Table
System Timing Slot
PXI_CLK10_IN
Rear Chassis Panel
10 MHz REF IN
Backplane PXI_CLK10,
PXIe_CLK100 and PXIe_SYNC100
No clock present No clock present Backplane generates its own clocks
No clock present 10 MHz clock present PXI_CLK10, PXIe_CLK100 and
PXIe_SYNC100 all phase-locked to
Rear Chassis Panel—10 MHz REF IN
PXIe_CLK100
PXI_CLK10
PXIe_SYNC100
012345678901234567890123456789

©National Instruments 9 18-Slot NI PXIe-1075 Backplane Installation Guide
A copy of the backplane’s PXI_CLK10 is exported to connector J506.
Refer to Figure 11 for the location of this connector. An independent buffer
drives this clock. Refer to the Backplane Specifications section for the
specification information for the 10 MHz REF OUT signal on the chassis
rear panel.
PXIe_SYNC_CTRL
PXIe_SYNC100 is by default a 10 ns pulse synchronous to PXI_CLK10.
The frequency of PXIe_SYNC100 is 10/nMHz, where nis a positive
integer. The default for nis 1, giving PXIe_SYNC100 a 100 ns period.
However, the backplane allows nto be programmed to other integers. For
example, setting n= 3 creates a PXIe_SYNC100 with a 300 ns period while
still maintaining its phase relationship to PXI_CLK10. The nvalue can be
any positive integer from 1 to 255.
The system timing slot has a control pin for PXIe_SYNC100 called
PXIe_SYNC_CTRL, for use when n > 1. Refer to Table 10, XP3 Connector
Pinout for the System Timing Slot, for the system timing slot pinout. Refer
to the Backplane Specifications section for the PXIe_SYNC_CTRL input
specifications.
By default, a high level detected by the backplane on the
PXIe_SYNC_CTRL pin causes a synchronous restart for the
PXIe_SYNC100 signal. On the next PXI_CLK10 edge, the
PXIe_SYNC100 signal restarts. This allows several chassis to have their
PXIe_SYNC100 in phase with each other. Refer to Figure 7 for timing
details with this method.
Figure 7. PXIe_SYNC100 at 3.33 MHz Using PXIe_SYNC_CTRL as Restart
10 MHz clock present No clock present PXI_CLK10, PXIe_CLK100 and
PXIe_SYNC100 all phase-locked to
System Timing Slot—PXI_CLK10_IN
10 MHz clock present 10 MHz clock present PXI_CLK10, PXIe_CLK100 and
PXIe_SYNC100 all phase-locked to
System Timing Slot—PXI_CLK10_IN
Table 1. Backplane External Clock Input Truth Table (Continued)
System Timing Slot
PXI_CLK10_IN
Rear Chassis Panel
10 MHz REF IN
Backplane PXI_CLK10,
PXIe_CLK100 and PXIe_SYNC100
PXI_CLK10
PXIe_SYNC_CTRL
PXIe_SYNC100
SYNC100 Divider
Restarted Here

18-Slot NI PXIe-1075 Backplane Installation Guide 10 ni.com
Mechanical Requirements
Mounting
Figure 8 shows the backplane dimensions. There are 40 holes available for
mounting with M2.5 hardware.
Use all mounting holes for proper backplane support.
Six mounting holes on top of the backplane have plated annular pads on the
back of the backplane. Use these mounting holes to connect the backplane
ground to the chassis in which the backplane is mounted. If you do not want
to connect the backplane ground to the chassis, use insulated washers at
these mounting holes. Refer to Figure 11 for the mounting hole positions.
For full backplane mounting and card cage dimensions, refer to the
CompactPCI Express PICMG EXP.0 R1.0 Specification.
Dimensions
Figure 8. Dimensions
1.00 in.
(25.40 mm)
0.148 in.
(3.76 mm)
5.916 in.
(150.27 mm)
0.122 in.
(3.09 mm)
0.972 in.
(24.68 mm)
0.162 in.
(4.11 mm)
0.800 in.
(20.32 mm)
16.56 in.
(420.65 mm)

©National Instruments 11 18-Slot NI PXIe-1075 Backplane Installation Guide
Cooling
Note National Instruments is not responsible for damage to the backplane if inadequate
cooling is used.
Airflow should be from the bottom to the top of the PXI modules. You must
determine the airflow requirements for your system based on the
PXI Hardware Specification.
The backplane must be adequately cooled to function reliably. Ensure that
the components shown in Figure 9 are kept below their maximum case
temperatures throughout the operating range.
Figure 9. Thermally Relevant Component Recommended Maximum
Operating Case Temperature (°C)
1 L5—125.00 °C
2U23—112.00 °C
3U12—116.00 °C
4U18—120.65 °C
5 U20—82.71 °C
6 U9—119.80 °C
7U43—113.24 °C
8U46—107.25 °C
9 U42—113.24 °C
10 U41—109.01 °C
11 U44—107.75 °C
12 U40—113.24 °C
13Q5—173.55 °C
14 Q3—173.55 °C
10
1
14
12 9 7811
6543
2
13

18-Slot NI PXIe-1075 Backplane Installation Guide 12 ni.com
Handling
Caution Be careful to avoid bending or otherwise damaging the pins on the backplane
connectors. Bent pins may cause functional failures or damage when the backplane is
powered.
Caution To protect both yourself and the backplane from electrical hazards, leave the
chassis powered off until you finish installing the PXI controller and modules.
Caution Electrostatic discharge can damage your equipment. To avoid such damage,
discharge the static built up on your body by touching a grounded metal object before
handling the PXI equipment. Then touch the antistatic plastic package containing the
backplane to a metal part of your PXI chassis before removing the backplane from the
packaging.
Electrical Requirements
PXI Connectors
The PXI and PXI Express connectors have pin descriptions defined in the
PXI Hardware Specification and PXI Express Hardware Specification.
Figure 10 shows the connectors.
Figure 10. PXI Connectors
1Card-Cage Thermistor Connectors(×4)
2Slot 1 (Controller Slot)
3Hybrid Peripheral Slots(2-5, 15-18)
4 PXI Express Peripheral Slots(6-9, 11-14)
5System Timing Slot (10)
233
4
45
1111

©National Instruments 13 18-Slot NI PXIe-1075 Backplane Installation Guide
Figure 11. Backplane Power, J500, and CLK10 Connectors
Power
Refer to the PXI Express Hardware Specification for power requirements
and to the specifications of the chosen power supply to determine the
minimum load required.
Connector J505
Connector J505 is the NI PXIe-1075 backplane power supply connector.
Figure 11 shows the J505 location. Refer to Table 2 for the pin
descriptions. Connector J505 consists of four large #8 pins (34-37) and nine
#12 pins (1-9) for power. There are also 24 #20 pins (10-33) for mixed
power and signaling. Table 2 also indicates which pins must be connected
for basic backplane operation.
Refer to the CompactPCI Express specification for details regarding
PS_ON# and PS_OK.
Caution Do not use the voltage sense pins (10, 18, and 25) to power the board. These pins
are connected by thin trace to the backplane center and are for voltage sensing only.
Providing current through these pins may damage the backplane. If your power supply has
voltage sensing, use these pins; otherwise, leave them unconnected. Pins with “power
plane” in the description are connected to the backplane’s internal power planes and are
suitable for carrying current.
1Plated Mounting Holes(×8)
2 Connector J500
3Connector J505
4 Connector J506
1
4
3
2
1
1

18-Slot NI PXIe-1075 Backplane Installation Guide 14 ni.com
Note Tyco Electronics manufactures the J505 mating connector, which you can order with
part number 6648167-1.
Note The connector SMBus pins are connected to the backplane SMBus, which the
CompactPCI Express specification defines. (The specification also defines uses and
addressing.) Improper use of the SMBus could result in system controller malfunctions.
There are three SMBus slave devices on the NI PXIe-1075 backplane. The
Backplane Descriptor EEPROM is at slave address A4Has defined by the
CompactPCI Express specification, and the backplane clocking CPLD is at
slave address 5AH. There is a temperature monitoring device at slave
address 5CH. If you must connect an SMBus slave device to the
J505 SMBus pins, use slave address 58H.

©National Instruments 15 18-Slot NI PXIe-1075 Backplane Installation Guide
Table 2. Connector J505 Pin Descriptions
Connector Pin Signal Description
Required
for Basic
Power Up
1+5V +5 V power plane Yes
2GND Ground plane Yes
3GND Ground plane Yes
4+3.3V +3.3 V power plane Yes
5+12V +12 V power plane Yes
6GND Ground plane Yes
7GND Ground plane Yes
8+12V +12 V power plane Yes
9GND Ground plane Yes
10 +12V_SENSE +12 V sense only, no power No
11 GND Ground plane Yes
12 -12V -12 V power plane Yes
13 GND Ground plane No
14 OVERTEMP# Alert of over-temperature
condition in card cage
No
15 GND Ground plane No
16 LED1 J500—pin 3 No
17 LED2 J500—pin 4 No
18 +5V_SENSE +5 V sense only, no power No
19 GND Ground plane No
20 GND Ground plane No
21 GND Ground plane No
22 SMBCLK Backplane SMBus clock No
23 SMBDAT Backplane SMBus data No
24 SMBALERT# Backplane SMBus alert# No
25 +3.3V_SENSE +3.3 V sense only,
no power
No
26 GND Ground plane Yes
27 -12V -12 V power plane Yes
28 5VAUX 5VAUX power plane Yes
123
456
789
10 15
16 21
22 27
28 33
34 35
36 37

18-Slot NI PXIe-1075 Backplane Installation Guide 16 ni.com
Connector J506
Connector J506 is for interfacing with the backplane PXI_CLK10 circuitry.
Figure 12 shows the J506 connector location. Positronic manufactures the
J506 mating connector, which you can order with part number
CBD7W2M2000Z-759.1.
Figure 12. J506 Connector
Connector J500
Use connector J500 in conjunction with J505 for interfacing with an inhibit
switch and LED. You do not need to connect anything to J500 for basic
backplane power up. Refer to Table 3 for the pin descriptions. The power
button (PWRBTN#) signal is a momentary pushbutton signal that tells the
system controller to enable or inhibit the power supply. You can use signals
LED1 and LED2 to drive a bicolor LED in the power switch, but you also
can use these signals to carry another digital signal.
29 GND Ground plane Yes
30 PS_ON# From system
slot J20—pin D2
No
31 12V_FAN To test point E8 No
32 GND Ground plane Yes
33 PS_OK To system slot from
power supply
Yes
34 GND Ground plane Yes
35 GND Ground plane Yes
36 +3.3V +3.3 V power plane Yes
37 +5V +5 V power plane Yes
Table 2. Connector J505 Pin Descriptions (Continued)
Connector Pin Signal Description
Required
for Basic
Power Up
Ground
10 MHz
OUT
10 MHz
IN

©National Instruments 17 18-Slot NI PXIe-1075 Backplane Installation Guide
Connectors J1, J2, J5, and J3
Use these connectors for four thermistors to monitor the card-cage
temperature. You can use signal OVERTEMP# on J505 as an alarm
indicating when the card-cage temperature exceeds 90 °C when used in
conjunction with the four thermistors.
Note Use a Sensor Scientific KWM502C-6 or similar thermistor with these connectors.
Note The mating connector for J1, J2, J5, and J3 is Molex part number 50-57-9402.
Backplane Specifications
Size......................................................... 3U-sized; one system slot
(with three system expansion
slots) and 17 peripheral slots.
Compliant with IEEE 1101.10
mechanical packaging.
PXI Express specification
compliant.
Accepts both PXI Express and
CompactPCI (PICMG 2.0 R 3.0)
3U modules.
Backplane bare-board material .............. UL 94 V-0 Recognized
Backplane connectors ............................ Conforms to IEC 917 and
IEC 1076-4-101, and are
UL 94 V-0 rated
Table 3. Connector J500 Pin Descriptions
Connector Pin Signal Description
1PWRBTN# Input to system
slot J20—pin F2
2GND Ground plane
3LED1 J505—pin 16
4LED2 J505—pin 17
1
2
3
4
J500

18-Slot NI PXIe-1075 Backplane Installation Guide 18 ni.com
System Synchronization Clock (PXI_CLK10, PXIe_CLK100,
PXIe_SYNC100) Specifications
10 MHz System Reference Clock: PXI_CLK10
Maximum slot-to-slot skew ....................500 ps
Accuracy.................................................±25 ppm max (guaranteed over
the operating temperature range)
Maximum jitter .......................................5 ps RMS phase-jitter
(10Hz-1MHzrange)
Duty-factor..............................................45%-55%
Unloaded signal swing............................3.3 V ±0.3 V
Note For other specifications, refer to the PXI-1 Hardware Specification.
100 MHz System Reference Clock: PXIe_CLK100 and
PXIe_SYNC100
Maximum slot-to-slot skew ....................100 ps
Accuracy.................................................±25 ppm max (guaranteed over
the operating temperature range)
Maximum jitter .......................................3 ps RMS phase-jitter
(10 Hz-12 kHz range)
2 ps RMS phase-jitter
(12kHz-20MHzrange)
Duty-factor for PXIe_CLK100...............45%-55%
Absolute single-ended voltage swing
(When each line in the differential pair
has 50 Ωtermination to 1.30 V
or Thévenin equivalent)..........................400-1000 mV
Note For other specifications, refer to the PXI-5 PXI Express Hardware Specification.

©National Instruments 19 18-Slot NI PXIe-1075 Backplane Installation Guide
External 10 MHz Reference Out (on J506)
Accuracy ................................................ ±25 ppm max (guaranteed over
the operating temperature range)
Maximum jitter ...................................... 5 ps RMS phase-jitter
(10Hz-1MHzrange)
Output amplitude.................................... 1 VPP ±20% square-wave
into 50 Ω
2 VPP unloaded
Output impedance .................................. 50 Ω± 5 Ω
External Clock Source
Frequency............................................... 10 MHz ±100 PPM
Input amplitude
J506................................................. 200 mVPP to 5 VPP square-wave
or sine-wave
System timing slot
PXI_CLK10_IN.............................. 5 V or 3.3 V TTL signal
J506 input impedance............................. 50 Ω± 5 Ω
Maximum jitter introduced
by backplane .......................................... 1 ps RMS phase-jitter
(10Hz-1MHzrange)
PXIe_SYNC_CTRL
VIH .......................................................... 2.0-5.5 V
VIL .......................................................... 0-0.8 V
PXI Star Trigger
Maximum slot-to-slot skew ................... 250 ps
Backplane characteristic impedance ...... 65 Ω±10%
Note For PXI slot to PXI Star mapping, refer to the System Timing Slot section of
Chapter 1, Getting Started, in the NI PXIe-1075 User Manual.
Note For other specifications, refer to the PXI-1 Hardware Specification.

18-Slot NI PXIe-1075 Backplane Installation Guide 20 ni.com
PXI Differential Star Triggers
(PXIe-DSTARA, PXIe-DSTARB, PXIe-DSTARC)
Maximum slot-to-slot skew ....................150 ps
Maximum differential skew....................25 ps
Backplane differential impedance ..........100 Ω±10%
Note For PXIe slot to PXI_DSTAR mapping, refer to the System Timing Slot section of
Chapter 1, Getting Started, in the NI PXIe-1075 User Manual.
Note For other specifications, the NI PXIe-1075 complies with the PXI-5 PXI Express
Hardware Specification.
Pinouts
This section describes the connector pinouts for the NI PXIe-1075 chassis
backplane.
Table 4 shows the XP1 connector pinout for the System Controller slot.
Table 5 shows the XP2 Connector Pinout for the System Controller slot.
Table 6 shows the XP3 Connector Pinout for the System Controller slot.
Table 7 shows the XP4 Connector Pinout for the System Controller slot.
Table 8 shows the TP1 Connector Pinout for the System Controller slot.
Table 9 shows the TP2 Connector Pinout for the System Timing slot.
Table 10 shows the XP3 Connector Pinout for the System Timing slot.
Table 11 shows the XP4 Connector Pinout for the System Timing slot.
Table 12 shows the P1 connector pinout for the Hybrid peripheral slots.
Table 13 shows the XP3 Connector Pinout for the Hybrid peripheral slots.
Table 14 shows the XP4 Connector Pinout for the Hybrid peripheral slots.
For more detailed information, refer to the PXI-5 PXI Express Hardware
Specification, Revision 2.0. Contact the PXI Systems Alliance for a copy
of the specification.